Hi Conor, On Sat, Nov 12, 2022 at 8:31 AM Conor Dooley <co...@kernel.org> wrote: > > On Thu, Nov 10, 2022 at 12:18:44AM +0100, Philippe Mathieu-Daudé wrote: > > Hi Conor, > > > > On 9/11/22 20:08, Conor Dooley wrote: > > > From: Conor Dooley <conor.doo...@microchip.com> > > > > > > @@ -168,6 +170,10 @@ static void mchp_pfsoc_ioscb_realize(DeviceState > > > *dev, Error **errp) > > > "mchp.pfsoc.ioscb.cfg", > > > IOSCB_SUBMOD_REG_SIZE); > > > memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg); > > > + memory_region_init_io(&s->ccc, OBJECT(s), &mchp_pfsoc_dummy_ops, s, > > > + "mchp.pfsoc.ioscb.ccc", IOSCB_CCC_REG_SIZE); > > > + memory_region_add_subregion(&s->container, IOSCB_CCC_BASE, &s->ccc); > > > > Unrelated but using the TYPE_UNIMPLEMENTED_DEVICE would ease tracing all > > these block accesses, as the block name would appear before the > > address/size. See for example aspeed_mmio_map_unimplemented(); > > Certainly looks like a nice idea, and I gave it a go but kept running > into issues due to my lack of understanding of QEMU :) I'm going to add > this to my todo pile - while I have a v2 of this lined up, I'd rather > not hold up adding the regions that prevent booting Linux etc as I > fumble around trying to understand the hierarchy of devices required to > set up something similar to your aspeed example. >
Do you plan to bring QEMU support to the latest MSS_LINUX configuration [1] Currently QEMU is supporting the MSS_BAREMETAL configuration. Do you think it makes sense to support both? [1] https://github.com/polarfire-soc/icicle-kit-reference-design Regards, Bin
