On Sat, Sep 24, 2022 at 4:10 PM Bin Meng wrote:
>
> On Fri, Sep 23, 2022 at 4:09 AM Marc-André Lureau
> wrote:
> >
> > Hi
> >
> > On Tue, Sep 20, 2022 at 2:33 PM Bin Meng wrote:
> >>
> >> From: Xuzhou Cheng
> >>
> >> The combination of GENERIC_WRITE and FILE_SHARE_READ options does
> >> not all
Hi Paolo,
On Tue, Sep 13, 2022 at 5:52 PM Marc-André Lureau
wrote:
>
> Hi
>
> On Wed, Aug 24, 2022 at 12:52 PM Bin Meng wrote:
>>
>> From: Bin Meng
>>
>> The maximum number of wait objects for win32 should be
>> MAXIMUM_WAIT_OBJECTS, not MAXIMUM_WAIT_OBJECTS + 1.
>>
>> Signed-off-by: Bin Meng
Qemu currently emulates a 32-bit CPU only, and crashes with this error
when it faces a 64-bit load (e.g. "ldd 0(r26),r0") or 64-bit store
(e.g. "std r26,0(r26)") instruction in the guest:
ERROR:../qemu/tcg/tcg-op.c:2822:tcg_canonicalize_memop: code should not be
reached
Fix this by adding check
The patch adds "show_menubar" command line option for GTK UI similar to
"show_tabs". This option allows to hide menu bar initially, it still can
be toggled by shortcut and other shortcuts still work.
(First-time contributor)
Signed-off-by: Bryce Mills
---
qapi/ui.json| 6 +-
qemu-optio
On 9/20/22 17:25, Paolo Bonzini wrote:
This adds another kind of weirdness when you thought you had seen it all:
an opcode byte that comes_after_ the address, not before. It's not
worth adding a new X86_SPECIAL_* constant for it, but it's actually
not unlike VCMP; so, forgive me for exploiting
On 9/20/22 17:25, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/fpu_helper.c | 78 ++--
1 file changed, 75 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 9/20/22 17:25, Paolo Bonzini wrote:
These are exactly the same as the non-VEX version, but one has to be careful
that only VEX.L=0 is allowed.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 25 +
target/i386/tcg/emit.c.inc | 20 +++
On 9/20/22 17:25, Paolo Bonzini wrote:
Here the code is a bit uglier due to the truncation and extension
of registers to and from 32-bit. There is also a mistake in the
manual with respect to the size of the memory operand of CVTPS2PI
and CVTTPS2PI, reported by Ricky Zhou.
Signed-off-by: Paolo
On 9/20/22 17:25, Paolo Bonzini wrote:
These are mostly moves, and yet are a total pain. The main issue
is that:
1) some instructions are selected by mod==11 (register operand)
vs. mod=00/01/10 (memory operand)
2) stores to memory are two-operand operations, while the 3-register
and load-from-
On 9/20/22 17:24, Paolo Bonzini wrote:
There are several special cases here:
1) extending moves have different widths for the helpers vs. for the
memory loads, and the width for memory loads depends on VEX.L too.
This is represented by X86_SPECIAL_AVXExtMov.
2) some instructions, such as variab
On 9/20/22 17:24, Paolo Bonzini wrote:
+static void gen_pmovmskb_vec(unsigned vece, TCGv_vec d, TCGv_vec s)
+{
+TCGv_vec t = tcg_temp_new_vec_matching(d);
+TCGv_vec m = tcg_constant_vec_matching(d, MO_8, 0x80);
+
+/* See above */
+tcg_gen_and_vec(vece, d, s, m);
+tcg_gen_shli_
On 9/20/22 17:24, Paolo Bonzini wrote:
The more complicated operations here are insertions and extractions.
Otherwise, there are just more entries than usual because the PS/PD/SS/SD
variations are encoded in the opcode rater than in the prefixes.
These three-byte opcodes also include AVX new ins
On 9/20/22 17:24, Paolo Bonzini wrote:
Three-byte opcodes from the 0F3Ah area all have an immediate byte which
is usually unsigned. Clarify in the helper code that it is unsigned;
the new decoder treats immediates as signed by default, and seeing
an intN_t in the prototype might give the wrong i
On 9/20/22 17:24, Paolo Bonzini wrote:
For LDDQU, using gen_load_sse directly might corrupt the register if
the second part of the load fails.
Surely LDDQU is not unique in this? I would think ldo/ldy both need fixing to load to
temps first.
Anyway, this patch is
Reviewed-by: Richard Hender
On 9/20/22 17:24, Paolo Bonzini wrote:
+static TCGv_ptr make_imm8u_xmm_vec(uint8_t imm, int vec_len)
+{
+MemOp ot = vec_len == 16 ? MO_128 : MO_256;
+TCGv_i32 imm_v = tcg_constant8u_i32(imm);
+TCGv_ptr ptr = tcg_temp_new_ptr();
+
+tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State,
On 9/20/22 17:24, Paolo Bonzini wrote:
+static void decode_0F78(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
uint8_t *b)
+{
+static const X86OpEntry opcodes_0F78[4] = {
+{},
+X86_OP_ENTRY3(EXTRQ_i, V,x, None,None, I,w, cpuid(SSE4A)),
+{},
+X86_
On 9/20/22 17:24, Paolo Bonzini wrote:
These are mostly floating-point SSE operations. The odd ones out
are MOVMSK and CVTxx2yy, the others are straightforward.
Unary operations are a bit special in AVX because they have 2 operands
for PD/PS operands (VEX. must be b), and 3 operands for
On 9/20/22 17:24, Paolo Bonzini wrote:
These are more simple integer instructions present in both MMX and SSE/AVX,
with no holes that were later occupied by newer instructions.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 28
target/i386/tcg
On 9/20/22 17:24, Paolo Bonzini wrote:
+static void gen_MOVD_to(DisasContext *s, CPUX86State *env, X86DecodedInsn
*decode)
+{
+MemOp ot = decode->op[2].ot;
+int vec_len = vector_len(s, decode);
+int lo_ofs = vector_elem_offset(&decode->op[0], ot, 0);
+
+tcg_gen_gvec_dup_imm(MO_64
On 9/20/22 17:24, Paolo Bonzini wrote:
Many SSE and AVX instructions are only valid with specific prefixes
(none, 66, F3, F2). Introduce a direct way to encode this in the
decoding table to avoid using decode groups too much.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc |
On 9/20/22 17:24, Paolo Bonzini wrote:
+uint8_t vex_class:8;
As before, "unsigned", so gdb doesn't present this as a character.
Otherwise,
Reviewed-by: Richard Henderson
r~
On 9/23/22 21:47, Lucas Mateus Castro(alqotel) wrote:
+static void do_xvtstdc_vec(unsigned vece, TCGv_vec t, TCGv_vec b, int64_t imm)
+{
+TCGv_vec match = tcg_const_ones_vec_matching(t);
+TCGv_vec temp;
+TCGv_vec mask;
+uint64_t exp_msk = (vece == MO_32) ? (uint32_t)EXP_MASK_SP :
Hi,
thanks for the remarks so far. Ping?
https://patchew.org/QEMU/20220911181840.8933-1-arwed.me...@gmx.de/
Any more comments? What's next?
The v2 in the cover letter head line is a c&p error by the way. It's
really v3 and otherwise looks ok in patchew. Not sure if/how to fix this.
Regards
From: Bin Meng
At present there are two callers of get_tmp_filename() and they are
inconsistent.
One does:
/* TODO: extra byte is a hack to ensure MAX_PATH space on Windows. */
char *tmp_filename = g_malloc0(PATH_MAX + 1);
...
ret = get_tmp_filename(tmp_filename, PATH_MAX + 1);
On 24/09/2022 14:09, BALATON Zoltan wrote:
On Sat, 17 Sep 2022, BALATON Zoltan wrote:
This series includes some clean ups to mac_newworld and mac_oldworld
to make them a bit simpler and more readable, It also removes the
shared mac.h file that turns out was more of a random collection of
unrela
On 9/20/22 17:24, Paolo Bonzini wrote:
+static void gen_load_sse(DisasContext *s, TCGv temp, MemOp ot, int dest_ofs,
bool aligned)
+{
+if (ot == MO_8) {
+gen_op_ld_v(s, MO_8, temp, s->A0);
+tcg_gen_st8_tl(temp, cpu_env, dest_ofs);
+} else if (ot == MO_16) {
switch + def
On 9/20/22 17:24, Paolo Bonzini wrote:
The new decoder is based on three principles:
- use mostly table-driven decoding, using tables derived as much as possible
from the Intel manual. Centralizing the decode the operands makes it
more homogeneous, for example all immediates are signed.
On 9/20/22 17:24, Paolo Bonzini wrote:
ldq takes a pointer to the first byte to load the 64-bit word in;
ldo takes a pointer to the first byte of the ZMMReg. Make them
consistent, which will be useful in the new SSE decoder's
load/writeback routines.
Signed-off-by: Paolo Bonzini
---
target/i3
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1193
The commit "Use io_uring_register_ring_fd() to skip fd operations" broke
when booting a guest with iothread and io_uring. That is because the
io_uring_register_ring_fd() call is made from the main thread instead of
IOThread where io_urin
On 9/23/22 21:47, Lucas Mateus Castro(alqotel) wrote:
+return (match != 0) ? 1 : 0;\
?: operator is redundant. Otherwise,
Reviewed-by: Richard Henderson
r~
On 9/23/22 21:47, Lucas Mateus Castro(alqotel) wrote:
+static void do_xvcpsgn_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
+{
+TCGv_vec most_significant_bit = tcg_temp_new_vec_matching(t);
+uint64_t msb = (vece == MO_32) ? SGN_MASK_SP : SGN_MASK_DP;
+tcg_gen_dupi_vec(vece, m
On 9/23/22 21:47, Lucas Mateus Castro(alqotel) wrote:
+static void xv_msb_op1(unsigned vece, TCGv_vec t, TCGv_vec b,
+ void (*tcg_gen_op_vec)(unsigned, TCGv_vec, TCGv_vec,
TCGv_vec))
+{
+TCGv_vec most_significant_bit = tcg_temp_new_vec_matching(t);
+uint64_t msb = (vece =
On 9/23/22 21:47, Lucas Mateus Castro(alqotel) wrote:
+TCGv_vec one = tcg_temp_new_vec_matching(t);
+tcg_gen_dupi_vec(vece, one, 1);
+tcg_gen_or_vec(vece, tmp, a, b);
+tcg_gen_and_vec(vece, tmp, tmp, one);
tcg_constant_vec_matching. With that,
Reviewed-by: Richard Henderson
On 9/23/22 21:47, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Moved VABSDUB, VABSDUH and VABSDUW to decodetree and use gvec to
translate them.
vabsdub:
reptloopmaster patch
8 12500 0,03601600 0,00688500 (-80.9%)
25 40000
On 9/23/22 21:47, Lucas Mateus Castro(alqotel) wrote:
+/* MO_32 is 2, so 2 iteractions for MO_32 and 3 for MO_64 */
+for (i = 0; i < vece; i++) {
+tcg_gen_shri_vec(vece, tmp, b, (4 << (vece - i)));
+tcg_gen_xor_vec(vece, b, tmp, b);
+}
+tcg_gen_dupi_vec(vece, tmp,
On 9/23/22 21:47, Lucas Mateus Castro(alqotel) wrote:
+static bool do_vx_vaddsubcuw(DisasContext *ctx, arg_VX *a, int add)
+{
+static const TCGOpcode vecop_list[] = {
+INDEX_op_cmp_vec, 0
+};
+
+static const GVecGen3 op[] = {
+{
+.fniv = gen_VSUBCUW,
+
On 9/23/22 21:47, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Moved the instructions VNEGW and VNEGD to decodetree and used gvec to
decode it.
vnegw:
reptloopmaster patch
8 12500 0,01053200 0,00548400 (-47.9%)
25 40000,0
On 9/23/22 21:47, Lucas Mateus Castro(alqotel) wrote:
+static void gen_VADDCUW(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
+{
+tcg_gen_not_vec(vece, a, a);
+tcg_gen_cmp_vec(TCG_COND_LTU, vece, t, a, b);
+tcg_gen_and_vec(vece, t, t, tcg_constant_vec_matching(t, vece, 1));
+}
I
When the emulation stops with a hard exception it's very useful for
debugging purposes to dump the current guest memory layout (like
/proc/self/maps) beside the CPU registers.
The open_self_maps() function provides such a memory dump, but since
it's located in the syscall.c file various changes (a
On 9/23/22 21:47, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
This patch moves VMHADDSHS and VMHRADDSHS to decodetree I couldn't find
a satisfactory implementation with TCG inline.
vmhaddshs:
reptloopmaster patch
8 12500 0,02983400
On 9/23/22 21:47, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
This patch moves VMLADDUHM to decodetree a creates a gvec implementation
using mul_vec and add_vec.
reptloopmaster patch
8 12500 0,01810500 0,00903100 (-50.1%)
25
On Thu, Sep 22, 2022 at 5:12 PM Alberto Campinho Faria
wrote:
>
> On Thu, Sep 22, 2022 at 9:49 AM Paolo Bonzini wrote:
> > Callers of coroutine_fn must be coroutine_fn themselves, or the call
> > must be within "if (qemu_in_coroutine())". Apply coroutine_fn to
> > functions where this holds.
> >
Queued, thanks.
Paolo
On Sat, 17 Sep 2022, BALATON Zoltan wrote:
This series includes some clean ups to mac_newworld and mac_oldworld
to make them a bit simpler and more readable, It also removes the
shared mac.h file that turns out was more of a random collection of
unrelated things. Getting rid of this mac.h improve
On 24/9/22 13:45, Bin Meng wrote:
From: Bin Meng
At present there are two callers of get_tmp_filename() and they are
inconsistent.
One does:
/* TODO: extra byte is a hack to ensure MAX_PATH space on Windows. */
char *tmp_filename = g_malloc0(PATH_MAX + 1);
...
ret = get_tm
On 9/24/22 13:44, Nicholas Piggin wrote:
This partially reverts commit 9dc20cc37db9 ("target/ppc: Simplify
powerpc_excp_booke"), which removed DOORI and DOORCI interrupts.
Without this patch, a -cpu e5500 -smp 2 machine booting Linux
crashes with:
qemu: fatal: Invalid PowerPC exception 36. Ab
Currently only base and size are set on initial bank creation and bcr
value is computed on mapping the region. Set bcr at init so the bcr
encoding method becomes local to the controller model and mapping and
unmapping can operate on the bank so it can be shared between
different controller models.
On 24/9/22 01:21, Claudio Fontana wrote:
if QEMU is configured with modules enabled, it is possible that the
load of an accelerator module will fail.
Abort in this case, relying on module_object_class_by_name to report
the specific load error if any.
Signed-off-by: Claudio Fontana
Reviewed-by:
Rename functions to avoid name clashes when moving the DDR2 controller
model currently called ppc440_sdram to ppc4xx_devs. This also more
clearly shows which function belongs to which model.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc405_boards.c | 2 +-
h
This function is only used by the ppc4xx memory controller models so
it can be made static.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc4xx_devs.c| 62 -
hw/ppc/ppc4xx_sdram.c | 61
include/hw/ppc/ppc4xx.h | 2
Rename the sdram local state variable to s in dcr read/write functions
and reset methods for better readability and to match realize methods.
Other places not converted will be changed or removed in subsequent
patches.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc
In order to move PPC4xx SDRAM controller models together move out the
DDR2 controller model from ppc440_uc.c into a new ppc4xx_sdram.c file.
Signed-off-by: BALATON Zoltan
---
hw/ppc/meson.build| 3 +-
hw/ppc/ppc440_uc.c| 328
hw/ppc/ppc4xx_sdram
Use the generic bank handling introduced in previous patch in the DDR
SDRAM controller too. This also fixes previously broken region unmap
due to sdram_ddr_unmap_bcr() ignoring container region so it crashed
with an assert when the guest tried to disable the controller.
Signed-off-by: BALATON Zolt
These are used by both the SDRAM controller model and system DCRs. In
preparation to move SDRAM controller in its own file move these macros
to the ppc4xx.h header.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 4
include/hw/ppc/ppc4xx.h | 4
2 files changed, 4 insertions
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc4xx_devs.c | 352
hw/ppc/ppc4xx_sdram.c | 365 ++
2 files changed, 365 insertions(+), 352 deletions(-)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 12af
This resolves the target_ulong dependency that's clearly wrong and was
also noted in a fixme comment.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc4xx_sdram.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdr
Do not exit from ppc4xx_sdram_banks() but report error via an errp
parameter instead.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc4xx_sdram.c | 28 +++-
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdram
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440_uc.c | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 8eae4ad9f0..900b7ab998 100644
--- a/hw/ppc/ppc440_uc.c
++
Change the ppc440_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr2. This is mostly
modelling the DDR2 SDRAM controller found in the 460EX (used on the
sam460ex board). Newer SoCs (regardless of their PPC core, e.g. 405EX)
may have this controller but we on
Move the check for valid memory sizes from board to sdram controller
init. This adds the missing valid memory sizes of 4 GiB, 16 and 8 MiB
to the DoC and the board now only checks for additional restrictions
imposed by its firmware then sdram init checks for valid sizes for SoC.
Signed-off-by: BAL
Remove the do_init parameter of ppc440_sdram_init and enable SDRAM
controller from the board. Firmware does this so it may only be needed
when booting with -kernel without firmware but we enable SDRAM
unconditionally to preserve previous behaviour.
Signed-off-by: BALATON Zoltan
---
v5: Add functi
Rename local sdram variable in ppc440_sdram_init to s for readability.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
---
hw/ppc/ppc440_uc.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440
Constants that are written zero padded for no good reason are hard to
read, it's easier to see what is meant if it's just 0 or 1 instead.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc4xx_devs.c | 40
1 file changed, 20
To allow removing the do_init hack we need to improve the DDR2 SDRAM
controller model to handle the enable/disable bit that it ignored so
far.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 34 --
1 file changed, 32 insertions(+), 2 deletions(-)
diff --gi
Change the ppc4xx_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr. This is mostly
modelling the DDR SDRAM controller found in the 440EP (used on the
bamboo board) but also backward compatible with the older DDR
controllers on some 405 SoCs so we also use i
Remove unneeded parenthesis around case labels.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 0a41274d63..24623ebe0c 100644
--- a/hw/ppc/ppc440_uc.c
+++
Instead of storing sdram bank parameters in unrelated arrays put them
in a struct so it's clear they belong to the same bank and simplify
the state struct using this bank type.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440_uc.c | 49 +--
This is the end of the QOMify series started by Cédric. This series
handles the SDRAM controller models to clean them up, QOMify and unify
them and at least partially clean up the mess that has accumulated
around these in the past. This includes the not yet merged patches
from the last series and n
Instead of checking if memory size is valid in board code move this
check to ppc4xx_sdram_init() as this is a restriction imposed by the
SDRAM controller.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc405.h | 2 --
hw/ppc/ppc405_boards.c | 10
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
---
hw/ppc/ppc440_bamboo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index edfb8c9709..7ec7c7c43d 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
The do_init parameter of ppc4xx_sdram_init() is used to map memory
regions that is normally done by the firmware by programming the SDRAM
controller. Do this from board code emulating what firmware would do
when booting a kernel directly from -kernel without a firmware so we
can get rid of this do_
Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead
of the separate arrays and adjust ppc4xx_sdram_init() and
ppc440_sdram_init() accordingly as well as machines using these.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
---
v2: Use pointer for ram_banks in the pr
In ppc4xx_sdram_init() the struct is allocated with g_new0() so no
need to clear its elements. In the bamboo machine init memset can be
replaced with array initialiser which is shorter.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_bamboo.c | 6 ++
hw/ppc/ppc4xx_devs.c | 8 ++--
2 fi
On 4/8/22 13:55, Anton Johansson via wrote:
From: Paolo Montesel
Missing the rationale. "The idef-parser will use it with IMM_NPC".
But I feel I'm missing something, what is the diff between IMM_PC/IMM_NPC?
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
Reviewed-by: R
On 4/8/22 13:55, Anton Johansson via wrote:
From: Niccolò Izzo
These helpers will be employed by the idef-parser generated code, to
correctly implement instruction semantics. "Helper" functions, in the
context of this patch, refers to functions which provide a manual TCG
implementation of certa
On 4/8/22 13:55, Anton Johansson via wrote:
From: Paolo Montesel
Make certain helper functions non-static, making them available outside
genptr.c. These functions are required by code generated by the
idef-parser.
This commit also makes some functions in op_helper.c non-static in order
to avoi
On 4/8/22 13:55, Anton Johansson via wrote:
From: Paolo Montesel
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
Acked-by: Richard Henderson
Reviewed-by: Taylor Simpson
---
target/hexagon/genptr.c | 24 +---
target/hexagon/macros.h | 2 +-
2 file
From: Bin Meng
At present there are two callers of get_tmp_filename() and they are
inconsistent.
One does:
/* TODO: extra byte is a hack to ensure MAX_PATH space on Windows. */
char *tmp_filename = g_malloc0(PATH_MAX + 1);
...
ret = get_tmp_filename(tmp_filename, PATH_MAX + 1);
The hppa target requires a much bigger stack than many other targets,
and the Linux kernel allocates 80 MB by default for it.
This patch increases the guest stack for hppa to 80MB, and prevents
that this default stack size gets reduced by a lower stack limit on the
host.
Since the stack grows upw
The xtensa platform has a value of 0x10 for PROT_SEM.
Signed-off-by: Helge Deller
---
linux-user/syscall_defs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 85b0f33e91..1e3577bfa5 100644
--- a/linux-user/syscall_d
We don't emulate a preemptive kernel on this level, and the hppa architecture
doesn't allow context switches on the gateway page. So we always have to return
to sc_iaoq[] and not to gr[31].
This fixes the remaining random segfaults which still occured.
Signed-off-by: Helge Deller
---
linux-user/
Signed-off-by: Helge Deller
---
linux-user/strace.list | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/linux-user/strace.list b/linux-user/strace.list
index da8c1bf34e..bfef568d18 100644
--- a/linux-user/strace.list
+++ b/linux-user/strace.list
@@ -285,10 +285,10 @@
{ TAR
In Linux kernel v5.18 the vDSO for signal trampoline was added.
This code mimiks the bare minimum of this vDSO and thus avoids that the
parisc emulation needs executable stacks.
Signed-off-by: Helge Deller
---
linux-user/hppa/signal.c| 41 +
linux-user/hpp
The hppa platform uses an upwards-growing stack and required in Linux
kernels < 5.18 an executable stack for signal processing. For that some
executables and libraries are marked to have an executable stack, for
which glibc uses the mprotect() syscall to mark the stack like this:
mprotect(xfa
The stack-overflow check when building the "grep" debian package fails
on the debian hppa target. Reason is, that the guard page at the top
of the stack (which is added by qemu) prevents the fault handler in the
grep program to properly detect the stack overflow.
The Linux kernel on a physical mac
Some additional patches for linux-user, which mostly target
the hppa platform.
This series is on top of my previous posted patch series.
Please review.
Helge
Helge Deller (7):
linux-user: Fix TARGET_PROT_SEM for XTENSA
linux-user: Add proper strace format strings for
getdents()/getdents6
This partially reverts commit 9dc20cc37db9 ("target/ppc: Simplify
powerpc_excp_booke"), which removed DOORI and DOORCI interrupts.
Without this patch, a -cpu e5500 -smp 2 machine booting Linux
crashes with:
qemu: fatal: Invalid PowerPC exception 36. Aborting
Signed-off-by: Nicholas Piggin
---
On 9/22/22 09:29, Markus Armbruster wrote:
Philippe Mathieu-Daudé writes:
On 8/9/22 21:40, Daniel Henrique Barboza wrote:
To save the FDT blob we have the '-machine dumpdtb=' property.
With this property set, the machine saves the FDT in and exit.
The created file can then be converted to
Hi Thomas,
On Sat, Sep 10, 2022 at 8:32 AM Bin Meng wrote:
>
> On Sat, Sep 10, 2022 at 12:32 AM Thomas Huth wrote:
> >
> > On 08/09/2022 15.28, Bin Meng wrote:
> > > From: Bin Meng
> > >
> > > At present the prerequisite packages for 64-bit and 32-bit builds
> > > are slightly different. Let's
On Sat, 24 Sept 2022 at 00:42, Patrick Venture wrote:
> On Thu, Sep 22, 2022 at 8:21 PM Jason Wang wrote:
>>
>> On Thu, Sep 22, 2022 at 8:35 PM Peter Maydell
>> wrote:
>> > A question to which I don't know the answer: if the guest writes to
>> > the device to change the MAC address, should that
On Fri, Sep 23, 2022 at 4:09 AM Marc-André Lureau
wrote:
>
> Hi
>
> On Tue, Sep 20, 2022 at 2:33 PM Bin Meng wrote:
>>
>> From: Xuzhou Cheng
>>
>> The combination of GENERIC_WRITE and FILE_SHARE_READ options does
>> not allow the same file to be opened again by CreateFile() from
>> another QEMU
On Fri, Sep 23, 2022 at 3:39 AM Marc-André Lureau
wrote:
>
> Hi
>
> On Tue, Sep 20, 2022 at 2:17 PM Bin Meng wrote:
>>
>> From: Bin Meng
>>
>> At present get_tmp_filename() has platform specific implementations
>> to get the directory to use for temporary files. Switch over to use
>> g_get_tmp_d
On Fri, Sep 23, 2022 at 4:18 AM Marc-André Lureau
wrote:
>
> Hi
>
> On Tue, Sep 20, 2022 at 3:37 PM Bin Meng wrote:
>>
>> From: Bin Meng
>>
>> Now that we have fixed various test case issues as seen when running
>> on Windows, let's enable the qtest build on Windows.
>>
>> Signed-off-by: Bin Men
From: Bin Meng
At present there are two callers of get_tmp_filename() and they are
inconsistent.
One does:
/* TODO: extra byte is a hack to ensure MAX_PATH space on Windows. */
char *tmp_filename = g_malloc0(PATH_MAX + 1);
...
ret = get_tmp_filename(tmp_filename, PATH_MAX + 1);
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