On Tue, Jan 18, 2022 at 11:24 AM Alistair Francis wrote:
>
> On Tue, Jan 18, 2022 at 3:27 PM Anup Patel wrote:
> >
> > On Tue, Jan 18, 2022 at 10:50 AM Alistair Francis
> > wrote:
> > >
> > > On Sat, Jan 15, 2022 at 2:18 AM Anup Patel
> > > wrote:
> > > >
> > > > Currently, we have to use Ope
Anup Patel 於 2022年1月17日 週一 下午10:18寫道：
> From: Anup Patel
>
> The RISC-V AIA (Advanced Interrupt Architecture) defines a new
> interrupt controller for wired interrupts called APLIC (Advanced
> Platform Level Interrupt Controller). The APLIC is capabable of
> forwarding wired interupts to RISC-V
On 1/17/22 13:51, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé
>
> Since commit 292e13142d2, dma_buf_rw() returns a MemTxResult type.
> Do not discard it, return it to the caller. Pass the previously
> returned value (the QEMUSGList residual size, which was rarely used)
> as an op
On 1/10/22 18:51, Alex Bennée wrote:
> We do mention the limitation of single parenthood for
> memory_region_add_subregion but lets also make it clear how aliases
> help solve that conundrum.
>
> Signed-off-by: Alex Bennée
> ---
> docs/devel/memory.rst | 14 +-
> 1 file changed, 9 in
On 1/11/22 19:42, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (10):
> stubs: Restrict fw_cfg to system emulation
> hw/nvram: Restrict fw_cfg QOM interface to sysemu and tools
> hw/pci: Restrict pci-bus stub to sysemu
> hw/pci: Document pci_dma_map()
> hw/dma: Remove CONFIG_USE
On 9/5/21 01:10, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (2):
> memory: Split mtree_info() as mtree_info_flatview() + mtree_info_as()
> memory: Have 'info mtree' remove duplicated Address Space information
Queued via memory-api.
On 1/17/22 21:08, Daniel Henrique Barboza wrote:
On 1/17/22 11:47, Fabiano Rosas wrote:
These tests ensure that our emulation for these cpus is not completely
broken and we can at least run OpenBIOS on them.
$ make check-avocado AVOCADO_TESTS=../tests/avocado/ppc_74xx.py
Signed-off-by: Fabia
On 1/17/22 21:53, Daniel Henrique Barboza wrote:
On 1/17/22 16:19, lagar...@linux.ibm.com wrote:
From: Leonardo Garcia
Signed-off-by: Leonardo Garcia
---
It is worth noticing that this patch applies cleanly only if the
"[PATCH 0/3] rSTify ppc-spapr-hotplug.txt" [1]
series is applied fir
On 1/17/22 20:50, Daniel Henrique Barboza wrote:
On 1/17/22 09:27, Cédric Le Goater wrote:
and grab the PHB version from the PEC class directly when needed.
I guess we want a capital "A" when starting the commit msg
I just removed the 'and'.
Thanks,
C.
Signed-off-by: Cédric Le Goat
On Tue, Jan 18, 2022 at 3:27 PM Anup Patel wrote:
>
> On Tue, Jan 18, 2022 at 10:50 AM Alistair Francis
> wrote:
> >
> > On Sat, Jan 15, 2022 at 2:18 AM Anup Patel wrote:
> > >
> > > Currently, we have to use OpenSBI firmware ELF as bios for the spike
> > > machine because the HTIF console requ
On Tue, Jan 18, 2022 at 10:50 AM Alistair Francis wrote:
>
> On Sat, Jan 15, 2022 at 2:18 AM Anup Patel wrote:
> >
> > Currently, we have to use OpenSBI firmware ELF as bios for the spike
> > machine because the HTIF console requires ELF for parsing "fromhost"
> > and "tohost" symbols.
> >
> > Th
On Sat, Jan 15, 2022 at 2:18 AM Anup Patel wrote:
>
> Currently, we have to use OpenSBI firmware ELF as bios for the spike
> machine because the HTIF console requires ELF for parsing "fromhost"
> and "tohost" symbols.
>
> The latest OpenSBI can now optionally pick-up HTIF register address
> from H
On 18/1/22 00:27, John Snow wrote:
On Mon, Jan 17, 2022 at 9:11 AM Daniel P. Berrangé wrote:
With the current 'qmp-shell' tool developers must first spawn QEMU with
a suitable -qmp arg and then spawn qmp-shell in a separate terminal
pointing to the right socket.
With 'qmp-shell-wrap' develope
On Tue, Jan 18, 2022 at 1:31 PM Anup Patel wrote:
>
> On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote:
> >
> > From: Guo Ren
> >
> > Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
> > need to ignore them. They cannot be a part of ppn.
> >
> > 1: The RISC-V Instruction Set Man
On Mon, Jan 17, 2022 at 5:18 PM wrote:
>
> From: Guo Ren
>
> Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
> need to ignore them. They cannot be a part of ppn.
>
> 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
>4.4 Sv39: Page-Based 39-bit Virtua
On Tue, Jan 18, 2022 at 11:59 AM wrote:
>
> From: Frank Chang
>
> All Zve* extensions support all vector load and store instructions,
> except Zve64* extensions do not support EEW=64 for index values when
> XLEN=32.
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
On Tue, Jan 11, 2022 at 1:54 PM Weiwei Li wrote:
>
> This patchset implements RISC-V scalar crypto extension v1.0.0 version
> instructions.
> Partial instructions are reused from B-extension.
>
> Specification:
> https://github.com/riscv/riscv-crypto
>
> The port is available here:
> https://gith
On Tue, Jan 11, 2022 at 1:56 PM Weiwei Li wrote:
>
>- reuse partial instructions of Zbb/Zbc extensions
>- add brev8, packh, unzip, zip, etc.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> ---
> target/riscv/bitmanip_helper.c | 74 ++
> target/riscv/h
On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li wrote:
>
>- add SEED CSR
>- add USEED, SSEED fields for MSECCFG CSR
>
> Co-authored-by: Ruibo Lu
> Co-authored-by: Zewen Ye
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> ---
> target/riscv/cpu_bits.h | 9 +
> target/riscv/cs
On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li wrote:
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> ---
> target/riscv/cpu.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b487a8282c..628a782ba9 100644
> --- a/
On Tue, Jan 11, 2022 at 2:01 PM Weiwei Li wrote:
>
> Co-authored-by: Ruibo Lu
> Co-authored-by: Zewen Ye
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> ---
> target/riscv/crypto_helper.c| 446 ++
> target/riscv/helper.h | 37 ++
>
Anup Patel 於 2022年1月17日 週一 下午10:18寫道：
> From: Anup Patel
>
> The AIA specification defines IMSIC interface CSRs for easy access
> to the per-HART IMSIC registers without using indirect xiselect and
> xireg CSRs. This patch implements the AIA IMSIC interface CSRs.
>
> Signed-off-by: Anup Patel
>
Anup Patel 於 2022年1月17日 週一 下午10:29寫道：
> From: Anup Patel
>
> The RISC-V AIA (Advanced Interrupt Architecture) defines a new
> interrupt controller for MSIs (message signal interrupts) called
> IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC
> is per-HART device and also suppport
Anup Patel 於 2022年1月18日 週二 上午11:41寫道：
> On Tue, Jan 18, 2022 at 9:04 AM Frank Chang
> wrote:
> >
> > Anup Patel 於 2022年1月17日 週一 下午10:28寫道：
> >>
> >> From: Anup Patel
> >>
> >> The AIA spec defines programmable 8-bit priority for each local
> interrupt
> >> at M-level, S-level and VS-level so w
On Tue, Jan 18, 2022 at 9:04 AM Frank Chang wrote:
>
> Anup Patel 於 2022年1月17日 週一 下午10:28寫道：
>>
>> From: Anup Patel
>>
>> The AIA spec defines programmable 8-bit priority for each local interrupt
>> at M-level, S-level and VS-level so we extend local interrupt processing
>> to consider AIA inter
On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote:
>
> - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on
> QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
> - add PTE_PBMT bit check for inner PTE
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Jun
Anup Patel 於 2022年1月17日 週一 下午10:28寫道：
> From: Anup Patel
>
> The AIA spec defines programmable 8-bit priority for each local interrupt
> at M-level, S-level and VS-level so we extend local interrupt processing
> to consider AIA interrupt priorities. The AIA CSRs which help software
> configure l
On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote:
>
> - add PTE_N bit
> - add PTE_N bit check for inner PTE
> - update address translation to support 64KiB continuous region (napot_bits =
> 4)
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Cc: Anup Patel
I did review this patch
On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote:
>
> From: Guo Ren
>
> Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
> need to ignore them. They cannot be a part of ppn.
>
> 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
>4.4 Sv39: Page-Based 39-
On Mon, Jan 17, 2022 at 12:48:10PM +0100, Paolo Bonzini wrote:
> On 1/17/22 00:53, Philippe Mathieu-Daudé via wrote:
> >We have one SGX-EPC address/size/node per memory backend,
> >make it child of the backend in the QOM composition tree.
> >
> >Cc: Yang Zhong
> >Signed-off-by: Philippe Mathieu-Da
From: Frank Chang
In SPI-mode, type B ("cleared on valid command") clear condition is not
supported, and as the "In idle state" bit in SPI-mode has type A
("according to current state") clear condition, the CURRENT_STATE bits
in an SPI-mode response should be the SD card's state after the command
On Mon, Jan 17, 2022 at 01:48:46PM +, Daniel P. Berrangé wrote:
> On Mon, Jan 17, 2022 at 12:53:30AM +0100, Philippe Mathieu-Daudé via wrote:
> > Avoid having CPUs objects dangling as unattached QOM ones,
> > directly attach them to the machine.
>
> Lets be more explicit here
>
> [quote]
>
From: Frank Chang
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c| 4 ++--
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c| 2 +-
target/riscv/translate.c | 2 ++
5 files changed, 7 insertions(+), 4 deletion
在 2022/1/18 9:00, Peter Xu 写道:
On Mon, Jan 17, 2022 at 10:00:57PM +0800, Hyman Huang wrote:
This algorithm seems works even worse than the previous version, could you have
a look on what's wrong?
What number the dirty-ring-size of qemu be configured? is it the same as
previous version test?
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2ba22503da..4bca1cd289 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -664,6 +664,7 @
From: Frank Chang
Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 18 ++
1 file changed, 18 insertions(+)
d
From: Frank Chang
Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 32 +++--
1 file changed, 25 insertion
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0898954c02..33c1df638b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -664,6 +664,7 @
From: Frank Chang
All Zve* extensions support all vector fixed-point arithmetic
instructions, except that vsmul.vv and vsmul.vx are not supported
for EEW=64 in Zve64*.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 27 +++
From: Frank Chang
All Zve* extensions support all vector load and store instructions,
except Zve64* extensions do not support EEW=64 for index values when
XLEN=32.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 19 +++
1 file changed, 15 insertions(+),
From: Frank Chang
Zve64f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
From: Frank Chang
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve32f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_t
From: Frank Chang
Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/targ
From: Frank Chang
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve64f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/t
From: Frank Chang
Zve32f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c| 4
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 5 -
target/riscv/csr.c| 6 +-
target/riscv/translate.c | 2 ++
5 files changed, 16 insertions(+), 2
From: Frank Chang
All Zve* extensions support all vector integer instructions,
except that the vmulh integer multiply variants that return the
high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx,
vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.
Signed-off-by: Frank C
From: Frank Chang
Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 ++---
1 file changed, 6 insertions(+), 3 deletions
From: Frank Chang
In RVV v1.0 spec, several Zve* vector extensions for embedded processors
are defined in Chapter 18.2:
https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#zve-vector-extensions-for-embedded-processors
This patchset implements Zve32f and Zve64f extensions.
The port is av
From: Frank Chang
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv
On Mon, Jan 17, 2022 at 01:51:30PM +0100, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé
>
> Since commit 292e13142d2, dma_buf_rw() returns a MemTxResult type.
> Do not discard it, return it to the caller. Pass the previously
> returned value (the QEMUSGList residual size, which was
On Tue, Jan 18, 2022 at 6:27 AM Alistair Francis
wrote:
> On Wed, Dec 29, 2021 at 12:34 PM wrote:
> >
> > From: Frank Chang
> >
> > All Zve* extensions support all vector load and store instructions,
> > except Zve64* extensions do not support EEW=64 for index values when
> > XLEN=32.
> >
> > S
- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma,
hfence.vvma and hfence.gvma except extension check
- do nothing other than extension check for sfence.w.inval and sfence.inval.ir
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Anup Patel
---
target/riscv
- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Cc: Anup Patel
---
target/riscv/cpu.c| 2 ++
target/riscv/cpu.h| 1 +
target/riscv/cpu_bi
- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU,
since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bit check for inner PTE
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Cc: Heiko Stuebner
Cc: Anup Patel
---
target/ris
From: Guo Ren
Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
need to ignore them. They cannot be a part of ppn.
1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
4.4 Sv39: Page-Based 39-bit Virtual-Memory System
4.5 Sv48: Page-Based 48-bit Virtual
This patchset implements virtual memory related RISC-V extensions: Svnapot
version 1.0, Svinval vesion 1.0, Svpbmt version 1.0.
Specification:
https://github.com/riscv/virtual-memory/tree/main/specs
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v5
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Anup Patel
---
target/riscv/cpu_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 26608ddf1c..1820188f41 100644
--- a/target/riscv/cpu_helper.c
+++ b/targ
在 2022/1/18 上午7:28, Alistair Francis 写道:
On Tue, Jan 11, 2022 at 1:57 PM Weiwei Li wrote:
- share it between target/arm and target/riscv
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Philippe Mathieu-Daudé
Do you mind fixing up the commit title?
Maybe something
On Mon, Jan 17, 2022 at 10:00:57PM +0800, Hyman Huang wrote:
> > This algorithm seems works even worse than the previous version, could you
> > have
> > a look on what's wrong?
> What number the dirty-ring-size of qemu be configured? is it the same as
> previous version test?
It should be the sam
The old legacy runner no longer seems to work with output logging, so we
can't see failure logs when a test case fails. The new runner doesn't
(seem to) support Coverage.py yet, but seeing error output is a more
important feature.
Signed-off-by: John Snow
---
python/avocado.cfg | 2 +-
1 file ch
QEMU versions prior to the "oob" capability *also* can't accept the
"enable" keyword argument at all. Fix the handshake process with older
QEMU versions.
Signed-off-by: John Snow
---
python/qemu/aqmp/qmp_client.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/python/qem
GitLab: https://gitlab.com/jsnow/qemu/-/commits/python-aqmp-fixes
CI: https://gitlab.com/jsnow/qemu/-/pipelines/449959282
Fix a bug in async QMP, and fix a minor test annoyance.
John Snow (2):
python/aqmp: Fix negotiation with pre-"oob" QEMU
python: use avocado's "new" runner
python/avocado
On Tue, Jan 11, 2022 at 1:57 PM Weiwei Li wrote:
>
>- share it between target/arm and target/riscv
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Reviewed-by: Philippe Mathieu-Daudé
Do you mind fixing up the commit title?
Maybe something more like:
crypto: move sm4_sbox fr
On Mon, Jan 17, 2022 at 9:11 AM Daniel P. Berrangé wrote:
>
> With the current 'qmp-shell' tool developers must first spawn QEMU with
> a suitable -qmp arg and then spawn qmp-shell in a separate terminal
> pointing to the right socket.
>
> With 'qmp-shell-wrap' developers can ignore QMP sockets en
On Mon, Jan 17, 2022 at 3:49 PM Peter Maydell wrote:
>
> On Mon, 17 Jan 2022 at 20:35, John Snow wrote:
>
> > Can you please try applying this temporary patch and running `./check
> > -qcow2 040 041` until you see a breakage and show me the output from
> > that?
>
> With this temporary patch the
On Sun, Jan 16, 2022 at 9:49 PM Bernhard Beschow wrote:
>
> fdt_open_into() obligingly returns an error code in case the operation
> failed. So be obliging as well and use it in the error message.
>
> Signed-off-by: Bernhard Beschow
Reviewed-by: Alistair Francis
Alistair
> ---
> softmmu/devi
On Wed, Dec 29, 2021 at 12:39 PM wrote:
>
> From: Frank Chang
>
> All Zve* extensions support the vector configuration instructions.
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
> 1 file changed, 2 insertions
On Wed, Dec 29, 2021 at 12:46 PM wrote:
>
> From: Frank Chang
>
> Vector narrowing conversion instructions are provided to and from all
> supported integer EEWs for Zve32f extension.
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_
On Wed, Dec 29, 2021 at 12:50 PM wrote:
>
> From: Frank Chang
>
> Vector widening conversion instructions are provided to and from all
> supported integer EEWs for Zve32f extension.
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_r
On Wed, Dec 29, 2021 at 12:52 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 5e98860a09..2b54c64f56 1006
On Wed, Dec 29, 2021 at 12:45 PM wrote:
>
> From: Frank Chang
>
> Vector narrowing conversion instructions are provided to and from all
> supported integer EEWs for Zve64f extension.
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_
On Wed, Dec 29, 2021 at 12:48 PM wrote:
>
> From: Frank Chang
>
> Vector single-width floating-point reduction operations for EEW=32 are
> supported for Zve32f extension.
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc |
On Wed, Dec 29, 2021 at 12:34 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c| 4 ++--
> target/riscv/cpu.h| 1 +
> target/riscv/cpu_helper.c | 2 +-
> target/riscv/csr.c| 2 +-
> target
On Wed, Dec 29, 2021 at 12:48 PM wrote:
>
> From: Frank Chang
>
> Zve32f extension requires the scalar processor to implement the F
> extension and implement all vector floating-point instructions for
> floating-point operands with EEW=32 (i.e., no widening floating-point
> operations).
>
> Signe
On Wed, Dec 29, 2021 at 12:42 PM wrote:
>
> From: Frank Chang
>
> Vector widening conversion instructions are provided to and from all
> supported integer EEWs for Zve64f extension.
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_r
On Wed, Dec 29, 2021 at 12:44 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 01239620ca..38cd11a8ae 1006
On Wed, Jan 12, 2022 at 6:20 PM Yifei Jiang via wrote:
>
> This series adds both riscv32 and riscv64 kvm support, and implements
> migration based on riscv.
>
> Because of RISC-V KVM has been merged into the Linux master, so this
> series are changed from RFC to patch.
>
> Several steps to use thi
On Wed, Dec 29, 2021 at 12:41 PM wrote:
>
> From: Frank Chang
>
> Vector single-width floating-point reduction operations for EEW=32 are
> supported for Zve64f extension.
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc |
On Tue, Jan 11, 2022 at 1:28 PM Yanan Wang via wrote:
>
> The pointer assignment "const char *p = path;" in function
> qemu_fdt_add_path is unnecessary. Let's remove it and just
> use the "path" passed in. No functional change.
>
> Suggested-by: Richard Henderson
> Signed-off-by: Yanan Wang
Tha
On Wed, Dec 29, 2021 at 12:43 PM wrote:
>
> From: Frank Chang
>
> Zve64f extension requires the scalar processor to implement the F
> extension and implement all vector floating-point instructions for
> floating-point operands with EEW=32 (i.e., no widening floating-point
> operations).
>
> Signe
On Wed, Dec 29, 2021 at 12:37 PM wrote:
>
> From: Frank Chang
>
> All Zve* extensions support all vector fixed-point arithmetic
> instructions, except that vsmul.vv and vsmul.vx are not supported
> for EEW=64 in Zve64*.
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
>
On Wed, Dec 29, 2021 at 12:36 PM wrote:
>
> From: Frank Chang
>
> All Zve* extensions support all vector integer instructions,
> except that the vmulh integer multiply variants that return the
> high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx,
> vmulhsu.vv, vmulhsu.vx) are not
On Wed, Dec 29, 2021 at 12:34 PM wrote:
>
> From: Frank Chang
>
> All Zve* extensions support all vector load and store instructions,
> except Zve64* extensions do not support EEW=64 for index values when
> XLEN=32.
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/insn_trans/trans_rvv.c.inc
On Wed, Dec 29, 2021 at 12:34 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c| 4
> target/riscv/cpu.h| 1 +
> target/riscv/cpu_helper.c | 5 -
> target/riscv/csr.c| 6 +-
>
On Wed, Dec 29, 2021 at 12:36 PM wrote:
>
> From: Frank Chang
>
> All Zve* extensions support the vector configuration instructions.
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 6 --
> 1 file changed, 4 insertio
Fabiano Rosas writes:
> Some bits described in the user manual are missing from msr_mask. Add
> them.
>
> Signed-off-by: Fabiano Rosas
> ---
> target/ppc/cpu_init.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> inde
On 1/17/22 16:19, lagar...@linux.ibm.com wrote:
From: Leonardo Garcia
Signed-off-by: Leonardo Garcia
---
It is worth noticing that this patch applies cleanly only if the
"[PATCH 0/3] rSTify ppc-spapr-hotplug.txt" [1]
series is applied first. The reason is that docs/system/ppc/pseries.rs
On 1/17/22 16:19, lagar...@linux.ibm.com wrote:
From: Leonardo Garcia
Signed-off-by: Leonardo Garcia
---
Reviewed-by: Daniel Henrique Barboza
docs/specs/{ppc-spapr-uv-hcalls.txt => ppc-spapr-uv-hcalls.rst} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename docs/specs/{ppc
On 1/17/22 16:19, lagar...@linux.ibm.com wrote:
From: Leonardo Garcia
Signed-off-by: Leonardo Garcia
---
Reviewed-by: Daniel Henrique Barboza
docs/specs/ppc-spapr-uv-hcalls.txt | 165 -
1 file changed, 89 insertions(+), 76 deletions(-)
diff --git a/docs/
On Mon, 17 Jan 2022 at 20:35, John Snow wrote:
> Can you please try applying this temporary patch and running `./check
> -qcow2 040 041` until you see a breakage and show me the output from
> that?
With this temporary patch the VM doesn't launch at all:
peter.mayd...@hackbox2.linaro.org:~/qemu-
On Mon, 17 Jan 2022 at 20:35, John Snow wrote:
>
> On Mon, Jan 17, 2022 at 5:05 AM Kevin Wolf wrote:
> >
> > Am 10.01.2022 um 16:55 hat Peter Maydell geschrieben:
> > > Just saw this failure of iotests in a netbsd VM
> This trace says that we timed out while awaiting a connection from
> QEMU dur
On 17/1/22 21:08, Daniel Henrique Barboza wrote:
On 1/17/22 11:47, Fabiano Rosas wrote:
These tests ensure that our emulation for these cpus is not completely
broken and we can at least run OpenBIOS on them.
$ make check-avocado AVOCADO_TESTS=../tests/avocado/ppc_74xx.py
Signed-off-by: Fabiano
On Mon, 17 Jan 2022 at 05:52, David Gibson wrote:
> It is also touched in the *super* old cpu_load_old. I suspect we
> could probably just drop that completely, since I don't think we
> realistically support migration from a version that old anyway.
This would be a nice thing to do, because the
Add and option to generate trace events. We should generate both trace
events and trace-events files for further trace events code generation.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
scripts/qapi/commands.py | 91 ++--
scripts/qapi/main.py | 10 +++
On Mon, Jan 17, 2022 at 5:05 AM Kevin Wolf wrote:
>
> Am 10.01.2022 um 16:55 hat Peter Maydell geschrieben:
> > Just saw this failure of iotests in a netbsd VM (the in-tree
> > tests/vm stuff). Pretty sure it's an intermittent as the
> > pulreq being tested has nothing io or block related.
> >
> >
1. Use --add-trace-events when generate qmp commands
2. Add corresponding .trace-events files as outputs in qapi_files
custom target
3. Define global qapi_trace_events list of .trace-events file targets,
to fill in trace/qapi.build and to use in trace/meson.build
4. In trace/meson.build use t
We are going to generate trace events for qmp commands. We should
generate both trace events and trace-events.
For now, add .trace-events file object, to be filled in further commit.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
scripts/qapi/gen.py | 13 ++---
1 file changed, 10 inser
Hi all!
This series aims to add trace points for each qmp command with help of
qapi code generator.
v3:
- don't drop old trace events
- make pair of qmp_enter_ and qmp_exit_ trace events
- improve patch splitting
- use term "trace events" constantly instead of "trace points"
- add comment on
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