On Wed, Dec 29, 2021 at 12:36 PM <frank.ch...@sifive.com> wrote: > > From: Frank Chang <frank.ch...@sifive.com> > > All Zve* extensions support the vector configuration instructions. > > Signed-off-by: Frank Chang <frank.ch...@sifive.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc > b/target/riscv/insn_trans/trans_rvv.c.inc > index 6c285c958b..5b47729a21 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -129,7 +129,8 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, > TCGv s2) > { > TCGv s1, dst; > > - if (!require_rvv(s) || !has_ext(s, RVV)) { > + if (!require_rvv(s) || > + !(has_ext(s, RVV) || s->ext_zve64f)) { > return false; > } > > @@ -164,7 +165,8 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, > TCGv s2) > { > TCGv dst; > > - if (!require_rvv(s) || !has_ext(s, RVV)) { > + if (!require_rvv(s) || > + !(has_ext(s, RVV) || s->ext_zve64f)) { > return false; > } > > -- > 2.31.1 > >