On Wed, Dec 29, 2021 at 12:34 PM <frank.ch...@sifive.com> wrote:
>
> From: Frank Chang <frank.ch...@sifive.com>
>
> Signed-off-by: Frank Chang <frank.ch...@sifive.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 4 ++++
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_helper.c | 5 ++++-
> target/riscv/csr.c | 6 +++++-
> target/riscv/translate.c | 2 ++
> 5 files changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6ef3314bce..01239620ca 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -562,6 +562,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> }
> set_vext_version(env, vext_version);
> }
> + if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
> + error_setg(errp, "Zve64f extension depends upon RVF.");
> + return;
> + }
> if (cpu->cfg.ext_j) {
> ext |= RVJ;
> }
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index dc10f27093..d7b2db2b2f 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -317,6 +317,7 @@ struct RISCVCPU {
> bool ext_icsr;
> bool ext_zfh;
> bool ext_zfhmin;
> + bool ext_zve64f;
>
> char *priv_spec;
> char *user_spec;
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 10f3baba53..52d93a41fd 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -69,12 +69,15 @@ static RISCVMXL cpu_get_xl(CPURISCVState *env)
> void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> target_ulong *cs_base, uint32_t *pflags)
> {
> + CPUState *cs = env_cpu(env);
> + RISCVCPU *cpu = RISCV_CPU(cs);
> +
> uint32_t flags = 0;
>
> *pc = env->pc;
> *cs_base = 0;
>
> - if (riscv_has_ext(env, RVV)) {
> + if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
> /*
> * If env->vl equals to VLMAX, we can use generic vector operation
> * expanders (GVEC) to accerlate the vector operations.
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 146447eac5..340b9661a8 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -47,7 +47,11 @@ static RISCVException fs(CPURISCVState *env, int csrno)
>
> static RISCVException vs(CPURISCVState *env, int csrno)
> {
> - if (env->misa_ext & RVV) {
> + CPUState *cs = env_cpu(env);
> + RISCVCPU *cpu = RISCV_CPU(cs);
> +
> + if (env->misa_ext & RVV ||
> + cpu->cfg.ext_zve64f) {
> #if !defined(CONFIG_USER_ONLY)
> if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
> return RISCV_EXCP_ILLEGAL_INST;
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 5df6c0d800..8c3b0168b7 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -78,6 +78,7 @@ typedef struct DisasContext {
> bool ext_ifencei;
> bool ext_zfh;
> bool ext_zfhmin;
> + bool ext_zve64f;
> bool hlsx;
> /* vector extension */
> bool vill;
> @@ -705,6 +706,7 @@ static void riscv_tr_init_disas_context(DisasContextBase
> *dcbase, CPUState *cs)
> ctx->ext_ifencei = cpu->cfg.ext_ifencei;
> ctx->ext_zfh = cpu->cfg.ext_zfh;
> ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
> + ctx->ext_zve64f = cpu->cfg.ext_zve64f;
> ctx->vlen = cpu->cfg.vlen;
> ctx->elen = cpu->cfg.elen;
> ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
> --
> 2.31.1
>
>
