On Tue, Jan 18, 2022 at 11:59 AM <frank.ch...@sifive.com> wrote:
>
> From: Frank Chang <frank.ch...@sifive.com>
>
> All Zve* extensions support all vector load and store instructions,
> except Zve64* extensions do not support EEW=64 for index values when
> XLEN=32.
>
> Signed-off-by: Frank Chang <frank.ch...@sifive.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 19 +++++++++++++++----
> 1 file changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 5b47729a21..0bf41aaa1e 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -263,10 +263,21 @@ static bool vext_check_st_index(DisasContext *s, int
> vd, int vs2, int nf,
> uint8_t eew)
> {
> int8_t emul = eew - s->sew + s->lmul;
> - return (emul >= -3 && emul <= 3) &&
> - require_align(vs2, emul) &&
> - require_align(vd, s->lmul) &&
> - require_nf(vd, nf, s->lmul);
> + bool ret = (emul >= -3 && emul <= 3) &&
> + require_align(vs2, emul) &&
> + require_align(vd, s->lmul) &&
> + require_nf(vd, nf, s->lmul);
> +
> + /*
> + * All Zve* extensions support all vector load and store instructions,
> + * except Zve64* extensions do not support EEW=64 for index values
> + * when XLEN=32. (Section 18.2)
> + */
> + if (get_xl(s) == MXL_RV32) {
> + ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
> + }
> +
> + return ret;
> }
>
> /*
> --
> 2.31.1
>
>
