Igor Mammedov writes:
> On Fri, 09 Jul 2021 13:25:43 +0200
> Markus Armbruster wrote:
>
>> Igor Mammedov writes:
>>
>> > On Thu, 08 Jul 2021 15:08:57 +0200
>> > Markus Armbruster wrote:
>> >
>> >> Daniel Henrique Barboza writes:
>> >>
>> >> > MEM_UNPLUG_ERROR is deprecated since the int
migrate_add_blocker() fails when running with --only-migratable, and
when migration is in progress.
qxl.c continues after migrate_add_blocker() fails:
{
/*
* Windows 8 drivers place qxl commands in the vram
* (instead of the ram) bar. We can't live m
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Title:
intel-hda:
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Title:
cpu feature
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Title:
CTRL+ALT is
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Title:
Mouse start
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Title:
certain pro
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Title:
Lots of stu
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Title:
intel-hda:
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Title:
Assertion f
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Title:
Guest displ
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Title:
Zynq7000 UA
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qemu-system
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Title:
Guest seems
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Title:
[RISCV] sfe
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Title:
Implement T
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QEMU gdbstu
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Title:
Tests canno
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Title:
Unable to s
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Title:
Mounting VF
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Title:
[Feature r
On Sat, Jul 10, 2021 at 11:43 AM Programmingkid
wrote:
>
>
>
> > On Jul 8, 2021, at 8:15 PM, Akihiko Odaki wrote:
> >
> > I tried [NSApp applicationIconImage] but had no luck. I suspect it is
> > because Rez is for Carbon development and deprecated while NSApp is
> > from AppKit. Loading from the
> On Jul 8, 2021, at 8:31 PM, Akihiko Odaki wrote:
>
> Hi,
>
> Reverting commit e31746ecf8dd2f25f687c94ac14016a3ba5debfc solves the
> problem only for cocoa and introduces another problem. (For others:
> see
> https://lore.kernel.org/qemu-devel/797ada26-0366-447f-85f0-5e27dc534...@gmail.com/
In tcg_region_prologue_set, we reset TCGContext.code_gen_ptr.
So do that after we've used it to dump the prologue contents.
Fixes: b0a0794a0f16
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 4dd40
> On Jul 8, 2021, at 8:15 PM, Akihiko Odaki wrote:
>
> I tried [NSApp applicationIconImage] but had no luck. I suspect it is
> because Rez is for Carbon development and deprecated while NSApp is
> from AppKit. Loading from the filesystem is inevitable.
Totally disagree. I'm on a new MacBook A
This patch provides the vhost-user backend implementation to work
in tandem with the vhost-user-rng implementation of the QEMU VMM.
It uses the vhost-user API so that other VMM can re-use the interface
without having to write the driver again.
Signed-off-by: Mathieu Poirier
---
tools/meson.buil
Following in the footsteps of what whas done for vhost-user-i2c
and virtiofsd, introduce a random number generator (RNG) backend
that communicates with a vhost-user server to retrieve entropy.
That way another VMM could be using the same vhost-user daemon and
avoid having to write yet another RNG d
This patch provides a PCI bus interface to the vhost-user-rng backed.
The implentation is similar to what was done for vhost-user-i2c-pci and
vhost-user-fs-pci.
Signed-off-by: Mathieu Poirier
---
hw/virtio/meson.build | 1 +
hw/virtio/vhost-user-rng-pci.c | 79 +
Add description and example for the vhost-user based RNG implementation.
Tailored on Viresh Kumar's vhost-user-i2c documentation.
Signed-off-by: Mathieu Poirier
---
docs/tools/index.rst | 1 +
docs/tools/vhost-user-rng.rst | 74 +++
2 files changed, 75 i
This sets adds a vhost-user based random number generator (RNG),
similar to what has been done for i2c and virtiofsd, with the
implementation following the patterns already set forth in those.
Applies cleanly to git://git.qemu.org/qemu.git master(05de778b5b8a).
Thanks,
Mathieu
Mathieu Poirier (4
The functions vmsa_ttbcr_write and vmsa_ttbcr_raw_write expect
the offset to be for the complete TCR structure, not the offset
to the low 32-bits of a uint64_t. Using offsetoflow32 in this
case breaks big-endian hosts.
For TTBCR2, we do want the high 32-bits of a uint64_t.
Use cp15.tcr_el[*].raw_
This one patch fixes boot_linux_console test_arm_virt.
It does not fix all of the failures. The next one on the
list is test_arm_emcraft_sf2, where the cpu boots fine but
the net device doesn't work correctly.
r~
Richard Henderson (1):
target/arm: Fix offsets for TTBCR
target/arm/helper.c
SEV-SNP builds upon existing SEV and SEV-ES functionality while adding
new hardware-based memory protections. SEV-SNP adds strong memory integrity
protection to help prevent malicious hypervisor-based attacks like data
replay, memory re-mapping and more in order to create an isolated memory
encrypt
The KVM_SEV_SNP_LAUNCH_UPDATE command is used for encrypting the bios
image used for booting the SEV-SNP guest.
Signed-off-by: Brijesh Singh
---
target/i386/sev.c| 33 -
target/i386/trace-events | 1 +
2 files changed, 33 insertions(+), 1 deletion(-)
dif
During the SNP guest launch sequence, a special secrets and cpuid page
needs to be populated by the SEV-SNP firmware. The secrets page contains
the VM Platform Communication Key (VMPCKs) used by the guest to send and
receive secure messages to the PSP. And CPUID page will contain the CPUID
value fi
The SNP_LAUNCH_START is called first to create a cryptographic launch
context within the firmware.
Signed-off-by: Brijesh Singh
---
target/i386/sev.c| 30 +-
target/i386/trace-events | 1 +
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/target
When SEV-SNP is enabled, the KVM_SNP_INIT command is used to initialize
the platform. The command checks whether SNP is enabled in the KVM, if
enabled then it allocate a new ASID from the SNP pool and calls the
firmware to initialize the all the resources.
Signed-off-by: Brijesh Singh
---
target
To launch the SEV-SNP guest, a user can specify up to 8 parameters.
Passing all parameters through command line can be difficult. To simplify
the launch parameter passing, introduce a .ini-like config file that can be
used for passing the parameters to the launch flow.
The contents of the config f
Sync the kvm.h with the kernel to include the SNP specific commands.
Signed-off-by: Brijesh Singh
---
linux-headers/linux/kvm.h | 47 +++
1 file changed, 47 insertions(+)
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 20d6a263bb..c17
09.07.2021 18:39, Eric Blake wrote:
Enhance the test to demonstrate existing less-than-stellar behavior of
qemu-img with a qcow2 image containing an inconsistent bitmap: we
don't diagnose the problem until after copying the entire image (a
potentially long time), and when we do diagnose the failu
On Thu, Jul 08, 2021 at 02:37:54PM -0700, Richard Henderson wrote:
> We still need the t0 temporary for computing overflow,
> but we do not need to initialize it to zero first.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Stafford Horne
On Thu, Jul 08, 2021 at 02:37:51PM -0700, Richard Henderson wrote:
> Replace uses of tcg_const_* with the allocate and free close together.
I read this as tcg_const_* is being replaced with allocate and free. Perhaps we
can say:
Replace uses of tcg_const_* allocate and free close together with
t
On Thu, Jul 08, 2021 at 02:37:53PM -0700, Richard Henderson wrote:
> We are virtually certain to have fetched constant 0 once, at the
> beginning of the TB, so we might as well use it elsewhere.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Stafford Horne
On Wed, Jul 07, 2021 at 03:40:28PM +0200, Michal Privoznik wrote:
> See 2/2 for explanation. The first patch is just cosmetics.
>
> Michal Privoznik (2):
> numa: Report expected initiator
> numa: Parse initiator= attribute before cpus= attribute
Queued, thanks!
--
Eduardo
On Mon, Jun 28, 2021 at 12:30:43PM +0100, Daniel P. Berrangé wrote:
> This is a spin off from this thread:
>
> https://lists.gnu.org/archive/html/qemu-devel/2021-06/msg06135.html
>
> to improve the documentation of the current behaviour of -smp
> arg. In that thread it is suggested that we chan
On 7/6/21 10:17 AM, Eric Auger wrote:
Add Intel IOMMU functional tests based on fedora 31.
Different configs are checked:
- strict
- caching mode, strict
- passthrough.
Signed-off-by: Eric Auger
Signed-off-by: Willian Rampazzo
Acked-by: Peter Xu
---
v4 -> v5:
- import cleanup (William)
-
From: Philippe Mathieu-Daudé
Fix "havn't (make)" -> "haven't (made)" typo.
Reviewed-by: Luis Pires
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Message-Id: <20210629051400.2573253-1-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
hw/usb/desc-msos.c | 2 +-
tar
From: Mark Nelson
We know that in the body of this if statement i is less than len, so
we really should be copying len - i bytes not i - len bytes.
Fix this typo.
Fixes: 8d8404f1564 ("util: Add qemu_guest_getrandom and associated routines")
Signed-off-by: Mark Nelson
Reviewed-by: Richard Hende
From: Thomas Huth
The errno numbers are very large on Haiku, so the linking currently
fails there with a "final link failed: memory exhausted" error
message. We should not use the errno number as array indexes here,
thus convert the code to a switch-case statement instead. A clever
compiler shoul
From: Hubert Jasudowicz
Signed-off-by: Hubert Jasudowicz
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Stefan Hajnoczi
Message-Id:
Signed-off-by: Laurent Vivier
---
tools/virtiofsd/fuse_virtio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/virtiofsd/fuse_vir
From: Olaf Hering
Fixes commit 3d0684b2ad82a5dde68e3f08b0d7786dccaf619c ("ram: Update
all functions comments")
Signed-off-by: Olaf Hering
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20210708162159.18045-1-o...@aepfle.de>
Signed-off-by: Laurent Vivier
From: Philippe Mathieu-Daudé
Such comments make reviewing this file somehow easier.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20210523094040.3516968-1-phi...@redhat.com>
Signed-off-by: Laurent Vivier
---
hw/virtio/virtio.c | 2 ++
1 file changed, 2 insert
From: Li Zhijian
Signed-off-by: Li Zhijian
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20210706094433.1766952-1-lizhij...@cn.fujitsu.com>
Signed-off-by: Laurent Vivier
---
migration/rdma.c | 2 +-
softmmu/cpus.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/mig
r-6.1-pull-request
for you to fetch changes up to e28ffe90fde5702aa8716ac2fa1b4116cdcc9e61:
util/guest-random: Fix size arg to tail memcpy (2021-07-09 18:42:46 +0200)
Trivial patches pull reques
From: Markus Armbruster
Commit c6ecec43b2 "qemu-option: Check return value instead of @err
where convenient" simplified
opts = qemu_opts_create(list, qdict_get_try_str(qdict, "id"), 1,
&local_err);
if (local_err) {
error_propagate(errp, local_err);
From: Philippe Mathieu-Daudé
MemoryRegion names is cached on first call to memory_region_name(),
so displaying the name is trace events is cheap. Add it for read /
write ops.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-Id: <20210307074833.143106-1-f4...@amsat.org>
By default, -fsanitize=fuzzer instruments all code with coverage
information. However, this means that libfuzzer will track coverage over
hundreds of source files that are unrelated to virtual-devices. This
means that libfuzzer will optimize inputs for coverage observed in timer
code, memory APIs e
On Fri, Jul 09, 2021 at 09:00:30AM -0700, Richard Henderson wrote:
> Ping.
>
> On 6/19/21 11:23 PM, Richard Henderson wrote:
> > The loop is performing a simple boolean test for the existence
> > of a BP_CPU breakpoint at EIP. Plus it gets the iteration wrong,
> > if we happen to have a BP_GDB br
On 7/8/21 2:34 PM, Cleber Rosa wrote:
On 7/8/21 4:56 AM, Eric Auger wrote:
I am not sufficiently expert on the test infra and python to be really
efficient fixing that. Can anyone help quickly to target the soft
freeze? Otherwise, today I will drop that patch and restore the code I
had in v4
> When setting up NUMA with HMAT enabled there's a check performed
> in machine_set_cpu_numa_node() that reports an error when a NUMA
> node has a CPU but the node's initiator is not itself. The error
> message reported contains only the expected value and not the
> actual value (which is different
Hi,
On 7/7/21 12:24 PM, Willian Rampazzo wrote:
Although it is possible to run a specific test using the avocado
command-line, a user may want to use a specific tag while running the
``make check-acceptance`` during the development or debugging.
I always wanted that feature, thanks for implemen
On Fri, Jul 09, 2021 at 07:09:22PM +0800, Yang Zhong wrote:
> Since Sean Christopherson has left Intel and i am responsible for Qemu SGX
> upstream work. His @intel.com address will be bouncing and his new email(
> sea...@google.com) is also in CC lists.
>
> This series is Qemu SGX virtualization
On Sun, Jun 27, 2021 at 01:38:14PM +0800, huang...@chinatelecom.cn wrote:
> @@ -370,9 +374,17 @@ static inline void
> cpu_physical_memory_set_dirty_lebitmap(unsigned long *bitmap,
> qatomic_or(&blocks[DIRTY_MEMORY_VGA][idx][offset], temp);
>
> if (global
On Sun, Jun 27, 2021 at 01:38:17PM +0800, huang...@chinatelecom.cn wrote:
> +static void calculate_dirtyrate_dirty_bitmap(struct DirtyRateConfig config)
> +{
> +int64_t msec = 0;
> +int64_t start_time;
> +uint64_t protect_flags = 0;
> +uint64_t initially_set = 0;
> +uint64_t pro
On Sun, Jun 27, 2021 at 01:38:16PM +0800, huang...@chinatelecom.cn wrote:
> From: Hyman Huang(黄勇)
>
> introduce util functions to setup the DIRTY_MEMORY_DIRTY_RATE
> dirty bits for the convenience of tracking dirty bitmap when
> calculating dirtyrate.
>
> Signed-off-by: Hyman Huang(黄勇)
> ---
>
Yong,
On Sun, Jun 27, 2021 at 01:38:13PM +0800, huang...@chinatelecom.cn wrote:
> From: Hyman Huang(黄勇)
>
> the dirtyrate measurement implemented by page-sampling originally, it
> is not accurate in some scenarios, so we have introduced dirty-ring
> based dirtyrate measurement(maybe it will be m
Signed-off-by: Mohit Kapoor
---
diff --git a/Makefile b/Makefile
index 86eb7c6..3ea82dd 100644
--- a/Makefile
+++ b/Makefile
@@ -83,6 +83,13 @@ PLUGIN_OBJS := \
plugins/wdc/wdc-utils.o \
plugins/huawei/huawei-nvme.o \
plugins/netapp/netapp-nvme.o \
+ plugins/mi/util/hal/mi-nvme-hal-
On Fri, Jul 09, 2021 at 06:41:41PM +0200, Kevin Wolf wrote:
> Currently, the block driver whitelists are only applied for the system
> emulator. All other binaries still give unrestricted access to all block
> drivers. There are use cases where this made sense because the main
> concern was avoidin
On Wed, Jul 07, 2021 at 10:28:10AM +0200, Philippe Mathieu-Daudé wrote:
> On 3/9/21 5:00 PM, huang...@chinatelecom.cn wrote:
> > From: Hyman
> >
> > The test aborts and error message as the following be throwed:
> > "No such file or directory: '/var/tmp/qemu-migrate-{pid}.migrate",
> > when the u
On 7/9/21 9:04 AM, Jonathan Albrecht wrote:
Currently when a compare-and-trap instruction is executed, qemu will
always raise a SIGILL signal. On real hardware, a SIGFPE is raised.
Change the PGM_DATA case in cpu_loop to follow the behavior in
linux kernel /arch/s390/kernel/traps.c.
* Only rai
Currently, the block driver whitelists are only applied for the system
emulator. All other binaries still give unrestricted access to all block
drivers. There are use cases where this made sense because the main
concern was avoiding customers running VMs on less optimised block
drivers and getting
Hi,
The goal of this email is to try and figure how we want to track/limit the
number of kernel threads created by vhost devices.
Background:
---
For vhost-scsi, we've hit a issue where the single vhost worker thread can't
handle all IO the being sent from multiple queues. IOPs is stuck a
For some scenarios, we'd like to hot-add a monitor device. But QEMU
doesn't support that, yet. It does support hot-swapping character
backends with QMP command chardev-change. This lets us pre-add a
monitor with a null character backend, then chardev-change to a
socket backend. Except the chard
The PL061 comes out of reset with all its lines configured as input,
which means they might need to be pulled to 0 or 1 depending on the
'pullups' and 'pulldowns' properties. Currently we do not assert
these lines on reset; they will only be set whenever the guest first
touches a register that tri
The following changes since commit 38848ce565849e5b867a5e08022b3c755039c11a:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210616'
into staging (2021-06-16 17:02:30 +0100)
are available in the Git repository at:
https://github.com/cminyard/qemu.git tags/for-qemu-6.1-
For the virt board we have two PL061 devices -- one for NonSecure which
is inputs only, and one for Secure which is outputs only. For the former,
we don't care whether its outputs are pulled low or high when the line is
configured as an input, because we don't connect them. For the latter,
we do ca
Le 09/07/2021 à 14:06, Mark Nelson a écrit :
> We know that in the body of this if statement i is less than len, so
> we really should be copying len - i bytes not i - len bytes.
>
> Fix this typo.
>
> Signed-off-by: Mark Nelson
> ---
> util/guest-random.c | 2 +-
> 1 file changed, 1 insertion(
The Luminary PL061s in the Stellaris LM3S9695 don't all have the same
reset value for GPIOPUR. We can get away with not letting the board
configure the PUR reset value because we don't actually wire anything
up to the lines which should reset to pull-up. Add a comment noting
this omission.
Signe
On 7/8/21 11:37 PM, Richard Henderson wrote:
> We are virtually certain to have fetched constant 0 once, at the
> beginning of the TB, so we might as well use it elsewhere.
>
> Signed-off-by: Richard Henderson
> ---
> target/openrisc/translate.c | 12 ++--
> 1 file changed, 6 insertions(
On 7/8/21 11:37 PM, Richard Henderson wrote:
> Replace uses of tcg_const_* with the allocate and free close together.
>
> Signed-off-by: Richard Henderson
> ---
> target/openrisc/translate.c | 42 -
> 1 file changed, 9 insertions(+), 33 deletions(-)
Reviewed-
The Luminary variant of the PL061 has registers GPIOPUR and GPIOPDR
which lets the guest configure whether the GPIO lines are pull-up,
pull-down, or truly floating. Instead of assuming all lines are pulled
high, honour the PUR and PDR registers.
For the plain PL061, continue to assume that lines h
Add a comment documenting the "QEMU interface" of this device:
which MMIO regions, IRQ lines, GPIO lines, etc it exposes.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
hw/gpio/pl061.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
On 7/9/21 6:25 AM, Richard Henderson wrote:
> Replace uses of tcg_const_* with the allocate and free close together.
>
> Signed-off-by: Richard Henderson
> ---
> target/riscv/translate.c| 36 --
> target/riscv/insn_trans/trans_rvf.c.inc | 3 +-
> target/riscv/insn_tr
To improve the problematic source code in qmp_chardev_change
and some redundant source code, the functions qmp_chardev_add
and qmp_chardev_change are refactored. It is mentioned in thread:
https://lists.nongnu.org/archive/html/qemu-devel/2021-04/msg03167.html
Signed-off-by: Li Zhang
---
chardev
From: "hn...@vmware.com"
Signed-off-by: Nick Hudson
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a66c1f0b9eb..910ace42741 10
Convert the use of the DPRINTF debug macro in the PL061 model to
use tracepoints.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
hw/gpio/pl061.c | 27 +--
hw/gpio/trace-events | 6 ++
2 files changed, 15 ins
The PL061 GPIO does not itself include pullup or pulldown resistors
to set the value of a GPIO line treated as an output when it is
configured as an input (ie when the PL061 itself is not driving it).
In real hardware it is up to the board to add suitable pullups or
pulldowns. Currently our implem
On 7/9/21 4:24 PM, Richard Henderson wrote:
> On 7/9/21 12:08 AM, Philippe Mathieu-Daudé wrote:
>> What about this one?
>>
>> @@ -3385,7 +3385,7 @@ static bool do_depw_sar(DisasContext *ct
>> /* Convert big-endian bit numbering in SAR to left-shift. */
>> tcg_gen_xori_reg(shift, cpu_sa
From: Rebecca Cran
Add a space in the message printed when gicr_read*/gicr_write* returns
MEMTX_ERROR in arm_gicv3_redist.c.
Signed-off-by: Rebecca Cran
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20210706211432.31902-1-rebe...@nuviainc.com
Signed-off-by: Peter Maydell
---
hw/intc/arm_gi
From: Ricardo Koller
icv_eoir_write() and icv_dir_write() ignore invalid virtual IRQ numbers
(like LPIs). The issue is that these functions check against the number
of implemented IRQs (QEMU's default is num_irq=288) which can be lower
than the maximum virtual IRQ number (1020 - 1). The consequ
On 09/07/21 13:09, Yang Zhong wrote:
+sgx_epc = g_malloc0(sizeof(*sgx_epc));
+pcms->sgx_epc = sgx_epc;
+
No need to malloc this, it's small.
}
+##
+# @SgxEPC:
+#
+# Sgx EPC cmdline information
+#
+# @id: device's ID
+#
+# @memdev: memory backend linked with device
+#
+# Since: 6
From: Alexandre Iooss
New mini-kernel test for STM32VLDISCOVERY USART1.
Signed-off-by: Alexandre Iooss
Acked-by: Thomas Huth
Acked-by: Alistair Francis
Message-id: 20210617165647.2575955-5-erdn...@crans.org
Signed-off-by: Peter Maydell
---
tests/qtest/boot-serial-test.c | 37 +++
Add tracepoints for reads and writes to the PL061 registers. This requires
restructuring pl061_read() to only return after the tracepoint, rather
than having lots of early-returns.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
hw/gpio/pl061
The stellaris board doesn't emulate the handling of the OLED
chipselect line correctly. Expand the comment describing this,
including a sketch of the theoretical correct way to do it.
Signed-off-by: Peter Maydell
---
hw/arm/stellaris.c | 56 +-
1 file
Currently the pl061_read() and pl061_write() functions handle offsets
using a combination of three if() statements and a switch(). Clean
this up to use just a switch, using case ranges.
This requires that instead of catching accesses to the luminary-only
registers on a stock PL061 via a check on
On 7/9/21 2:06 PM, Mark Nelson wrote:
> We know that in the body of this if statement i is less than len, so
> we really should be copying len - i bytes not i - len bytes.
>
> Fix this typo.
>
Oops.
Fixes: 8d8404f1564 ("util: Add qemu_guest_getrandom and associated
routines")
Reviewed-by: Phili
From: Alexandre Iooss
This adds the target guide for Netduino 2, Netduino Plus 2 and STM32VLDISCOVERY.
Signed-off-by: Alexandre Iooss
Reviewed-by: Alistair Francis
Message-id: 20210617165647.2575955-4-erdn...@crans.org
Signed-off-by: Peter Maydell
---
docs/system/arm/stm32.rst | 66
From: Alexandre Iooss
This SoC is similar to stm32f205 SoC.
This will be used by the STM32VLDISCOVERY to create a machine.
Signed-off-by: Alexandre Iooss
Reviewed-by: Alistair Francis
Message-id: 20210617165647.2575955-2-erdn...@crans.org
Signed-off-by: Peter Maydell
---
include/hw/arm/stm32
From: Alexandre Iooss
This is a Cortex-M3 based machine. Information can be found at:
https://www.st.com/en/evaluation-tools/stm32vldiscovery.html
Signed-off-by: Alexandre Iooss
Reviewed-by: Alistair Francis
Message-id: 20210617165647.2575955-3-erdn...@crans.org
Signed-off-by: Peter Maydell
-
ing
(2021-07-09 14:30:01 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20210709
for you to fetch changes up to 05449abb1d4c5f0c69ceb3d8d03cbc75de39b646:
hw/intc: Improve formatting of MEMTX_ERROR guest error messag
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