Arm changes for before softfreeze: mostly my PL061/GPIO patches, but also a new M-profile board and various other things.
thanks -- PMM The following changes since commit 05de778b5b8ab0b402996769117b88c7ea5c7c61: Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-07-09 14:30:01 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210709 for you to fetch changes up to 05449abb1d4c5f0c69ceb3d8d03cbc75de39b646: hw/intc: Improve formatting of MEMTX_ERROR guest error message (2021-07-09 16:09:12 +0100) ---------------------------------------------------------------- target-arm queue: * New machine type: stm32vldiscovery * hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write * hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers * virt: Fix implementation of GPIO-based powerdown/shutdown mechanism * Correct the encoding of MDCCSR_EL0 and DBGDSCRint * hw/intc: Improve formatting of MEMTX_ERROR guest error message ---------------------------------------------------------------- Alexandre Iooss (4): stm32f100: Add the stm32f100 SoC stm32vldiscovery: Add the STM32VLDISCOVERY Machine docs/system: arm: Add stm32 boards description tests/boot-serial-test: Add STM32VLDISCOVERY board testcase Peter Maydell (10): hw/gpio/pl061: Convert DPRINTF to tracepoints hw/gpio/pl061: Clean up read/write offset handling logic hw/gpio/pl061: Add tracepoints for register read and write hw/gpio/pl061: Document the interface of this device hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers hw/gpio/pl061: Make pullup/pulldown of outputs configurable hw/arm/virt: Make PL061 GPIO lines pulled low, not high hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset hw/gpio/pl061: Document a shortcoming in our implementation hw/arm/stellaris: Expand comment about handling of OLED chipselect Rebecca Cran (1): hw/intc: Improve formatting of MEMTX_ERROR guest error message Ricardo Koller (1): hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write hn...@vmware.com (1): target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint docs/system/arm/stm32.rst | 66 +++++++ docs/system/target-arm.rst | 1 + default-configs/devices/arm-softmmu.mak | 1 + include/hw/arm/stm32f100_soc.h | 57 ++++++ hw/arm/stellaris.c | 56 +++++- hw/arm/stm32f100_soc.c | 182 +++++++++++++++++ hw/arm/stm32vldiscovery.c | 66 +++++++ hw/arm/virt.c | 3 + hw/gpio/pl061.c | 341 +++++++++++++++++++++++++------- hw/intc/arm_gicv3_cpuif.c | 4 +- hw/intc/arm_gicv3_redist.c | 4 +- target/arm/helper.c | 16 +- tests/qtest/boot-serial-test.c | 37 ++++ MAINTAINERS | 13 ++ hw/arm/Kconfig | 10 + hw/arm/meson.build | 2 + hw/gpio/trace-events | 9 + 17 files changed, 790 insertions(+), 78 deletions(-) create mode 100644 docs/system/arm/stm32.rst create mode 100644 include/hw/arm/stm32f100_soc.h create mode 100644 hw/arm/stm32f100_soc.c create mode 100644 hw/arm/stm32vldiscovery.c
