Will be merged in 20.10 with qemu >=5.0 where this came upstream.
** Tags added: qemu-20.10
** Changed in: qemu (Ubuntu)
Status: Confirmed => Triaged
--
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/
On 01/05/2020 15:54, Leonardo Bras wrote:
> If SELinux is setup without 'execmem' permission for qemu, all mmap
> with (PROT_WRITE | PROT_EXEC) will fail and print a warning in
> SELinux log.
>
> If "nvlink2-mr" memory allocation fails (fist diff), it will cause
> guest NUMA nodes to not be cor
Patchew URL:
https://patchew.org/QEMU/20200430162813.17671-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20200430162813.17671-1-richard.hender...@linaro.org
Subject: [PATCH v4 00/18] target/arm: sve
On 4/30/20 11:10 AM, Peter Maydell wrote:
> Convert the Neon floating point VFMA and VFMS insn to decodetree.
> These are the last insns in the 3-reg-same group so we can
> remove all the support/loop code from the old decoder.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.i
On 4/30/20 11:10 AM, Peter Maydell wrote:
> Convert the Neon fp VMAX/VMIN/VMAXNM/VMINNM/VRECPS/VRSQRTS 3-reg-same
> insns to decodetree. (These are all the remaining non-accumulation
> instructions in this group.)
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 60
On 4/30/20 11:10 AM, Peter Maydell wrote:
> Convert the Neon integer 3-reg-same compare insns VCGE, VCGT,
> VCEQ, VACGE and VACGT to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 5 +
> target/arm/translate.c | 39 ++-
On 4/30/20 11:10 AM, Peter Maydell wrote:
> Convert the Neon integer VMUL, VMLA, and VMLS 3-reg-same inssn to
> decodetree.
>
> Since VMLA and VMLS accumulate into the destination register, we add
> a reads_vd parameter to do_3same_fp() which tells it to load the
> old value into vd before calling
Michael/Jason,
As Linux headers was updated in qemu and now include RSC/RSS/Hash
definitions, please let me know what you prefer:
1. You apply this series as is, then I submit clean-up series that will
remove all the redundant defines from virtio-net.c
2. I post v8 of this series with cleanup of a
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon float VPMIN, VPMAX and VPADD 3-reg-same insns to
> decodetree. These are the only remaining 'pairwise' operations,
> so we can delete the pairwise-specific bits of the old decoder's
> for-each-element loop now.
>
> Signed-off-by: Peter M
On 4/30/20 11:09 AM, Peter Maydell wrote:
> +TCGv_ptr fpstatus = get_fpstatus_ptr(1);
> +for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
> +tmp = neon_load_reg(a->vn, pass);
> +tmp2 = neon_load_reg(a->vm, pass);
> +fn(tmp, tmp, tmp2, fpstatus);
> +tcg_temp_fr
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon VQDMULH and VQRDMULH 3-reg-same insns to
> decodetree. These are the last integer operations in the
> 3-reg-same group.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 44 +
>
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon integer VPADD 3-reg-same insns to decodetree. These
> are 'pairwise' operations. (Note that VQRDMLAH, which shares the
> same primary opcode but has U=1, has already been converted.)
>
> Signed-off-by: Peter Maydell
> ---
> target/ar
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon integer VPMAX and VPMIN 3-reg-same insns to
> decodetree. These are 'pairwise' operations.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 71 +
> target/arm/translate.c
Sounds good to me generally.
Also, we need to identify the filter by its node name when the file names of a
node and of the filter above it are the same. And what about automatically
generated node name for the filter? We will want to pass it to the stream
routine.
Andrey
_
On 4/30/20 11:09 AM, Peter Maydell wrote:
> +for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
> +tmp = neon_load_reg(a->vn, pass);
> +tmp2 = neon_load_reg(a->vm, pass);
> +abd_fn(tmp, tmp, tmp2);
> +tcg_temp_free_i32(tmp2);
> +tmp2 = neon_load_reg(a->vd, p
That's what I suggested,
We preserve a float computing cache
typedef struct FpRecord {
uint8_t op;
float32 A;
float32 B;
} FpRecord;
FpRecord fp_cache[1024];
int fp_cache_length;
uint32_t fp_exceptions;
1. For each new fp operation we push it to the fp_cache,
2. Once we read the fp_except
Patchew URL:
https://patchew.org/QEMU/20200430115142.13430-1-peter.mayd...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20200430115142.13430-1-peter.mayd...@linaro.org
Subject: [PULL 00/31] target-arm queue
Type: seri
> On Apr 30, 2020, at 12:34 PM, Dino Papararo wrote:
>
> Maybe the fastest way to implement hardfloats for ppc could be run them by
> default and until some fpu instruction request for FPSCR register.
> At this time probably we want to check for some exception.. so QEMU could
> come back to l
On 4/30/20 11:09 AM, Peter Maydell wrote:
> +static bool do_3same_qs32(DisasContext *s, arg_3same *a, NeonGenTwoOpEnvFn
> *fn)
> +{
> +/*
> + * Saturating shift operations handled elementwise 32 bits at a
> + * time which need to pass cpu_env to the helper and where the rn
> + * an
The softfloat function floatx80_round_to_int incorrectly handles the
case of a pseudo-denormal where only the high bit of the significand
is set, ignoring that bit (treating the number as an exact zero)
rather than treating the number as an alternative representation of
+/- 2^-16382 (which may roun
The softfloat floatx80 comparisons fail to allow for pseudo-denormals,
which should compare equal to corresponding values with biased
exponent 1 rather than 0. Add an adjustment for that case when
comparing numbers with the same sign.
Note that this fix only changes floatx80_compare_internal, not
The softfloat function addFloatx80Sigs, used for addition of values
with the same sign and subtraction of values with opposite sign, fails
to handle the case where the two values both have biased exponent zero
and there is a carry resulting from adding the significands, which can
occur if one or bo
Conversions between IEEE floating-point formats should convert
signaling NaNs to quiet NaNs. Most of those in QEMU's softfloat code
do so, but those for floatx80 fail to. Fix those conversions to
silence signaling NaNs as well.
Signed-off-by: Joseph Myers
---
fpu/softfloat.c | 24 +
Attempting to run the GCC and glibc testsuites for i686 under QEMU
shows up a range of bugs in the x87 floating-point emulation. This
series fixes some bugs (found both through those testsuites and
through subsequent code inspection) that appear to be in the softfloat
code itself rather than in th
On Thu, 16 Apr 2020 18:59:57 +0100
Sergei Trofimovich wrote:
> Fix syscall name and parameters priinter.
>
> Before the change:
>
> ```
> $ alpha-linux-user/qemu-alpha -strace -L /usr/alpha-unknown-linux-gnu/ /tmp/a
> ...
> 1274697
> %s(%d)(2097152,274903156744,274903156760,274905840712,274877
Patchew URL: https://patchew.org/QEMU/20200430113915.19550-1-jcmvb...@gmail.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
> I'm not sure HS is a higher privilege mode.
>
> HS is privilege encoding 1, which is the same as VS (VU is obviously lower).
I just checked the spec and it doesn't actually, explicitly state that
HS is a higher-privilege mode than VS. I thought this was something
implicit, but you might be right
On Thu, Apr 30, 2020 at 12:45 PM Alistair Francis wrote:
>
> On Fri, Apr 24, 2020 at 8:10 AM Jose Martins wrote:
> >
> > The spec states that on sv39x4 guest physical "address bits 63:41
> > must all be zeros, or else a guest-page-fault exception occurs.".
> > However, the check performed for th
Public bug reported:
git commit 27c94566379069fb8930bb1433dcffbf7df3203d
The global variable system_clock_scale used in hw/timer/armv7m_systick.c
is never set on the netduinoplus2 platform, it stays initialized as
zero. Using the timer with the clock source as cpu clock leads to an
infinit loop b
On 4/30/20 11:09 AM, Peter Maydell wrote:
> +for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
> +tmp = neon_load_reg(a->vn, pass);
> +tmp2 = neon_load_reg(a->vm, pass);
> +fn(tmp, tmp, tmp2);
> +tcg_temp_free_i32(tmp2);
> +neon_store_reg(a->vd, pass, tmp);
On 4/30/20 11:09 AM, Peter Maydell wrote:
> +
> +rn = tcg_temp_new_i64();
> +rm = tcg_temp_new_i64();
> +rd = tcg_temp_new_i64();
> +
> +for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
> +neon_load_reg64(rn, a->vn + pass);
> +neon_load_reg64(rm, a->vm + pass);
> +
Patchew URL:
https://patchew.org/QEMU/20200430111033.29980-1-vsement...@virtuozzo.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bas
Ping?
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 25, 2020 4:14 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; phi...@redhat.com; laur...@vivier.eu;
> riku.voi...@iki.fi; aleksandar.m.m...@gmail.com
> Subject: RE: [RFC PATCH v
Patchew URL:
https://patchew.org/QEMU/20200430111033.29980-1-vsement...@virtuozzo.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEG
On 4/30/20 11:09 AM, Peter Maydell wrote:
> We're going to want at least some of the NeonGen* typedefs
> for the refactored 32-bit Neon decoder, so move them all
> to translate.h since it makes more sense to keep them in
> one group.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate.
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon SHA instructions in the 3-reg-same group
> to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 139
> target/arm/translate.c | 46 +--
> target/ar
On 4/30/20 11:09 AM, Peter Maydell wrote:
> These don't use do_3same() because they want to
> operate on VFP double registers, whose offsets are different from the
> neon_reg_offset() calculations do_3same does.
Actually, no, it's an around the bush way of computing the same register offset.
vfp_
On Thu, 30 Apr 2020, Alex Bennée wrote:
BALATON Zoltan writes:
On Tue, 28 Apr 2020, Alex Bennée wrote:
罗勇刚(Yonggang Luo) writes:
I am confusing why only inexact are set then we can use hard-float.
The inexact behaviour of the host hardware may be different from the
guest architecture we
Patchew URL:
https://patchew.org/QEMU/1588242155-23924-1-git-send-email-che...@lemote.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 1588242155-23924-1-git-send-email-che...@lemote.com
Subject: [PATCH for-5.1 V2 0/7] mips: Add
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon VQRDMLAH and VQRDMLSH insns in the 3-reg-same group
> to decodetree. These don't use do_3same() because they want to
> operate on VFP double registers, whose offsets are different from the
> neon_reg_offset() calculations do_3same does.
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon VMUL, VMLA, VMLS and VSHL insns in the
> 3-reg-same grouping to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 44 +
> target/arm/translate.c | 28 +++
On Fri, Apr 24, 2020 at 8:10 AM Jose Martins wrote:
>
> The spec states that on sv39x4 guest physical "address bits 63:41
> must all be zeros, or else a guest-page-fault exception occurs.".
> However, the check performed for these top bits of the virtual address
> on the second stage is the same
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon VQADD/VQSUB insns in the 3-reg-same grouping
> to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 15 +++
> target/arm/translate.c | 14 ++
> target/arm/neon-dp.de
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon comparison ops in the 3-reg-same grouping
> to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 22 ++
> target/arm/translate.c | 23 +++
> target/a
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon 3-reg-same VMAX and VMIN insns to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 14 ++
> target/arm/translate.c | 21 ++---
> target/arm/neon-dp.decode
On Wed, Apr 29, 2020 at 2:08 PM Jose Martins wrote:
>
> > Your change just made it true for whenever virtulisation is enabled
> > (in which case we don't need it).
>
> This is exactly my point. As I said in the commit message, the spec
> clearly tells us that "Interrupts for higher-privilege modes
Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU
Signed-off-by: Stephen Long
---
Made the changes Richard requested. I think the only SVE2 insns left
are the FMLA and FMLS (both vector and indexed) ones.
There are a couple of patches that Richard has to review:
* this one
* TBX / TBL (not fully
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon logic ops in the 3-reg-same grouping to decodetree.
> Note that for the logic ops the 'size' field forms part of their
> decode and the actual operations are always bitwise.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon 3-reg-same VADD and VSUB insns to decodetree.
>
> Note that we don't need the neon_3r_sizes[op] check here because all
> size values are OK for VADD and VSUB; we'll add this when we convert
> the first insn that has size restrictions.
>
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon "load/store single structure to one lane" insns to
> decodetree.
>
> As this is the last set of insns in the neon load/store group,
> we can remove the whole disas_neon_ls_insn() function.
>
> Signed-off-by: Peter Maydell
> ---
> targ
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon "load single structure to all lanes" insns to
> decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 73 +
> target/arm/translate.c | 55 +--
Signed-off-by: Stephen Long
---
I made the changes Richard requested. I took out the status field for
the helper function.
include/fpu/softfloat.h| 5 +++
target/arm/helper-sve.h| 4 +++
target/arm/sve.decode | 4 +++
target/arm/sve_helper.c| 63 +
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon "load/store multiple structures" insns to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 124
> target/arm/translate.c | 91 +--
> t
28.04.2020 17:51, Vladimir Sementsov-Ogievskiy wrote:
28.04.2020 14:08, Max Reitz wrote:
On 28.04.20 10:55, Vladimir Sementsov-Ogievskiy wrote:
Hi!
I wanted to resend my "[PATCH 0/4] fix & merge block_status_above and
is_allocated_above", and returned to all the inconsistencies about
block-sta
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the V[US]DOT (scalar) insns in the 2reg-scalar-ext group
> to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 35 +
> target/arm/translate.c | 13 +---
> ta
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the VFM[AS]L (scalar) insns in the 2reg-scalar-ext group
> to decodetree. These are the last ones in the group so we can remove
> all the legacy decode for the group.
>
> Note that in disas_thumb2_insn() the parts of this encoding space
> where t
From: KONRAD Frederic
Currently "cf-core.xml" is sent to GDB when using any m68k flavor. Thing is
it uses the "org.gnu.gdb.coldfire.core" feature name and gdb 8.3 then expects
a coldfire FPU instead of the default m68881 FPU.
This is not OK because the m68881 floats registers are 96 bits wide s
Now we have support for debugging over a unix socket for linux-user
lets use it in our test harness.
Signed-off-by: Alex Bennée
---
tests/guest-debug/run-test.py | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/tests/guest-debug/run-test.py b/tests/guest-debug/r
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert VCMLA (scalar) in the 2reg-scalar-ext group to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 40 +
> target/arm/translate.c | 26 +
> target/a
We don't really need to track this fd beyond the initial creation of
the socket. We already know if the system has been initialised by
virtue of the gdbserver_state so lets remove it. This makes the later
re-factoring easier.
Signed-off-by: Alex Bennée
---
v1
- fix coding style issue
---
gdbs
While debugging over TCP is fairly straightforward now we have test
cases that want to orchestrate via make and currently a parallel build
fails as two processes can't use the same listening port. While system
emulation offers a wide cornucopia of connection methods thanks to the
chardev abstractio
BALATON Zoltan writes:
> On Tue, 28 Apr 2020, Alex Bennée wrote:
>> 罗勇刚(Yonggang Luo) writes:
>>> I am confusing why only inexact are set then we can use hard-float.
>>
>> The inexact behaviour of the host hardware may be different from the
>> guest architecture we are trying to emulate and
This test seems flaky and reports attachment even when we failed to
negotiate the architecture. However the fetching of the guest
architecture will fail tripping up the gdb AttributeError which will
trigger our early no error status exit from the test
Signed-off-by: Alex Bennée
---
tests/tcg/aar
When the gdbstub code was converted to the new API we missed a few
snafus in the various guests. Add a simple gdb test script which can
be used on all our linux-user guests to check for obvious failures.
Signed-off-by: Alex Bennée
---
v2
- use EXTRA_RUNS to queue the tests so as not to break p
From: Philippe Mathieu-Daudé
When converted to use GByteArray in commits 462474d760c and
a010bdbe719, the call to stfq_p() was removed. This call
serialize a float.
Since we now use a GByteArray, we can not use stfq_p() directly.
Introduce the gdb_get_float64() helper to load a float64 register.
It seems older and non-multiarach aware GDBs might not fail gracefully
when faced with something they don't know. For example when faced with
a target XML for s390x the Ubuntu 18.04 gdb will generate an internal
fault and prompt for a core dump.
Work around this by invoking GDB in a more batch ori
Hi,
As another release is cut from the tree we start again the collection
of patches fixes and enhancements that weren't yet ready to be
released on an unsuspecting world.
Some of these patches have been seen before in my random collection
series but these are all gdbstub related, This includes m
As gdb will generally be talking to "foreign" guests lets use that if
we can. Otherwise the chances of gdb barfing are considerably higher.
Signed-off-by: Alex Bennée
---
configure | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure b/configure
index 23b5e93752..c587871
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the V[US]DOT (vector) insns to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 32
> target/arm/translate.c | 9 +
> target/arm/neon-shared.decode | 4
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the VCADD (vector) insns to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 37 +
> target/arm/translate.c | 11 +-
> target/arm/neon-shared.decode | 3 +
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the VFM[AS]L (vector) insns to decodetree. This is the last
> insn in the legacy decoder for the 3same_ext group, so we can
> delete the legacy decoder function for the group entirely.
>
> Note that in disas_thumb2_insn() the parts of this encod
On Thu, 30 Apr 2020 at 11:19, Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> The following changes since commit 648db19685b7030aa558a4ddbd3a8e53d8c9a062:
>
> Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-04-29'
> into staging (2020-04-29 15:07:33 +0100)
>
> are a
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Add the infrastructure for building and invoking a decodetree decoder
> for the AArch32 Neon encodings. At the moment the new decoder covers
> nothing, so we always fall back to the existing hand-written decode.
>
> We follow the same pattern we did for
On 29.04.20 10:54, Christian Borntraeger wrote:
>
>
> On 28.04.20 19:13, David Hildenbrand wrote:
>> On 28.04.20 18:34, Markus Armbruster wrote:
>>> Both s390_features[S390_FEAT_PCC_CMAC_AES_256].name and
>>> s390_features[S390_FEAT_PCC_CMAC_EAES_256].name is
>>> "pcc-cmac-eaes-256". The form
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the VCMLA (vector) insns in the 3same extension group to
> decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 37 +
> target/arm/translate.c | 11 +-
> target/
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Somewhere along theline we accidentally added a duplicate
> "using D16-D31 when they don't exist" check to do_vfm_dp()
> (probably an artifact of a patchseries rebase). Remove it.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c
30.04.2020 17:27, Kevin Wolf wrote:
This tests that the backup job catches situations where the target node
has a different size than the source node. It must also forbid resize
operations when the job is already running.
Signed-off-by: Kevin Wolf
Thanks!
Reviewed-by: Vladimir Sementsov-Ogiev
On 4/30/20 9:28 AM, Stephen Long wrote:
> Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU
>
> Signed-off-by: Stephen Long
> ---
>
> I'm not too sure about the casting I'm doing willy nilly in the helper
> functions, but I think they should be ok. Also, there might be some avenues
> for optimizat
David Hildenbrand writes:
> On 28.04.20 18:34, Markus Armbruster wrote:
>> Both s390_features[S390_FEAT_PCC_CMAC_AES_256].name and
>> s390_features[S390_FEAT_PCC_CMAC_EAES_256].name is
>> "pcc-cmac-eaes-256". The former is obviously a pasto.
>>
>> Impact:
>>
>> * s390_feat_bitmap_to_ascii() mi
Convert the Neon fp VMAX/VMIN/VMAXNM/VMINNM/VRECPS/VRSQRTS 3-reg-same
insns to decodetree. (These are all the remaining non-accumulation
instructions in this group.)
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 60 +
target/arm/translate.c
30.04.2020 17:27, Kevin Wolf wrote:
Since the introduction of a backup filter node in commit 00e30f05d, the
backup block job crashes when the target image is smaller than the
source image because it will try to write after the end of the target
node without having BLK_PERM_RESIZE. (Previously, th
Convert the Neon floating point VFMA and VFMS insn to decodetree.
These are the last insns in the 3-reg-same group so we can
remove all the support/loop code from the old decoder.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 41
target/arm/translate.c | 1
Convert the Neon float VPMIN, VPMAX and VPADD 3-reg-same insns to
decodetree. These are the only remaining 'pairwise' operations,
so we can delete the pairwise-specific bits of the old decoder's
for-each-element loop now.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 63
On 4/30/20 11:09 AM, Peter Maydell wrote:
> We were accidentally permitting decode of Thumb Neon insns even if
> the CPU didn't have the FEATURE_NEON bit set, because the feature
> check was being done before the call to disas_neon_data_insn() and
> disas_neon_ls_insn() in the Arm decoder but was o
Convert the Neon integer 3-reg-same compare insns VCGE, VCGT,
VCEQ, VACGE and VACGT to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 5 +
target/arm/translate.c | 39 ++---
target/arm/neon-dp.decode | 5 +
3 fi
Convert the Neon VADD, VSUB, VABD 3-reg-same insns to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 54 +
target/arm/translate.c | 10 ++
target/arm/neon-dp.decode | 8 +
3 files changed, 65 insertions(+), 7
Convert the Neon VQDMULH and VQRDMULH 3-reg-same insns to
decodetree. These are the last integer operations in the
3-reg-same group.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 44 +
target/arm/translate.c | 24 +-
t
Convert the VQSHL, VRSHL and VQRSHL insns in the 3-reg-same
group to decodetree. We have already implemented the size==0b11
case of these insns; this commit handles the remaining sizes.
TODO: find out from rth why decodetree insists on VSHL going
into the group...
Signed-off-by: Peter Maydell
--
Convert the Neon integer VMUL, VMLA, and VMLS 3-reg-same inssn to
decodetree.
Since VMLA and VMLS accumulate into the destination register, we add
a reads_vd parameter to do_3same_fp() which tells it to load the
old value into vd before calling the callback function, in the same
way that the trans
Convert the Neon VHADD insns in the 3-reg-same group to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 62 +
target/arm/translate.c | 4 +--
target/arm/neon-dp.decode | 2 ++
3 files changed, 65 insertions(+), 3 del
Convert the Neon VRHADD, VHSUB and VABD 3-reg-same insns to
decodetree. (These are all the other insns in 3-reg-same which were
using GEN_NEON_INTEGER_OP() and which are not pairwise or
reversed-operands.)
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 3 +++
target/arm/tra
Convert the Neon integer VPADD 3-reg-same insns to decodetree. These
are 'pairwise' operations. (Note that VQRDMLAH, which shares the
same primary opcode but has U=1, has already been converted.)
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 2 ++
target/arm/translate.c
Convert the NEON VABA insn in the 3-reg-same group to decodetree.
This is the only insn in this group which does an integer
accumulate into the destination register.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 76 +
target/arm/translate.c
Convert the Neon VQADD/VQSUB insns in the 3-reg-same grouping
to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 15 +++
target/arm/translate.c | 14 ++
target/arm/neon-dp.decode | 6 ++
3 files changed, 23 insertions(+),
Convert the Neon integer VPMAX and VPMIN 3-reg-same insns to
decodetree. These are 'pairwise' operations.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 71 +
target/arm/translate.c | 16 +---
target/arm/neon-dp.decode | 9 +
Convert the Neon SHA instructions in the 3-reg-same group
to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 139
target/arm/translate.c | 46 +--
target/arm/neon-dp.decode | 10 +++
3 files changed, 151 ins
Convert the 64-bit element insns in the 3-reg-same group
to decodetree. This covers VQSHL, VRSHL and VQRSHL where
size==0b11.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 62 +
target/arm/translate.c | 38 ++--
target
Convert the Neon logic ops in the 3-reg-same grouping to decodetree.
Note that for the logic ops the 'size' field forms part of their
decode and the actual operations are always bitwise.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 19 +
target/arm/translate
We're going to want at least some of the NeonGen* typedefs
for the refactored 32-bit Neon decoder, so move them all
to translate.h since it makes more sense to keep them in
one group.
Signed-off-by: Peter Maydell
---
target/arm/translate.h | 17 +
target/arm/translate-a64.c |
Convert the VFM[AS]L (vector) insns to decodetree. This is the last
insn in the legacy decoder for the 3same_ext group, so we can
delete the legacy decoder function for the group entirely.
Note that in disas_thumb2_insn() the parts of this encoding space
where the decodetree decoder returns false
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