Convert the Neon VQDMULH and VQRDMULH 3-reg-same insns to
decodetree. These are the last integer operations in the
3-reg-same group.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
target/arm/translate-neon.inc.c | 44 +++++++++++++++++++++++++++++++++
target/arm/translate.c | 24 +-----------------
target/arm/neon-dp.decode | 3 +++
3 files changed, 48 insertions(+), 23 deletions(-)
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index 31a8e4ef486..2fab547840d 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -1277,3 +1277,47 @@ DO_3SAME_PAIR(VPMIN_S, pmin_s)
DO_3SAME_PAIR(VPMAX_U, pmax_u)
DO_3SAME_PAIR(VPMIN_U, pmin_u)
DO_3SAME_PAIR(VPADD, padd_u)
+
+static void gen_VQDMULH_s16(TCGv_i32 rd, TCGv_i32 rn, TCGv_i32 rm)
+{
+ gen_helper_neon_qdmulh_s16(rd, cpu_env, rn, rm);
+}
+
+static void gen_VQDMULH_s32(TCGv_i32 rd, TCGv_i32 rn, TCGv_i32 rm)
+{
+ gen_helper_neon_qdmulh_s32(rd, cpu_env, rn, rm);
+}
+
+static bool trans_VQDMULH_3s(DisasContext *s, arg_3same *a)
+{
+ static NeonGenTwoOpFn * const fns[] = {
+ gen_VQDMULH_s16, gen_VQDMULH_s32,
+ };
+
+ if (a->size != 1 && a->size != 2) {
+ return false;
+ }
+ return do_3same_32(s, a, fns[a->size - 1]);
+}
+
+static void gen_VQRDMULH_s16(TCGv_i32 rd, TCGv_i32 rn, TCGv_i32 rm)
+{
+ gen_helper_neon_qrdmulh_s16(rd, cpu_env, rn, rm);
+}
+
+static void gen_VQRDMULH_s32(TCGv_i32 rd, TCGv_i32 rn, TCGv_i32 rm)
+{
+ gen_helper_neon_qrdmulh_s32(rd, cpu_env, rn, rm);
+}
+
+static bool trans_VQRDMULH_3s(DisasContext *s, arg_3same *a)
+{
+ static NeonGenTwoOpFn * const fns[] = {
+ gen_VQRDMULH_s16, gen_VQRDMULH_s32,
+ };
+
+ if (a->size != 1 && a->size != 2) {
+ return false;
+ }
+ return do_3same_32(s, a, fns[a->size - 1]);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f583cc900e1..9fec1889613 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4784,6 +4784,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t
insn)
case NEON_3R_VPMAX:
case NEON_3R_VPMIN:
case NEON_3R_VPADD_VQRDMLAH:
+ case NEON_3R_VQDMULH_VQRDMULH:
/* Already handled by decodetree */
return 1;
}
@@ -4848,29 +4849,6 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
tmp2 = neon_load_reg(rm, pass);
}
switch (op) {
- case NEON_3R_VQDMULH_VQRDMULH: /* Multiply high. */
- if (!u) { /* VQDMULH */
- switch (size) {
- case 1:
- gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2);
- break;
- case 2:
- gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
- break;
- default: abort();
- }
- } else { /* VQRDMULH */
- switch (size) {
- case 1:
- gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
- break;
- case 2:
- gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
- break;
- default: abort();
- }
- }
- break;
case NEON_3R_FLOAT_ARITH: /* Floating point arithmetic. */
{
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index acaf278cc8d..8ceedd8b8d8 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -137,6 +137,9 @@ VPMAX_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 0
.... @3same_q0
VPMIN_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 1 .... @3same_q0
VPMIN_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 1 .... @3same_q0
+VQDMULH_3s 1111 001 0 0 . .. .... .... 1011 . . . 0 .... @3same
+VQRDMULH_3s 1111 001 1 0 . .. .... .... 1011 . . . 0 .... @3same
+
VPADD_3s 1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0
VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
--
2.20.1
