On 4/30/20 11:10 AM, Peter Maydell wrote: > Convert the Neon integer VMUL, VMLA, and VMLS 3-reg-same inssn to > decodetree. > > Since VMLA and VMLS accumulate into the destination register, we add > a reads_vd parameter to do_3same_fp() which tells it to load the > old value into vd before calling the callback function, in the same > way that the translate-vfp.inc.c do_vfp_3op_sp() and do_vfp_3op_dp() > functions work. > > This conversion fixes in passing an underdecoding for VMUL > (originally reported by Fredrik Strupe <fred...@strupe.net>): bit 1 > of the 'size' field must be 0. The old decoder didn't enforce this, > but the decodetree pattern does. > > The gen_VMLA_fp_reg() function performs the addition operation > with the operands in the opposite order to the old decoder: > since Neon sets 'default NaN mode' float32_add operations are > commutative so there is no behaviour difference, but putting > them this way around matches the Arm ARM pseudocode and the > required operation order for the subtraction in gen_VMLS_fp_reg(). > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target/arm/translate-neon.inc.c | 49 +++++++++++++++++++++++++++------ > target/arm/translate.c | 17 +----------- > target/arm/neon-dp.decode | 3 ++ > 3 files changed, 44 insertions(+), 25 deletions(-)
Note that we do have helper_gvec_fmul_s, similar to fadd before, but currently no mla. Otherwise, Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
