[PATCH] block/iscsi:fix heap-buffer-overflow in iscsi_aio_ioctl_cb

There is an overflow, the source 'datain.data[2]' is 100 bytes, but the 'ss' is 252 bytes.This may cause a security issue because we can access a lot of unrelated memory data. The len for sbp copy data should take the minimum of mx_sb_len and sb_len_wr, not the maximum. If we use iscsi device

[PATCH] hw/i386/amd_iommu: Fix the reserved bits definition of IOMMU commands

Many reserved bits of amd_iommu commands are defined incorrectly in QEMU. Because of it, QEMU incorrectly injects lots of illegal commands into guest VM's IOMMU event log. Signed-off-by: Wei Huang --- hw/i386/amd_iommu.c | 19 ++- 1 file changed, 10 insertions(+), 9 deletions(-)

[Bug 1859920] Re: daemoniz not working on MacOS

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1859920 Title: daemoniz no

Re: [PATCH 08/16] target/arm: Use SVEContLdSt in sve_ld1_r

On 4/16/20 6:26 AM, Peter Maydell wrote: > On Wed, 11 Mar 2020 at 06:44, Richard Henderson > wrote: >> >> First use of the new helper functions, so we can remove the >> unused markup. No longer need a scratch for user-only, as >> we completely probe the page set before reading; system mode >> sti

Re: [PATCH 11/16] target/arm: Update contiguous first-fault and no-fault loads

On 4/16/20 7:15 AM, Peter Maydell wrote: >> + * While we do not have access to the memory attributes from the PTE >> + * to tell Device memory from Normal memory, we can validly assume that >> + * non-RAM has been mapped as Device memory. Thus we indicate fault >> + * on all MMIO.

Re: [PATCH 10/16] target/arm: Use SVEContLdSt for multi-register contiguous loads

On 4/16/20 6:35 AM, Peter Maydell wrote: > On Wed, 11 Mar 2020 at 06:44, Richard Henderson > wrote: >> >> Signed-off-by: Richard Henderson >> --- >> target/arm/sve_helper.c | 223 ++-- >> 1 file changed, 79 insertions(+), 144 deletions(-) > > >> #define DO_

Re: [PATCH] Add a new PIIX option to control PCI hot unplugging of devices on non-root buses

+Julia who implemented https://patchwork.kernel.org/patch/1131/ > On Apr 18, 2020, at 3:26 AM, Laine Stump wrote: > > On 4/17/20 12:35 PM, Ani Sinha wrote: >> +Laine >>> On Apr 17, 2020, at 9:39 PM, Michael S. Tsirkin wrote: >>> >>> Problem is, I think this is not something we can support

Re: [PATCH 2/3] intc/gicv3_kvm: use kvm_gicc_access to get ICC_CTLR_EL1

Hi Peter, On 2020/4/17 19:09, Peter Maydell wrote: > On Mon, 13 Apr 2020 at 10:18, Keqian Zhu wrote: >> >> Replace kvm_device_access with kvm_gicc_access to simplify >> code. >> >> Signed-off-by: Keqian Zhu >> --- >> hw/intc/arm_gicv3_kvm.c | 5 ++--- >> 1 file changed, 2 insertions(+), 3 delet

Re: [PATCH 06/16] target/arm: Add sve infrastructure for page lookup

On 4/16/20 6:03 AM, Peter Maydell wrote: >> +#ifdef CONFIG_USER_ONLY >> +memset(&info->attrs, 0, sizeof(info->attrs)); > > Could just write "info->attrs = {};" ? Not quite. Correct syntax would be attrs = (MemTxAttrs){ }. I don't see that as an improvement over memset though. >> +int16_

[Bug 1873542] [NEW] Windows 98 videocard passthrough - unable to load higher resolution -Desktop, after some games crashes, without whole physical machine reset..

Public bug reported: When you are using games which are using fullscreen switching resolutions (some old games are 640x480 or 800x600 max), videocard is often stuck after crash and whole Linux machine has to be rebooted, to fix it.. VM reboot is not enough. That stuck is strange one, after rest

Re: [PATCH v25 00/10] Add ARMv8 RAS virtualization support in QEMU

On 2020/4/17 21:32, Peter Maydell wrote: > On Fri, 10 Apr 2020 at 12:46, Dongjiu Geng wrote: >> >> In the ARMv8 platform, the CPU error types includes synchronous external >> abort(SEA) >> and SError Interrupt (SEI). If exception happens in guest, host does not >> know the detailed >> informa

Re: [PATCH 04/16] target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn

On 4/16/20 5:19 AM, Peter Maydell wrote: > On Wed, 11 Mar 2020 at 06:44, Richard Henderson > wrote: >> >> Use the "normal" memory access functions, rather than the >> softmmu internal helper functions directly. >> >> Since fb901c905dc3, cpu_mem_index is now a simple extract >> from env->hflags and

Re: [PATCH 03/16] exec: Add cpu_probe_watchpoint

On 4/16/20 5:08 AM, Peter Maydell wrote: >> void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, >>MemTxAttrs attrs, int flags, uintptr_t ra); >> +bool cpu_probe_watchpoint(CPUState *cpu, vaddr addr, vaddr len, int flags); > > Could we have a doc comment for

Re: [PATCH] resend slave fd to vhost when reconnect to vhost

On Fri, Apr 17, 2020 at 01:14:00PM +0800, ni.xun.in...@gmail.com wrote: > > From: Ni Xun > > when reconnecting to vhost server, it doesn't send slave fd to vhost > as the slave fd is only sent in vhost_user_init. also resend the slave fd > in vhost reconnect. > I don’t think that’s correct. Se

Re: Avoid copying unallocated clusters during full backup

On Fri, Apr 17, 2020 at 5:34 PM John Snow wrote: > > > On 4/17/20 6:57 PM, Leo Luan wrote: > > On Fri, Apr 17, 2020 at 1:24 PM Eric Blake > > wrote: > > > > On 4/17/20 3:11 PM, John Snow wrote: > > > > >> + > > >> +if (s->sync_mode == MIRROR_SYNC_MODE_FU

Re: Avoid copying unallocated clusters during full backup

On 4/17/20 6:57 PM, Leo Luan wrote: > On Fri, Apr 17, 2020 at 1:24 PM Eric Blake > wrote: > > On 4/17/20 3:11 PM, John Snow wrote: > > >> + > >> +    if (s->sync_mode == MIRROR_SYNC_MODE_FULL && > >> +       s->bcs->target->bs->drv != NULL && > >>

[PATCH] net: tulip: Set PCI revision to match dec21143

The tulip driver claims to emulate dec21143 and it does not emulate dec21142. The dec21142 and dec21143 can be discerned by the PCI revision register, where dec21142 reports value < 0x20 and dec21143 value >= 0x20. E.g. the U-Boot 'tulip' driver also only supports dec21143 and verifies that the PCI

Re: [PATCH v2 02/16] accel/tcg: Add probe_access_flags

On 4/16/20 4:54 AM, Peter Maydell wrote: >> -target_ulong tlb_addr; >> -size_t elt_ofs; >> -int wp_access; >> - >> -g_assert(-(addr | TARGET_PAGE_MASK) >= size); >> - >> -switch (access_type) { >> -case MMU_DATA_LOAD: >> -elt_ofs = offsetof(CPUTLBEntry, addr_read); >

Re: [PATCH 2/4] target/arm: Implement SVE2 RADDHNB, RADDHNT

On 4/17/20 2:24 PM, Richard Henderson wrote: > On 4/17/20 9:22 AM, Stephen Long wrote: >> +#define DO_RADDHN(N, M, SH) ((N + M + (1 << (SH - 1))) >> SH) > > This formula will overflow. See DO_RSHR -- with some added parenthesis, we > could actually reuse that macro. My bad. While it does overfl

[Bug 1873341] Re: Qemu Win98 VM with KVM videocard passthrough DOS mode video is not working for most of games..

** Description changed: Hello, im using Win98 machine with KVM videocards passthrough which is working fine, but when i try Windows 98 - Dosbox mode, there is something work with all videocards which i tried PCI-E/PCI - Nvidia, 3Dfx, Matrox. - Often is framerate is very slow, as slidesho

[Bug 1873338] Re: Dos on the fly CD image replacement is not Working with DOS

I tried Win98 virtual machine here its working fine, without reboot. Im using MS-DOS 7.1 - integrated within and Win9x and classic MSDEX or SHSUCDX drivers for CD-ROM, but o dpmt thing that it matters. -- You received this bug notification because you are a member of qemu- devel-ml, which is su

Re: [PATCH v1 0/6] target-microblaze: Misc configurability #2

Patchew URL: https://patchew.org/QEMU/20200417191022.5247-1-edgar.igles...@gmail.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGI

Re: Avoid copying unallocated clusters during full backup

On Fri, Apr 17, 2020 at 1:24 PM Eric Blake wrote: > On 4/17/20 3:11 PM, John Snow wrote: > > >> + > >> +if (s->sync_mode == MIRROR_SYNC_MODE_FULL && > >> + s->bcs->target->bs->drv != NULL && > >> + strncmp(s->bcs->target->bs->drv->format_name, "qcow2", 5) == 0 > && > >> + s-

Re: [PATCH RFC v2 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface

On Fri, Apr 10, 2020 at 9:16 PM Yifei Jiang wrote: > > Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c. > Meanwhile, add kvm support in configure file. > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis Alistair > --- > confi

Re: [PATCH v7 39/61] target/riscv: vector floating-point compare instructions

On Mon, Mar 30, 2020 at 9:55 AM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 37 + > target/riscv/insn32.decode | 12 ++ > target/riscv/insn_trans/trans_rvv.inc.c | 35 + > tar

Re: Avoid copying unallocated clusters during full backup

On Fri, Apr 17, 2020 at 1:11 PM John Snow wrote: > > > On 4/17/20 2:33 PM, Leo Luan wrote: > > When doing a full backup from a single layer qcow2 disk file to a new > > qcow2 file, the backup_run function does not unset unallocated parts in > > the copy bit map. The subsequent backup_loop call g

Re: [PATCH v7 38/61] target/riscv: vector floating-point sign-injection instructions

On Mon, Mar 30, 2020 at 9:53 AM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 19 ++ > target/riscv/insn32.decode | 6 ++ > target/riscv/insn_trans/t

Re: [PATCH v7 36/61] target/riscv: vector floating-point square-root instruction

On Mon, Mar 30, 2020 at 9:49 AM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 4 +++ > target/riscv/insn32.decode | 3 ++ > target/riscv/insn_trans/tran

Re: [PATCH v7 35/61] target/riscv: vector widening floating-point fused multiply-add instructions

On Mon, Mar 30, 2020 at 9:47 AM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 17 + > target/riscv/insn32.decode | 8 +++ > target/riscv/insn_trans/t

Re: [PATCH] qemu-img: Fix stale doc comment

On 4/17/20 5:12 PM, Eric Blake wrote: Missed in commit e13c59fa. Signed-off-by: Eric Blake --- qemu-img-cmds.hx | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) and I should have grepped for other instances; this needs to be squashed in: diff --git i/qemu-img.c w/qemu-img.c index d90

Re: [PATCH v7 30/61] target/riscv: vector single-width floating-point add/subtract instructions

On Mon, Mar 30, 2020 at 9:37 AM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 16 > target/riscv/insn32.decode | 5 + > target/riscv/insn_trans/tr

[PATCH] qemu-img: Fix stale doc comment

Missed in commit e13c59fa. Signed-off-by: Eric Blake --- qemu-img-cmds.hx | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu-img-cmds.hx b/qemu-img-cmds.hx index 37cb36335218..5a341d06bf4d 100644 --- a/qemu-img-cmds.hx +++ b/qemu-img-cmds.hx @@ -7,7 +7,7 @@ HXCOMM command s

Re: [PATCH v7 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions

On Mon, Mar 30, 2020 at 9:45 AM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 49 + > target/riscv/insn32.decode | 16 ++ > target/riscv/insn_trans/

Re: [PATCH v7 31/61] target/riscv: vector widening floating-point add/subtract instructions

On Mon, Mar 30, 2020 at 9:39 AM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 17 +++ > target/riscv/insn32.decode | 8 ++ > target/riscv/insn_trans/tr

Re: [PATCH v7 28/61] target/riscv: vector single-width scaling shift instructions

On Mon, Mar 30, 2020 at 9:33 AM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 17 > target/riscv/insn32.decode | 6 ++ > target/riscv/insn_trans/t

Re: [PATCH] Add a new PIIX option to control PCI hot unplugging of devices on non-root buses

On 4/17/20 12:35 PM, Ani Sinha wrote: +Laine On Apr 17, 2020, at 9:39 PM, Michael S. Tsirkin wrote: Problem is, I think this is not something we can support with pcie or shpc. I'm reluctant to add features that only ACPI can support, we are trying to phase that out. Hmm. I see. We use conve

[v2 PATCH] target/i386: Fix the CPUID leaf CPUID_Fn80000008

CPUID leaf CPUID_Fn8008_ECX provides information about the number of threads supported by the processor. It was found that the field ApicIdSize(bits 15-12) was not set correctly. ApicIdSize is defined as the number of bits required to represent all the ApicId values within a package. Valid Va

Re: [PATCH v7 33/61] target/riscv: vector widening floating-point multiply

On Mon, Mar 30, 2020 at 9:43 AM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 5 + > target/riscv/insn32.decode | 2 ++ > target/riscv/insn_trans/tr

Re: [PATCH v7 29/61] target/riscv: vector narrowing fixed-point clip instructions

On Mon, Mar 30, 2020 at 9:35 AM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 13 +++ > target/riscv/insn32.decode | 6 + > target/riscv/insn_trans/tra

Re: [PATCH v1 6/6] target/microblaze: Add the pvr-user2 property

On Fri, Apr 17, 2020 at 12:13 PM Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > Add the pvr-user2 property to control the user-defined > PVR1 User2 register. > > Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Alistair > --- > target/microblaze/cpu.c | 2 ++ > tar

Re: [PATCH v1 5/6] target/microblaze: Add the pvr-user1 property

On Fri, Apr 17, 2020 at 12:17 PM Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > Add the pvr-user1 property to control the user-defined > PVR0 User1 field. > > Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Alistair > --- > target/microblaze/cpu.c | 4 +++- > targ

Re: [PATCH v1 4/6] target/microblaze: Add the unaligned-exceptions property

On Fri, Apr 17, 2020 at 12:10 PM Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > Add the unaligned-exceptions property to control if the core > traps unaligned memory accesses. > > Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Alistair > --- > target/microblaze/c

Re: [PATCH v1 3/6] target/microblaze: Add the div-zero-exception property

On Fri, Apr 17, 2020 at 12:15 PM Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > Add the div-zero-exception property to control if the core > traps divizions by zero. > > Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Alistair > --- > target/microblaze/cpu.c

Re: [PATCH v1 2/6] target/microblaze: Add the ill-opcode-exception property

On Fri, Apr 17, 2020 at 12:14 PM Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > Add the ill-opcode-exception property to control if illegal > instructions will raise exceptions. > > Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Alistair > --- > target/microblaze

Re: [PATCH v1 1/6] target/microblaze: Add the opcode-0x0-illegal CPU property

On Fri, Apr 17, 2020 at 12:12 PM Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > Add the opcode-0x0-illegal CPU property to control if the core > should trap opcode zero as illegal. > > Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Alistair > --- > target/microbl

Re: [PATCH 2/4] target/arm: Implement SVE2 RADDHNB, RADDHNT

On 4/17/20 9:22 AM, Stephen Long wrote: > +#define DO_RADDHN(N, M, SH) ((N + M + (1 << (SH - 1))) >> SH) This formula will overflow. See DO_RSHR -- with some added parenthesis, we could actually reuse that macro. r~

Re: [PATCH v18 4/4] iotests: 287: add qcow2 compression type test

On 4/2/20 1:36 AM, Denis Plotnikov wrote: The test checks fulfilling qcow2 requiriements for the compression requirements type feature and zstd compression type operability. Signed-off-by: Denis Plotnikov Reviewed-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/287 | 167

[Bug 1873338] Re: Dos on the fly CD image replacement is not Working with DOS

Does this work with other guests, like Windows 95/98 as far as you can tell? Is it only a problem in DOS? What exact version of DOS are you seeing the problem with? -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpa

[PATCH 0/1] vfio-ccw: Enable transparent CCW IPL from DASD

Remove the explicit prefetch check when using vfio-ccw devices. This check is not needed as all Linux channel programs are intended to use prefetch and will be executed in the same way regardless. Jared Rossi (1): vfio-ccw: Enable transparent CCW IPL from DASD hw/vfio/ccw.c | 13 +++--

[PATCH 1/1] vfio-ccw: Enable transparent CCW IPL from DASD

Remove the explicit prefetch check when using vfio-ccw devices. This check is not needed as all Linux channel programs are intended to use prefetch and will be executed in the same way regardless. Signed-off-by: Jared Rossi --- hw/vfio/ccw.c | 13 +++-- 1 file changed, 3 insertions(+), 1

Re: Avoid copying unallocated clusters during full backup

On 4/17/20 3:11 PM, John Snow wrote: + +    if (s->sync_mode == MIRROR_SYNC_MODE_FULL && +       s->bcs->target->bs->drv != NULL && +       strncmp(s->bcs->target->bs->drv->format_name, "qcow2", 5) == 0 && +       s->bcs->source->bs->backing_file[0] == '\0') This isn't going to suffice upstrea

Re: Avoid copying unallocated clusters during full backup

On 4/17/20 2:33 PM, Leo Luan wrote: > When doing a full backup from a single layer qcow2 disk file to a new > qcow2 file, the backup_run function does not unset unallocated parts in > the copy bit map.  The subsequent backup_loop call goes through these > unallocated clusters unnecessarily.  In

Re: 5.0.0-rc3 : Opcode 1f 12 0f 00 (7ce003e4) leaked temporaries

On 4/17/20 2:20 AM, Philippe Mathieu-Daudé wrote: > --enable-debug enables --enable-debug-tcg which is not designed for > performance. You might want to try '--enable-debug --disable-debug-tcg'. More importantly, --enable-debug turns off compiler optimization. That is going to be the biggest hit

Re: [[PATCH v2 0/4] Introduce Xlnx ZynqMP CAN controller for QEMU

Patchew URL: https://patchew.org/QEMU/1587148169-173268-1-git-send-email-fnu.vik...@xilinx.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST S

Re: [PATCH-for-5.1 3/3] hw: Remove unnecessary DEVICE() cast

On 4/12/20 5:09 PM, Philippe Mathieu-Daudé wrote: > diff --git a/hw/ide/piix.c b/hw/ide/piix.c > index 3b2de4c312..b402a93636 100644 > --- a/hw/ide/piix.c > +++ b/hw/ide/piix.c > @@ -193,7 +193,7 @@ int pci_piix3_xen_ide_unplug(DeviceState *dev, bool aux) > blk_unref(blk); >

Re: [PATCH-for-5.1 2/3] various: Remove unnecessary OBJECT() cast

On 4/12/20 5:09 PM, Philippe Mathieu-Daudé wrote: > -memory_region_init_io(&a->mmio, OBJECT(obj), &allwinner_ahci_mem_ops, a, > +memory_region_init_io(&a->mmio, obj, &allwinner_ahci_mem_ops, a, Acked-by: John Snow

Re: [PATCH] target/i386: Fix the CPUID leaf CPUID_Fn80000008

On 4/17/20 2:15 PM, Eduardo Habkost wrote: > Good catch, thanks for the patch. Comments below: > > On Fri, Apr 17, 2020 at 10:14:32AM -0500, Babu Moger wrote: >> CPUID leaf CPUID_Fn8008_ECX provides information about the >> number of threads supported by the processor. It was found that >>

Re: [PATCH-for-5.1 1/3] hw/ide/ahci: Use qdev gpio rather than qemu_allocate_irqs()

On 4/12/20 5:29 PM, Philippe Mathieu-Daudé wrote: > Switch to using the qdev gpio API which is preferred over > qemu_allocate_irqs(). One step to eventually deprecate and > remove qemu_allocate_irqs() one day. > > Patch created mechanically using spatch with this script > inspired from commit d

[PATCH v1 5/6] target/microblaze: Add the pvr-user1 property

From: "Edgar E. Iglesias" Add the pvr-user1 property to control the user-defined PVR0 User1 field. Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 4 +++- target/microblaze/cpu.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/microblaze/cpu.c b/targe

Re: [PATCH] target/i386: Fix the CPUID leaf CPUID_Fn80000008

Good catch, thanks for the patch. Comments below: On Fri, Apr 17, 2020 at 10:14:32AM -0500, Babu Moger wrote: > CPUID leaf CPUID_Fn8008_ECX provides information about the > number of threads supported by the processor. It was found that > the field ApicIdSize(bits 15-12) was not set correctly

[PATCH v1 3/6] target/microblaze: Add the div-zero-exception property

From: "Edgar E. Iglesias" Add the div-zero-exception property to control if the core traps divizions by zero. Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 2 ++ target/microblaze/cpu.h | 1 + target/microblaze/op_helper.c | 5 +++-- 3 files changed, 6 insertions(+

[PATCH v1 2/6] target/microblaze: Add the ill-opcode-exception property

From: "Edgar E. Iglesias" Add the ill-opcode-exception property to control if illegal instructions will raise exceptions. Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 4 target/microblaze/cpu.h | 1 + target/microblaze/translate.c | 2 +- 3 files changed, 6 i

[PATCH v1 1/6] target/microblaze: Add the opcode-0x0-illegal CPU property

From: "Edgar E. Iglesias" Add the opcode-0x0-illegal CPU property to control if the core should trap opcode zero as illegal. Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 6 +- target/microblaze/cpu.h | 1 + target/microblaze/translate.c | 2 +- 3 files changed

[PATCH v1 6/6] target/microblaze: Add the pvr-user2 property

From: "Edgar E. Iglesias" Add the pvr-user2 property to control the user-defined PVR1 User2 register. Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 2 ++ target/microblaze/cpu.h | 1 + 2 files changed, 3 insertions(+) diff --git a/target/microblaze/cpu.c b/target/microblaze/c

[PATCH v1 0/6] target-microblaze: Misc configurability #2

From: "Edgar E. Iglesias" This is another round of conversion from hardcoded regs to cpu properties. The property names are taken from the device-tree bindings. Cheers, Edgar Edgar E. Iglesias (6): target/microblaze: Add the opcode-0x0-illegal CPU property target/microblaze: Add the ill-opc

[PATCH v1 4/6] target/microblaze: Add the unaligned-exceptions property

From: "Edgar E. Iglesias" Add the unaligned-exceptions property to control if the core traps unaligned memory accesses. Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 4 target/microblaze/cpu.h | 1 + target/microblaze/translate.c | 4 ++-- 3 files changed, 7 i

[PATCH v2] 9pfs: local: ignore O_NOATIME if we don't have permissions

From: Omar Sandoval QEMU's local 9pfs server passes through O_NOATIME from the client. If the QEMU process doesn't have permissions to use O_NOATIME (namely, it does not own the file nor have the CAP_FOWNER capability), the open will fail. This causes issues when from the client's point of view,

Re: [PATCH] 9pfs: local: ignore O_NOATIME if we don't have permissions

On Fri, Apr 17, 2020 at 12:45:36PM +0200, Christian Schoenebeck wrote: > On Donnerstag, 16. April 2020 20:47:11 CEST Omar Sandoval wrote: > > > > Luckily, O_NOATIME is effectively a hint, and is often ignored by, e.g., > > > > network filesystems. open(2) notes that O_NOATIME "may not be effective

[[PATCH v2 2/4] hw/net/can: Introduce Xlnx ZynqMP CAN controller for QEMU

XlnxCAN is developed based on SocketCAN, QEMU CAN bus implementation. Bus connection and socketCAN connection for each CAN module can be set through command lines. Signed-off-by: Vikram Garhwal --- hw/net/can/Makefile.objs |1 + hw/net/can/xlnx-zynqmp-can.c | 1113 +++

[[PATCH v2 3/4] hw/net/can: Connect Xlnx ZynqMP CAN controller to ZCU102 machine

Connect CAN0 and CAN1 to ZCU102 board. Signed-off-by: Vikram Garhwal --- hw/arm/xlnx-zynqmp.c | 26 ++ include/hw/arm/xlnx-zynqmp.h | 3 +++ 2 files changed, 29 insertions(+) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index b84d153..e5f0d9f 100644

Avoid copying unallocated clusters during full backup

When doing a full backup from a single layer qcow2 disk file to a new qcow2 file, the backup_run function does not unset unallocated parts in the copy bit map. The subsequent backup_loop call goes through these unallocated clusters unnecessarily. In the case when the target and source reside in d

[[PATCH v2 0/4] Introduce Xlnx ZynqMP CAN controller for QEMU

Example for single CAN: -object can-bus,id=canbus0 \ -global driver=xlnx.zynqmp-can,property=canbus0,value=canbus0 \ -object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0 Example for connecting both CAN: -object can-bus,id=canbus0 -object can-bus,id=canbus1 \

[[PATCH v2 4/4] hw/net/can: Introduce QTEST for Xlnx CAN controller

Qtest performs five tests on Xlnx-CAN controller: It checks communication between CAN0 and CAN1 via can-bus. Tests CAN in loopback, sleep and snoop mode. Tests CAN filtering for incoming messages. Signed-off-by: Vikram Garhwal --- tests/qtest/Makefile.include | 1 + tes

[[PATCH v2 1/4] MAINTAINERS: Add maintainer entry for Xilinx CAN

Add myself as Xilinx CAN maintainer. Signed-off-by: Vikram Garhwal --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8cbc1fa..6223573 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1433,6 +1433,13 @@ F: hw/net/opencores_eth.c Devices -

Re: [PATCH v9 0/9] Clock framework API

On Mon, 6 Apr 2020 at 14:53, Damien Hedde wrote: > > Hi all, > > The series has now been fully reviewed and is ready to be merged > (obviously not for 5.0). I did this v9 to fix the small typos > Alistair spotted in the doc. I've also rebased the series on master. Applied to target-arm.next for 5

[PATCH v2] Cadence: gem: fix wraparound in 64bit descriptors

Wraparound of TX descriptor cyclic buffer only updated the low 32 bits of the descriptor. Fix that by checking if we're working with 64bit descriptors. Signed-off-by: Ramon Fried Reviewed-by: Edgar E. Iglesias --- v2: Fix indention problem. hw/net/cadence_gem.c | 9 - 1 file changed, 8

Re: [PATCH] Cadence: gem: fix wraparound in 64bit descriptors

On Fri, Apr 17, 2020 at 4:37 PM Peter Maydell wrote: > > On Thu, 16 Apr 2020 at 10:02, Ramon Fried wrote: > > > > Wraparound of TX descriptor cyclic buffer only updated > > the low 32 bits of the descriptor. > > Fix that by checking if we're working with 64bit descriptors. > > > > Signed-off-by:

Re: [PATCH v9 5/9] docs/clocks: add device's clock documentation

On 4/17/20 5:52 PM, Peter Maydell wrote: > On Mon, 6 Apr 2020 at 14:53, Damien Hedde wrote: >> >> Add the documentation about the clock inputs and outputs in devices. >> >> This is based on the original work of Frederic Konrad. >> >> Signed-off-by: Damien Hedde >> Reviewed-by: Alistair Francis

Re: [PATCH] Add a new PIIX option to control PCI hot unplugging of devices on non-root buses

+Laine > On Apr 17, 2020, at 9:39 PM, Michael S. Tsirkin wrote: > > Problem is, I think this is not something we can support with pcie or shpc. > I'm reluctant to add features that only ACPI can support, > we are trying to phase that out. Hmm. I see. We use conventional PCI and hence was lookin

[PATCH v2] qcow2: Expose bitmaps' size during measure

It's useful to know how much space can be occupied by qcow2 persistent bitmaps, even though such metadata is unrelated to the guest-visible data. Report this value as an additional field. Update iotest 190 to cover it. The addition of a new field demonstrates why we should always zero-initialize

[PATCH 4/4] target/arm: Implement SVE2 RSUBHNB, RSUBHNT

This completes the section 'SVE2 integer add/subtract narrow high part' Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 2 ++ target/arm/sve_helper.c| 10 ++ target/arm/translate-sve.c | 2 ++ 4 files changed, 22 insertions(+)

[PATCH 3/4] target/arm: Implement SVE2 SUBHNB, SUBHNT

Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 2 ++ target/arm/sve_helper.c| 10 ++ target/arm/translate-sve.c | 3 +++ 4 files changed, 23 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 5d

[PATCH 0/4] target/arm: Implement last SVE2 narrowing section

Submitting patches for the section 'SVE2 integer add/subtract narrow high part' for early review. Stephen Long (4): target/arm: Implement SVE2 ADDHNB, ADDHNT target/arm: Implement SVE2 RADDHNB, RADDHNT target/arm: Implement SVE2 SUBHNB, SUBHNT target/arm: Implement SVE2 RSUBHNB, RSUBHNT

[PATCH 2/4] target/arm: Implement SVE2 RADDHNB, RADDHNT

Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 2 ++ target/arm/sve_helper.c| 10 ++ target/arm/translate-sve.c | 2 ++ 4 files changed, 22 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 5b8

[PATCH 1/4] target/arm: Implement SVE2 ADDHNB, ADDHNT

Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 5 + target/arm/sve_helper.c| 36 target/arm/translate-sve.c | 13 + 4 files changed, 62 insertions(+) diff --git a/target/arm/helper-s

Re: [PATCH] Add a new PIIX option to control PCI hot unplugging of devices on non-root buses

On Fri, Apr 17, 2020 at 03:36:14PM +, Ani Sinha wrote: > > > > On Apr 17, 2020, at 8:57 PM, Michael S. Tsirkin wrote: > > > > Is there a real reason to do this? Can't we just limit the > > hotplug control to pcie ports? At some point I'd like us to > > start leaving piix alone.. > > Yes we

Re: QEMU Development Questions

On Fri, 17 Apr 2020 at 16:50, Randy Yates wrote: > > Thanks for the answers I've received so far - much appreciated. > > Is there a standard way to define your own custom coprocessor CP15 registers? It can be done but you very likely don't want to do it... thanks -- PMM

Re: [PATCH v9 5/9] docs/clocks: add device's clock documentation

On Mon, 6 Apr 2020 at 14:53, Damien Hedde wrote: > > Add the documentation about the clock inputs and outputs in devices. > > This is based on the original work of Frederic Konrad. > > Signed-off-by: Damien Hedde > Reviewed-by: Alistair Francis > Reviewed-by: Edgar E. Iglesias I did an edit pa

Re: [PATCH v1 1/1] hw/arm: versal: Setup the ADMA with 128bit bus-width

On Fri, Apr 17, 2020 at 8:38 AM Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > Setup the ADMA with 128bit bus-width. This matters when > FIXED BURST mode is used. > > Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Alistair > --- > hw/arm/xlnx-versal.c | 2 ++ > 1

Re: QEMU Development Questions

Thanks for the answers I've received so far - much appreciated. Is there a standard way to define your own custom coprocessor CP15 registers? Randy 1 Randy Yates, DSP/Embedded Firmware Developer Digital Signal Labs http://www.digitalsigna

Re: [PATCH] Cadence: gem: fix wraparound in 64bit descriptors

On Thu, Apr 16, 2020 at 12:02:47PM +0300, Ramon Fried wrote: > Wraparound of TX descriptor cyclic buffer only updated > the low 32 bits of the descriptor. > Fix that by checking if we're working with 64bit descriptors. Looks good to me, so with the indentation fix that Peter mentioned: Reviewed-b

[PATCH v1 1/1] hw/arm: versal: Setup the ADMA with 128bit bus-width

From: "Edgar E. Iglesias" Setup the ADMA with 128bit bus-width. This matters when FIXED BURST mode is used. Signed-off-by: Edgar E. Iglesias --- hw/arm/xlnx-versal.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index cb0122a3a6..94460f2343 1

[PATCH v1 0/1] hw/arm: versal: Setup the ADMA with 128bit bus-width

From: "Edgar E. Iglesias" Running more testcases on the upstream models I noticed that the ADMA was not setup for 128bit bus-width causing some tests to fail. This fixes that. Cheers, Edgar Edgar E. Iglesias (1): hw/arm: versal: Setup the ADMA with 128bit bus-width hw/arm/xlnx-versal.c | 2

Re: [PATCH] Add a new PIIX option to control PCI hot unplugging of devices on non-root buses

> On Apr 17, 2020, at 8:57 PM, Michael S. Tsirkin wrote: > > Is there a real reason to do this? Can't we just limit the > hotplug control to pcie ports? At some point I'd like us to > start leaving piix alone.. Yes we really need this feature as want to be able to hot plug devices into the g

[PATCH] linux-user: Prevent crash in epoll_ctl

>From 894bb5172705e46a3a04c93b4962c0f0cafee814 Mon Sep 17 00:00:00 2001 From: Giuseppe Musacchio Date: Fri, 17 Apr 2020 17:25:07 +0200 Subject: [PATCH] linux-user: Prevent crash in epoll_ctl The `event` parameter is ignored by the kernel if `op` is EPOLL_CTL_DEL, do the same and avoid returning E

Re: Hot unplug disabling on pci-pci bridge

Hi Igor: > On Mar 24, 2020, at 7:47 PM, Igor Mammedov wrote: > > if you are interested in hacking ACPI PCI hotplug more, look at how > build_append_pci_bus_devices() works I am trying to disable hot unplug of a device on PCI-PCI bridge without removing the capability to hot plug. Will it be e

Re: [PATCH] Add a new PIIX option to control PCI hot unplugging of devices on non-root buses

On Fri, Apr 17, 2020 at 03:13:31PM +, Ani Sinha wrote: > A new option "use_acpi_unplug" is introduced for PIIX which will > selectively only disable hot unplugging of both hot plugged and > cold plugged PCI devices on non-root PCI buses. This will prevent > hot unplugging of devices from Window

[PATCH] Add a new PIIX option to control PCI hot unplugging of devices on non-root buses

A new option "use_acpi_unplug" is introduced for PIIX which will selectively only disable hot unplugging of both hot plugged and cold plugged PCI devices on non-root PCI buses. This will prevent hot unplugging of devices from Windows based guests from system tray but will not prevent devices from b

[PATCH] target/i386: Fix the CPUID leaf CPUID_Fn80000008

CPUID leaf CPUID_Fn8008_ECX provides information about the number of threads supported by the processor. It was found that the field ApicIdSize(bits 15-12) was not set correctly. ApicIdSize is defined as the number of bits required to represent all the ApicId values within a package. Valid Va

Re: [PATCH v9 1/9] hw/core/clock: introduce clock object

On Mon, 6 Apr 2020 at 14:53, Damien Hedde wrote: > > This object may be used to represent a clock inside a clock tree. > > A clock may be connected to another clock so that it receives update, > through a callback, whenever the source/parent clock is updated. > --- a/hw/core/trace-events > +++ b/

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