On Mon, Mar 30, 2020 at 9:43 AM LIU Zhiwei <zhiwei_...@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/helper.h | 5 +++++
> target/riscv/insn32.decode | 2 ++
> target/riscv/insn_trans/trans_rvv.inc.c | 4 ++++
> target/riscv/vector_helper.c | 22 ++++++++++++++++++++++
> 4 files changed, 33 insertions(+)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index fa1558179a..5b3340a4af 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -846,3 +846,8 @@ DEF_HELPER_6(vfdiv_vf_d, void, ptr, ptr, i64, ptr, env,
> i32)
> DEF_HELPER_6(vfrdiv_vf_h, void, ptr, ptr, i64, ptr, env, i32)
> DEF_HELPER_6(vfrdiv_vf_w, void, ptr, ptr, i64, ptr, env, i32)
> DEF_HELPER_6(vfrdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32)
> +
> +DEF_HELPER_6(vfwmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfwmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfwmul_vf_h, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfwmul_vf_w, void, ptr, ptr, i64, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 16fd938261..1d963f0b8a 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -461,6 +461,8 @@ vfmul_vf 100100 . ..... ..... 101 ..... 1010111
> @r_vm
> vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm
> vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm
> vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm
> +vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm
> +vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm
>
> vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
> vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
> b/target/riscv/insn_trans/trans_rvv.inc.c
> index 77c5222c4d..5395063b1b 100644
> --- a/target/riscv/insn_trans/trans_rvv.inc.c
> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> @@ -2075,3 +2075,7 @@ GEN_OPFVV_TRANS(vfdiv_vv, opfvv_check)
> GEN_OPFVF_TRANS(vfmul_vf, opfvf_check)
> GEN_OPFVF_TRANS(vfdiv_vf, opfvf_check)
> GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check)
> +
> +/* Vector Widening Floating-Point Multiply */
> +GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwmul_vf)
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index a9fdf47c2a..bbe3719e69 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -3409,3 +3409,25 @@ RVVCALL(OPFVF2, vfrdiv_vf_d, OP_UUU_D, H8, H8,
> float64_rdiv)
> GEN_VEXT_VF(vfrdiv_vf_h, 2, 2, clearh)
> GEN_VEXT_VF(vfrdiv_vf_w, 4, 4, clearl)
> GEN_VEXT_VF(vfrdiv_vf_d, 8, 8, clearq)
> +
> +/* Vector Widening Floating-Point Multiply */
> +static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s)
> +{
> + return float32_mul(float16_to_float32(a, true, s),
> + float16_to_float32(b, true, s), s);
> +}
> +
> +static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s)
> +{
> + return float64_mul(float32_to_float64(a, s),
> + float32_to_float64(b, s), s);
> +
> +}
> +RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16)
> +RVVCALL(OPFVV2, vfwmul_vv_w, WOP_UUU_W, H8, H4, H4, vfwmul32)
> +GEN_VEXT_VV_ENV(vfwmul_vv_h, 2, 4, clearl)
> +GEN_VEXT_VV_ENV(vfwmul_vv_w, 4, 8, clearq)
> +RVVCALL(OPFVF2, vfwmul_vf_h, WOP_UUU_H, H4, H2, vfwmul16)
> +RVVCALL(OPFVF2, vfwmul_vf_w, WOP_UUU_W, H8, H4, vfwmul32)
> +GEN_VEXT_VF(vfwmul_vf_h, 2, 4, clearl)
> +GEN_VEXT_VF(vfwmul_vf_w, 4, 8, clearq)
> --
> 2.23.0
>
