On Mon, Mar 30, 2020 at 9:53 AM LIU Zhiwei <zhiwei_...@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/helper.h | 19 ++++++
> target/riscv/insn32.decode | 6 ++
> target/riscv/insn_trans/trans_rvv.inc.c | 8 +++
> target/riscv/vector_helper.c | 85 +++++++++++++++++++++++++
> 4 files changed, 118 insertions(+)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 12d959ba0d..d6e7ce57be 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -934,3 +934,22 @@ DEF_HELPER_6(vfmin_vf_d, void, ptr, ptr, i64, ptr, env,
> i32)
> DEF_HELPER_6(vfmax_vf_h, void, ptr, ptr, i64, ptr, env, i32)
> DEF_HELPER_6(vfmax_vf_w, void, ptr, ptr, i64, ptr, env, i32)
> DEF_HELPER_6(vfmax_vf_d, void, ptr, ptr, i64, ptr, env, i32)
> +
> +DEF_HELPER_6(vfsgnj_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfsgnj_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfsgnj_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfsgnjn_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfsgnjn_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfsgnjn_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfsgnjx_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfsgnjx_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfsgnjx_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfsgnj_vf_h, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfsgnj_vf_w, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfsgnj_vf_d, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfsgnjn_vf_h, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfsgnjn_vf_w, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfsgnjn_vf_d, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfsgnjx_vf_h, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfsgnjx_vf_w, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfsgnjx_vf_d, void, ptr, ptr, i64, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 5ec5595e2c..ce2f497ed2 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -494,6 +494,12 @@ vfmin_vv 000100 . ..... ..... 001 ..... 1010111
> @r_vm
> vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
> vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
> vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm
> +vfsgnj_vv 001000 . ..... ..... 001 ..... 1010111 @r_vm
> +vfsgnj_vf 001000 . ..... ..... 101 ..... 1010111 @r_vm
> +vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm
> +vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm
> +vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm
> +vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm
>
> vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
> vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
> b/target/riscv/insn_trans/trans_rvv.inc.c
> index ea00e2dfb0..4963004dd4 100644
> --- a/target/riscv/insn_trans/trans_rvv.inc.c
> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> @@ -2155,3 +2155,11 @@ GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
> GEN_OPFVV_TRANS(vfmax_vv, opfvv_check)
> GEN_OPFVF_TRANS(vfmin_vf, opfvf_check)
> GEN_OPFVF_TRANS(vfmax_vf, opfvf_check)
> +
> +/* Vector Floating-Point Sign-Injection Instructions */
> +GEN_OPFVV_TRANS(vfsgnj_vv, opfvv_check)
> +GEN_OPFVV_TRANS(vfsgnjn_vv, opfvv_check)
> +GEN_OPFVV_TRANS(vfsgnjx_vv, opfvv_check)
> +GEN_OPFVF_TRANS(vfsgnj_vf, opfvf_check)
> +GEN_OPFVF_TRANS(vfsgnjn_vf, opfvf_check)
> +GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check)
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index a2c427b26c..3f01fdd83c 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -3843,3 +3843,88 @@ RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8,
> float64_maxnum)
> GEN_VEXT_VF(vfmax_vf_h, 2, 2, clearh)
> GEN_VEXT_VF(vfmax_vf_w, 4, 4, clearl)
> GEN_VEXT_VF(vfmax_vf_d, 8, 8, clearq)
> +
> +/* Vector Floating-Point Sign-Injection Instructions */
> +static uint16_t fsgnj16(uint16_t a, uint16_t b, float_status *s)
> +{
> + return deposit64(b, 0, 15, a);
> +}
> +
> +static uint32_t fsgnj32(uint32_t a, uint32_t b, float_status *s)
> +{
> + return deposit64(b, 0, 31, a);
> +}
> +
> +static uint64_t fsgnj64(uint64_t a, uint64_t b, float_status *s)
> +{
> + return deposit64(b, 0, 63, a);
> +}
> +
> +RVVCALL(OPFVV2, vfsgnj_vv_h, OP_UUU_H, H2, H2, H2, fsgnj16)
> +RVVCALL(OPFVV2, vfsgnj_vv_w, OP_UUU_W, H4, H4, H4, fsgnj32)
> +RVVCALL(OPFVV2, vfsgnj_vv_d, OP_UUU_D, H8, H8, H8, fsgnj64)
> +GEN_VEXT_VV_ENV(vfsgnj_vv_h, 2, 2, clearh)
> +GEN_VEXT_VV_ENV(vfsgnj_vv_w, 4, 4, clearl)
> +GEN_VEXT_VV_ENV(vfsgnj_vv_d, 8, 8, clearq)
> +RVVCALL(OPFVF2, vfsgnj_vf_h, OP_UUU_H, H2, H2, fsgnj16)
> +RVVCALL(OPFVF2, vfsgnj_vf_w, OP_UUU_W, H4, H4, fsgnj32)
> +RVVCALL(OPFVF2, vfsgnj_vf_d, OP_UUU_D, H8, H8, fsgnj64)
> +GEN_VEXT_VF(vfsgnj_vf_h, 2, 2, clearh)
> +GEN_VEXT_VF(vfsgnj_vf_w, 4, 4, clearl)
> +GEN_VEXT_VF(vfsgnj_vf_d, 8, 8, clearq)
> +
> +static uint16_t fsgnjn16(uint16_t a, uint16_t b, float_status *s)
> +{
> + return deposit64(~b, 0, 15, a);
> +}
> +
> +static uint32_t fsgnjn32(uint32_t a, uint32_t b, float_status *s)
> +{
> + return deposit64(~b, 0, 31, a);
> +}
> +
> +static uint64_t fsgnjn64(uint64_t a, uint64_t b, float_status *s)
> +{
> + return deposit64(~b, 0, 63, a);
> +}
> +
> +RVVCALL(OPFVV2, vfsgnjn_vv_h, OP_UUU_H, H2, H2, H2, fsgnjn16)
> +RVVCALL(OPFVV2, vfsgnjn_vv_w, OP_UUU_W, H4, H4, H4, fsgnjn32)
> +RVVCALL(OPFVV2, vfsgnjn_vv_d, OP_UUU_D, H8, H8, H8, fsgnjn64)
> +GEN_VEXT_VV_ENV(vfsgnjn_vv_h, 2, 2, clearh)
> +GEN_VEXT_VV_ENV(vfsgnjn_vv_w, 4, 4, clearl)
> +GEN_VEXT_VV_ENV(vfsgnjn_vv_d, 8, 8, clearq)
> +RVVCALL(OPFVF2, vfsgnjn_vf_h, OP_UUU_H, H2, H2, fsgnjn16)
> +RVVCALL(OPFVF2, vfsgnjn_vf_w, OP_UUU_W, H4, H4, fsgnjn32)
> +RVVCALL(OPFVF2, vfsgnjn_vf_d, OP_UUU_D, H8, H8, fsgnjn64)
> +GEN_VEXT_VF(vfsgnjn_vf_h, 2, 2, clearh)
> +GEN_VEXT_VF(vfsgnjn_vf_w, 4, 4, clearl)
> +GEN_VEXT_VF(vfsgnjn_vf_d, 8, 8, clearq)
> +
> +static uint16_t fsgnjx16(uint16_t a, uint16_t b, float_status *s)
> +{
> + return deposit64(b ^ a, 0, 15, a);
> +}
> +
> +static uint32_t fsgnjx32(uint32_t a, uint32_t b, float_status *s)
> +{
> + return deposit64(b ^ a, 0, 31, a);
> +}
> +
> +static uint64_t fsgnjx64(uint64_t a, uint64_t b, float_status *s)
> +{
> + return deposit64(b ^ a, 0, 63, a);
> +}
> +
> +RVVCALL(OPFVV2, vfsgnjx_vv_h, OP_UUU_H, H2, H2, H2, fsgnjx16)
> +RVVCALL(OPFVV2, vfsgnjx_vv_w, OP_UUU_W, H4, H4, H4, fsgnjx32)
> +RVVCALL(OPFVV2, vfsgnjx_vv_d, OP_UUU_D, H8, H8, H8, fsgnjx64)
> +GEN_VEXT_VV_ENV(vfsgnjx_vv_h, 2, 2, clearh)
> +GEN_VEXT_VV_ENV(vfsgnjx_vv_w, 4, 4, clearl)
> +GEN_VEXT_VV_ENV(vfsgnjx_vv_d, 8, 8, clearq)
> +RVVCALL(OPFVF2, vfsgnjx_vf_h, OP_UUU_H, H2, H2, fsgnjx16)
> +RVVCALL(OPFVF2, vfsgnjx_vf_w, OP_UUU_W, H4, H4, fsgnjx32)
> +RVVCALL(OPFVF2, vfsgnjx_vf_d, OP_UUU_D, H8, H8, fsgnjx64)
> +GEN_VEXT_VF(vfsgnjx_vf_h, 2, 2, clearh)
> +GEN_VEXT_VF(vfsgnjx_vf_w, 4, 4, clearl)
> +GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8, clearq)
> --
> 2.23.0
>
