[PATCH v20 5/5] target-arm: kvm64: handle SIGBUS signal from kernel or KVM

From: Dongjiu Geng Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type, translates the host VA delivered by host to guest PA, then fills this PA to guest APEI GHES memory, then notifies guest according to the SIGBUS type. When guest accesses the poisoned memory, it will gener

[PATCH v20 3/5] ACPI: Add APEI GHES table generation support

From: Dongjiu Geng This patch implements APEI GHES Table generation via fw_cfg blobs. Now it only supports ARMv8 SEA, a type of GHESv2 error source. Afterwards, we can extend the supported types if needed. For the CPER section, currently it is memory section because kernel mainly wants userspace

[PATCH v20 4/5] KVM: Move hwpoison page related functions into kvm-all.c

From: Dongjiu Geng kvm_hwpoison_page_add() and kvm_unpoison_all() will both be used by X86 and ARM platforms, so moving them into "accel/kvm/kvm-all.c" to avoid duplicate code. For architectures that don't use the poison-list functionality the reset handler will harmlessly do nothing, so let's r

[PATCH v20 1/5] hw/arm/virt: Introduce a RAS machine option

From: Dongjiu Geng RAS Virtualization feature is not supported now, so add a RAS machine option and disable it by default. Signed-off-by: Dongjiu Geng Signed-off-by: Xiang Zheng --- hw/arm/virt.c | 23 +++ include/hw/arm/virt.h | 1 + 2 files changed, 24 insertion

[PATCH v20 2/5] docs: APEI GHES generation and CPER record description

From: Dongjiu Geng Add APEI/GHES detailed design document Signed-off-by: Dongjiu Geng Signed-off-by: Xiang Zheng --- docs/specs/acpi_hest_ghes.rst | 95 +++ docs/specs/index.rst | 1 + 2 files changed, 96 insertions(+) create mode 100644 docs/specs/a

[PATCH v20 0/5] Add ARMv8 RAS virtualization support in QEMU

In the ARMv8 platform, the CPU error types are synchronous external abort(SEA) and SError Interrupt (SEI). If exception happens in guest, sometimes it's better for guest to perform the recovery, because host does not know the detailed information of guest. For example, if an exception happens in a

[PATCH v2 4/6] migration/multifd: used must not be 0 for a pending job

After thread synchronization request is handled in another case, this means when we only get pending_job when there is used pages. Signed-off-by: Wei Yang --- migration/ram.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/migration/ram.c b/migration/ram.c index 6

[PATCH v2 1/6] migration/multifd: move Params update and pages cleanup into multifd_send_fill_packet()

Fill data and update/cleanup related field in one place. Also make the code a little clean. Signed-off-by: Wei Yang --- migration/ram.c | 20 +++- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/migration/ram.c b/migration/ram.c index 5876054195..35f147388b 100644

[PATCH v2 0/6] migration/multifd: a new mechanism for send thread sync

Current send thread could work while the sync mechanism has some problem: * has spuriously wakeup * number of channels_ready will *overflow* the number of real channels The reason is: * if MULTIFD_FLAG_SYNC is set in the middle of send thread running, there is one more spurious wakeup

Re: [RFC 0/3] block/file-posix: Work around XFS bug

Patchew URL: https://patchew.org/QEMU/20191025095849.25283-1-mre...@redhat.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #

[PATCH v2 6/6] migration/multifd: there is no spurious wakeup now

The spurious wakeup is gone. Signed-off-by: Wei Yang --- migration/ram.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/migration/ram.c b/migration/ram.c index fccdbfabc5..73ace40b1b 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -1168,8 +1168,8 @@ static void *mu

Re: [PATCH 0/4] SCSI COMPARE_AND_WRITE support

Patchew URL: https://patchew.org/QEMU/1571996163-27688-1-git-send-email-baiyao...@cmss.chinamobile.com/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PATCH 0/4] SCSI COMPARE_AND_WRITE support Type: series Message-id: 1571996163-2768

[PATCH v2 5/6] migration/multifd: use boolean for pending_job is enough

After synchronization request is handled in another case, there only could be one pending_job for one send thread at most. This is fine to use boolean to represent this behavior. Signed-off-by: Wei Yang --- migration/ram.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --g

[PATCH v2 16/27] riscv: plic: Always set sip.SEIP bit for HS

When the PLIC generates an interrupt ensure we always set it for the SIP CSR that corresponds to the HS (V=0) register. Signed-off-by: Alistair Francis --- hw/riscv/sifive_plic.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/si

[PATCH v2 2/6] migration/multifd: notify channels_ready when send thread starts

multifd_send_state->channels_ready is initialized to 0. It is proper to let main thread know we are ready when thread start running. Current implementation works since ram_save_setup() calls multifd_send_sync_main() which wake up send thread and posts channels_ready. This behavior will introduce s

[PATCH v2 3/6] migration/multifd: use sync field to synchronize send threads

Add a field in MultiFDSendParams to indicate there is a request to synchronize send threads. By doing so, send_thread will just post sem_sync on synchronization request and channels_ready will not *overflow*. Signed-off-by: Wei Yang --- migration/ram.c | 30 -- 1 fil

[PATCH v2 14/27] target/ricsv: Flush the TLB on virtulisation mode changes

To ensure our TLB isn't out-of-date we flush it on all virt mode changes. Unlike priv mode this isn't saved in the mmu_idx as all guests share V=1. The easiest option is just to flush on all changes. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 5 +

[PATCH v2 19/27] target/riscv: Add hfence instructions

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/insn32.decode| 23 ++- .../riscv/insn_trans/trans_privileged.inc.c | 40 +++ 2 files changed, 54 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn32.decode b/tar

[PATCH v2 08/27] target/riscv: Dump Hypervisor registers if enabled

Dump the Hypervisor registers and the current Hypervisor state. While we are editing this code let's also dump stvec and scause. Signed-off-by: Alistair Francis Signed-off-by: Atish Patra Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 34 ++ 1 file change

[PATCH v2 05/27] target/riscv: Fix CSR perm checking for HS mode

Update the CSR permission checking to work correctly when we are in HS-mode. Signed-off-by: Alistair Francis --- target/riscv/csr.c | 18 ++ 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index da02f9f0b1..08956aa557 100644

[PATCH v2 04/27] target/riscv: Add the force HS exception mode

Add a FORCE_HS_EXCEP mode to the RISC-V virtulisation status. This bit specifies if an exeption should be taken to HS mode no matter the current delegation status. This is used when an exeption must be taken to HS mode, such as when a second level page fault occurs. Signed-off-by: Alistair Francis

[PATCH v2 00/27] Add RISC-V Hypervisor Extension v0.4

This patch series adds the RISC-V Hypervisor extension v0.4. This is the latest draft spec of the Hypervisor extension. The Hypervisor extension is disabled by default, so this series should result in no changes to anyone using QEMU unless they enable the extension. The extention can be enabled

[PATCH v2 01/27] target/riscv: Don't set write permissions on dirty PTEs

Setting write permission on dirty PTEs results in userspace inside a Hypervisor guest (VU) becoming corrupted. This appears to be because it ends up with write permission in the second stage translation in cases where we aren't doing a store. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng

[PATCH v1 1/1] opensbi: Upgrade from v0.4 to v0.5

This release has: Lot of critical fixes Hypervisor extension support SBI v0.2 base extension support Debug prints support Handle traps when doing unpriv load/store Allow compiling without FP support Use git describe to generate boot-time banner Andes AE350 platform s

[PATCH 1/2] migration/multifd: clean pages after filling packet

This is a preparation for the next patch: not use multifd during postcopy. Without enabling postcopy, everything looks good. While after enabling postcopy, migration may fail even not use multifd during postcopy. The reason is the pages is not properly cleared and *old* target page will conti

[PATCH 0/2] not use multifd during postcopy

We don't support multifd during postcopy, but user still could enable both multifd and postcopy. This leads to migration failure. Patch 1 does proper cleanup, otherwise we may have data corruption. Patch 2 does the main job. BTW, current multifd synchronization method needs a cleanup. Will send a

[PATCH v2 15/27] target/riscv: Generate illegal instruction on WFI when V=1

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/op_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index d150551bc9..beb34e705b 100644 --- a/target/riscv/op_helper.c +++ b/target/ri

[PATCH v2 20/27] target/riscv: Disable guest FP support based on virtual status

When the Hypervisor extension is in use we only enable floating point support when both status and vsstatus have enabled floating point support. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/targe

[PATCH v2 27/27] target/riscv: Allow enabling the Hypervisor extension

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 5 + target/riscv/cpu.h | 1 + 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 03622825f3..6d02e61e8a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@

[PATCH v2 18/27] target/riscv: Add Hypervisor trap return support

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/op_helper.c | 66 1 file changed, 54 insertions(+), 12 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index beb34e705b..e5128570e6 100644 --- a/ta

[PATCH v2 26/27] target/riscv: Add the MSTATUS_MPV_ISSET helper macro

Add a helper macro MSTATUS_MPV_ISSET() which will determine if the MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V. Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 11 +++ target/riscv/cpu_helper.c | 4 ++-- target/riscv/op_helper.c | 2 +- target/riscv/transl

[PATCH v2 22/27] target/riscv: Respect MPRV and SPRV for floating point ops

mark_fs_dirty() is the only place in translate.c that uses the virt_enabled bool. Let's respect the contents of MSTATUS.MPRV and HSTATUS.SPRV when setting the bool as this is used for performing floating point operations when V=0. Signed-off-by: Alistair Francis --- target/riscv/translate.c | 16

[PATCH v2 17/27] target/riscv: Add hypvervisor trap support

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 4 +-- target/riscv/cpu_helper.c | 71 +-- target/riscv/csr.c| 4 +-- 3 files changed, 65 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu_bits.h

[PATCH v2 25/27] target/riscv: Add support for the 32-bit MSTATUSH CSR

Signed-off-by: Alistair Francis --- target/riscv/cpu.c| 6 ++ target/riscv/cpu.h| 7 +++ target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_helper.c | 7 +++ target/riscv/csr.c| 25 + target/riscv/op_helper.c | 4 6 files cha

[PATCH v2 12/27] target/riscv: Add virtual register swapping function

Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 13 +- target/riscv/cpu_bits.h | 7 target/riscv/cpu_helper.c | 88 +++ 3 files changed, 107 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5b7

[PATCH v2 24/27] target/riscv: Implement second stage MMU

Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 193 ++ 1 file changed, 174 insertions(+), 19 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 275b6c2a67..b3ce345f81 100644 --- a/target/riscv/cpu_helper.c ++

[PATCH v2 11/27] target/riscv: Convert mie and mstatus to pointers

To handle the new Hypervisor CSR register aliasing let's use pointers. We only need to convert the MIE and MSTATUS CSRs. With the exception of MIP all of the other CSRs that swap with virtulsation changes are S-Mode only, so we can just do a lazy switch. This because more challenging for the M-Mod

[PATCH v2 13/27] target/riscv: Add support for virtual interrupt setting

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 19 +-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 12a10e8679..bb4557df16 100644 --- a/target/riscv/cpu_help

[PATCH v2 07/27] target/riscv: Print priv and virt in disas log

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/translate.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index adeddb85f6..8ac72c6470 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate

[PATCH v2 23/27] target/riscv: Allow specifying MMU stage

Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 39 ++- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 79966ac6e6..275b6c2a67 100644 --- a/target/riscv/cpu_helper.c +++

[PATCH v2 21/27] target/riscv: Mark both sstatus and vsstatus as dirty

Mark both sstatus and vsstatus as dirty (3). Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/translate.c | 12 1 file changed, 12 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8ac72c6470..19771904f4 100644 --- a/t

[PATCH v2 03/27] target/riscv: Add the virtulisation mode

Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 4 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_helper.c | 18 ++ 3 files changed, 25 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 91e1c56fc4..469dcbd1c0 100644 --- a/target/

[PATCH v2 09/27] target/riscv: Add Hypervisor CSR access functions

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/csr.c | 68 ++ 1 file changed, 68 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 08956aa557..edfafca06f 100644 --- a/target/riscv/csr.c +++ b/target

[PATCH v2 02/27] target/riscv: Add the Hypervisor extension

Signed-off-by: Alistair Francis Reviewed-by: Chih-Min Chao Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f889427869..91e1c56fc4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -67,

[PATCH v2 10/27] target/riscv: Add Hypervisor virtual CSRs accesses

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 11 target/riscv/csr.c | 119 2 files changed, 130 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 162d42f211..95909f1

[PATCH v2 06/27] target/riscv: Add the Hypervisor CSRs to CPUState

As the MIP CSR is 32-bits to allow atomic_read on 32-bit hosts the vsip is 32-bit as well. Signed-off-by: Alistair Francis Reviewed-by: Chih-Min Chao Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h | 17 + 1 file changed, 17 insertions(+) diff --git a/target/riscv/cpu.h b/t

Re: [PATCH] buildfix: update texinfo menu

On 10/23/19 12:19, Gerd Hoffmann wrote: > Build error message: > qemu-doc.texi:34: node `Top' lacks menu item for `Recently removed features' > despite being its Up target > > Fixes: 3264ffced3d0 ("dirty-bitmaps: remove deprecated autoload parameter") > Signed-off-by: Gerd Hoffmann > --- > qemu

[PATCH 2/2] migration/multifd: not use multifd during postcopy

We don't support multifd during postcopy, but user still could enable both multifd and postcopy. This leads to migration failure. Skip multifd during postcopy. Signed-off-by: Wei Yang --- migration/ram.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/migration/ram.

Re: [PATCH] Semihost SYS_READC implementation (v4)

Peter Maydell writes: > I'm going to push for somebody actually writing out a > document and putting it somewhere that we can point to > and say "that's the authoritative spec", please... > it doesn't have to be a big formal thing, but I do > think you want it written down, because the whole poin

Re: [PATCH] ptimer: Remove old ptimer_init_with_bh() API

On 10/25/19 10:24 AM, Peter Maydell wrote: > Now all the users of ptimers have converted to the transaction-based > API, we can remove ptimer_init_with_bh() and all the code paths > that are used only by bottom-half based ptimers, and tidy up the > documentation comments to consider the transaction

Re: [PATCH] fw_cfg: Allow reboot-timeout=-1 again

On 10/25/19 18:57, Dr. David Alan Gilbert (git) wrote: > From: "Dr. David Alan Gilbert" > > Commit ee5d0f89de3e53cdb0dc added range checking on reboot-timeout > to only allow the range 0..65535; however both qemu and libvirt document > the special value -1 to mean don't reboot. > Allow it again.

Re: [PATCH v2 4/7] exec: Use const alias for TARGET_PAGE_BITS_VARY

On 10/25/19 5:01 PM, Peter Maydell wrote: > On Fri, 25 Oct 2019 at 21:43, Richard Henderson > wrote: >> >> On 10/25/19 10:51 AM, Peter Maydell wrote: + * We want to declare the "target_page" variable as const, which tells + * the compiler that it can cache any value that it reads across

Re: [PATCH] fw_cfg: Allow reboot-timeout=-1 again

"Dr. David Alan Gilbert (git)" writes: > From: "Dr. David Alan Gilbert" > > Commit ee5d0f89de3e53cdb0dc added range checking on reboot-timeout > to only allow the range 0..65535; however both qemu and libvirt document > the special value -1 to mean don't reboot. > Allow it again. > > Fixes: ee5

[Bug 1849894] Re: hw/scsi/scsi-disk.c line 2554 allocation overflow

FYI. Adding if (len <= 0) return; in the scsi_disk_new_request_dump solved the compilation issue for me. So indeed gcc thinks len == -1 I am pretty sure the build qemu is functional, as this path is only taken if the trace_event_get_state_backends(TRACE_SCSI_DISK_NEW_REQUEST) is true, which by de

Re: [PATCH v2 4/7] exec: Use const alias for TARGET_PAGE_BITS_VARY

On Fri, 25 Oct 2019 at 21:43, Richard Henderson wrote: > > On 10/25/19 10:51 AM, Peter Maydell wrote: > >> + * We want to declare the "target_page" variable as const, which tells > >> + * the compiler that it can cache any value that it reads across calls. > >> + * This avoids multiple assertions

Re: [PULL 00/20] MIPS queue for October 24th, 2019 - v2

On Fri, 25 Oct 2019 at 17:44, Aleksandar Markovic wrote: > > From: Aleksandar Markovic > > The following changes since commit 03bf012e523ecdf047ac56b2057950247256064d: > > Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging > (2019-10-25 14:59:53 +0100) > > are availabl

Re: [PULL 00/12] tcg patch queue

On 10/25/19 12:12 PM, Peter Maydell wrote: > Compile failure, win32: ... > /usr/lib/mxe/usr/x86_64-w64-mingw32.shared/include/glib-2.0/glib/gmacros.h:337:23: > error: expected expression befor > e 'do' > #define G_STMT_START do >^ > /usr/lib/mxe/usr/x86_64-w64-mingw32.shar

Re: [PATCH v2 0/4] tcg/LICENSE: Remove no-longer-true statement that TCG is BSD-licensed

On 10/25/19 11:58 AM, Peter Maydell wrote: > Since 2008 the tcg/LICENSE file has not changed: it claims that > everything under tcg/ is BSD-licensed. > > This is not true and hasn't been true for years: in 2013 we > accepted the tcg/aarch64 target code under a GPLv2-or-later > license statement. W

Re: [PATCH] Semihost SYS_READC implementation (v4)

On Fri, 25 Oct 2019 at 20:15, Keith Packard wrote: > > Peter Maydell writes: > > > Is there a specification for RISC-V semihosting? This is > > likely to be my first question when the support comes > > round for review, so you can have it early :-) We'd > > prefer to implement specified interfac

Re: [PATCH v2 0/4] tcg/LICENSE: Remove no-longer-true statement that TCG is BSD-licensed

On 25.10.19 17:58, Peter Maydell wrote: Since 2008 the tcg/LICENSE file has not changed: it claims that everything under tcg/ is BSD-licensed. This is not true and hasn't been true for years: in 2013 we accepted the tcg/aarch64 target code under a GPLv2-or-later license statement. We also have

Re: [PATCH v13 06/12] numa: Extend CLI to provide memory latency and bandwidth information

On Fri, Oct 25, 2019 at 09:44:50PM +0200, Markus Armbruster wrote: > Igor Mammedov writes: > > > On Fri, 25 Oct 2019 14:33:53 +0800 > > Tao Xu wrote: > > > >> On 10/23/2019 11:28 PM, Igor Mammedov wrote: > >> > On Sun, 20 Oct 2019 19:11:19 +0800 > >> > Tao Xu wrote: > >> [...] > >> >> +# > >>

[PULL 0/1] Require Python >= 3.5 to build QEMU

The following changes since commit 03bf012e523ecdf047ac56b2057950247256064d: Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2019-10-25 14:59:53 +0100) are available in the Git repository at: git://github.com/ehabkost/qemu.git tags/python-next-pull-request for

Re: [PATCH v2 4/7] exec: Use const alias for TARGET_PAGE_BITS_VARY

On 10/25/19 10:51 AM, Peter Maydell wrote: >> + * We want to declare the "target_page" variable as const, which tells >> + * the compiler that it can cache any value that it reads across calls. >> + * This avoids multiple assertions and multiple reads within any one user. >> + * >> + * This works b

Re: [PATCH v5] ssi: xilinx_spips: Skip spi bus update for a few register writes

On Thu, Oct 24, 2019 at 10:31 PM Sai Pavan Boddu wrote: > > A few configuration register writes need not update the spi bus state, so just > return after register write. > > Signed-off-by: Sai Pavan Boddu Reviewed-by: Alistair Francis Alistair > --- > > Changes for V2: > Just skip upd

Re: [Qemu-devel] [Qemu-riscv] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers

On Thu, Sep 19, 2019 at 9:59 AM Jonathan Behrens wrote: > > On Thu, Sep 19, 2019 at 10:50 AM Richard Henderson > wrote: > > > > On 9/18/19 4:47 PM, Alistair Francis wrote: > > > I'm not a fan of the pointer method that I'm using, but to me it seems > > > the least worst in terms of handling futur

[PULL 1/1] configure: Require Python >= 3.5

Python 3.5 is the oldest Python version available on our supported build platforms, and Python 2 end of life will be 3 weeks after the planned release date of QEMU 4.2.0. Drop Python 2 support from configure completely, and require Python 3.5 or newer. Signed-off-by: Eduardo Habkost Message-Id:

[Bug 1849894] [NEW] hw/scsi/scsi-disk.c line 2554 allocation overflow

Public bug reported: When compiling qemu from git master (at commit 03bf012e523ecdf047ac56b2057950247256064d ) on Linux amd64, with gcc-9 9.2.1 , and using `-march=native -flto`, during linking of most target binaries, compiler does detect an issue with allocation in scsi_disk_new_request_dump and

Re: [PULL v2 00/73] tcg plugins and testing updates

Alex Bennée writes: > Markus Armbruster writes: > >> I hate to interfere with the merging of working code for non-technical >> reasons >> >> This is a plugin interface. As I wrote in reply to v4, I'd like to see >> a pragmatic argument why abuse of the plugin interface to circumvent the >>

[PULL v3 13/15] travis.yml: --enable-debug-tcg to check-tcg

This adds a whole bunch of asserts which will catch bugs you might introduce into the TCG code. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé diff --git a/.travis.yml b/.travis.yml index c43597f1331..ba3a8d4cfc9 100644 --- a/.travis.yml +++ b/.travis.yml @@ -334,14 +334,14 @@ m

[PULL v3 06/15] travis.yml: Test the release tarball

From: Philippe Mathieu-Daudé Add a job to generate the release tarball and build/install few QEMU targets from it. Ideally we should build the 'efi' target from the 'roms' directory, but it is too time consuming. This job is only triggered when a tag starting with 'v' is pushed, which is the ca

[PULL 1/2] virtio-blk: Add blk_drain() to virtio_blk_device_unrealize()

From: Julia Suvorova QEMU does not wait for completed I/O requests, assuming that the guest driver will reset the device before calling unrealize(). This does not happen on Windows, and QEMU crashes in virtio_notify(), getting the result of a completed I/O request on hot-unplugged device. Signed

[PULL v3 12/15] gitlab-ci.yml: Use libvdeplug-dev to compile-test the VDE network backend

From: Thomas Huth The libvdeplug-dev package is required to compile-test net/vde.c. Signed-off-by: Thomas Huth Message-Id: <20191016131002.29663-1-th...@redhat.com> Signed-off-by: Alex Bennée diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index ed8067f5cf9..be57c6a454a 100644 --- a/.gitlab-ci.y

Re: [PATCH v2 02/15] qapi/block-core: add option for io_uring

Stefan Hajnoczi writes: > From: Aarushi Mehta > > Only enumerates option for devices that support it. I'm not sure I get this sentence. > Since QAPI schema > supports io_uring, which is the actual name of the Linux API, it is > preferred over

[PULL v3 15/15] tests/docker: update Travis image to a more current version

This isn't the latest one available on hub.docker.com but it does match the ID reported by the Xenial builds running on Travis: instance: ... travis-ci-sardonyx-xenial-1553530528-f909ac5 Signed-off-by: Alex Bennée diff --git a/tests/docker/dockerfiles/travis.docker b/tests/docker/dockerfiles

[PULL v3 14/15] tests/docker: set HOST_ARCH if we don't have ARCH

As the docker rules want to be able to be run on a virgin unconfigured checkout add a fallback and use it if we need to. Signed-off-by: Alex Bennée diff --git a/.shippable.yml b/.shippable.yml index bbc6f88510f..f74a3de3ffd 100644 --- a/.shippable.yml +++ b/.shippable.yml @@ -27,8 +27,6 @@ env:

[PULL v3 02/15] travis.yml: Add libvdeplug-dev to compile-test net/vde.c

From: Thomas Huth This library is needed to compile the VDE network backend. Signed-off-by: Thomas Huth Message-Id: <20191009170701.14756-2-th...@redhat.com> Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé diff --git a/.travis.yml b/.travis.yml index 7d90b87540f..7be2a9949f5 1

Re: [RFC v4 PATCH 48/49] multi-process: add the concept description to docs/devel/qemu-multiprocess

On Thu, Oct 24, 2019 at 05:09:29AM -0400, Jagannathan Raman wrote: > From: John G Johnson > > Signed-off-by: John G Johnson > Signed-off-by: Elena Ufimtseva > Signed-off-by: Jagannathan Raman > --- > v2 -> v3: >- Updated with latest design of this project > > v3 -> v4: > - Updated doc

[PULL v3 07/15] travis.yml: bump Xcode 10 to latest dot release

According to: https://docs.travis-ci.com/user/reference/osx/#macos-version we have 10.3 available so lets use it. I don't know what Apple's deprecation policy is for Xcode because it requires an AppleID to find out. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé diff --git a

[PULL v3 10/15] tests/vm/netbsd: Disable IPv6

From: Eduardo Habkost Workaround for issues when the host has no IPv6 connectivity. Signed-off-by: Eduardo Habkost Reviewed-by: Thomas Huth Message-Id: <20191018181705.17957-4-ehabk...@redhat.com> Signed-off-by: Alex Bennée diff --git a/tests/vm/netbsd b/tests/vm/netbsd index ee9eaeab504..18

Re: [PULL v2 00/73] tcg plugins and testing updates

Peter Maydell writes: > On Fri, 25 Oct 2019 at 07:37, Alex Bennée wrote: >> >> The following changes since commit 81c1f71eeb874c4cbbb9c5c4d1a1dc0ba7391dff: >> >> Merge remote-tracking branch >> 'remotes/ehabkost/tags/machine-next-pull-request' into staging (2019-10-24 >> 10:43:20 +0100) >>

[PULL v3 04/15] travis.yml: Use newer version of libgnutls and libpng

From: Thomas Huth libgnutls-dev and libpng12-dev are not available in newer versions of Ubuntu anymore, so installing these packages fails e.g. in the new arm64 containers on Travis. Let's use newer versions of these packages by default instead. (The old versions still get tested in the "gcc-9" b

[PULL v3 11/15] travis.yml: cache the clang sanitizer build

Hopefully we'll see the same benefits as the other builds. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé diff --git a/.travis.yml b/.travis.yml index da6a2063fca..c43597f1331 100644 --- a/.travis.yml +++ b/.travis.yml @@ -189,6 +189,7 @@ matrix: - env: - CONFIG=

[PULL v3 03/15] travis.yml: Use libsdl2 instead of libsdl1.2, and install libsdl2-image

From: Thomas Huth We've removed support for SDL 1.2 quite a while ago already, so let's use SDL 2 now in Travis to get test coverage for SDL again. And while we're at it, also add libsdl2-image-dev which can be used by QEMU nowadays, too. Signed-off-by: Thomas Huth Message-Id: <20191009170701.1

[PULL v3 01/15] travis.yml: reduce scope of the --enable-debug build

Adding debug makes things run a bit slower so lets not hammer all the targets. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé diff --git a/.travis.yml b/.travis.yml index d0b9e099b9c..7d90b87540f 100644 --- a/.travis.yml +++ b/.travis.yml @@ -124,12 +124,13 @@ matrix: -

[PULL v3 00/15] testing updates

The following changes since commit 03bf012e523ecdf047ac56b2057950247256064d: Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2019-10-25 14:59:53 +0100) are available in the Git repository at: https://github.com/stsquad/qemu.git tags/pull-testing-next-251019-3 f

[PULL v3 09/15] tests/vm: Let subclasses disable IPv6

From: Eduardo Habkost The mechanism will be used to work around issues related to IPv6 on the netbsd image builder. Signed-off-by: Eduardo Habkost Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20191018181705.17957-3-ehabk...@redhat.com> Signed-off-by: Alex Bennée

[PULL v3 08/15] cirrus.yml: add latest Xcode build target

CirrusCI provides a mojave-xcode alias for the latest Xcode available. Let's use it to make sure we track the latest releases. Signed-off-by: Alex Bennée diff --git a/.cirrus.yml b/.cirrus.yml index 8326a3a4b16..27efc48619b 100644 --- a/.cirrus.yml +++ b/.cirrus.yml @@ -25,3 +25,14 @@ macos_task

[PULL v3 05/15] travis.yml: Fix the ccache lines

From: Thomas Huth The "command -v ccache && ccache ..." likely were supposed to test the availability of ccache before running the program. But this shell construct causes Travis to abort if ccache is not available. Use an if-statement instead to fix this problem. Signed-off-by: Thomas Huth Rev

Re: [PATCH v13 06/12] numa: Extend CLI to provide memory latency and bandwidth information

Igor Mammedov writes: > On Fri, 25 Oct 2019 14:33:53 +0800 > Tao Xu wrote: > >> On 10/23/2019 11:28 PM, Igor Mammedov wrote: >> > On Sun, 20 Oct 2019 19:11:19 +0800 >> > Tao Xu wrote: >> [...] >> >> +# >> >> +# @access-bandwidth: access bandwidth (MB/s) >> >> +# >> >> +# @read-bandwidth: read

[PULL 2/2] yield_until_fd_readable: make it work with any AioContect

From: Dietmar Maurer Simply use qemu_get_current_aio_context(). Signed-off-by: Dietmar Maurer Message-Id: <20191024045610.9071-1-diet...@proxmox.com> Signed-off-by: Stefan Hajnoczi --- util/qemu-coroutine-io.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/util/qem

[PULL 0/2] Block patches

The following changes since commit 58560ad254fbda71d4daa6622d71683190070ee2: Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.2-20191024' into staging (2019-10-24 16:22:58 +0100) are available in the Git repository at: https://github.com/stefanha/qemu.git tags/block-pull-request

Re: [PATCH] Semihost SYS_READC implementation (v4)

Peter Maydell writes: > Is there a specification for RISC-V semihosting? This is > likely to be my first question when the support comes > round for review, so you can have it early :-) We'd > prefer to implement specified interfaces, not random > ad-hoc "this seems to be what newlib wants to se

Re: [PATCH 0/7] i386: Add `machine` parameter to query-cpu-definitions

Patchew URL: https://patchew.org/QEMU/20191025022553.25298-1-ehabk...@redhat.com/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PATCH 0/7] i386: Add `machine` parameter to query-cpu-definitions Type: series Message-id: 2019102502255

[PATCH] Semihost SYS_READC implementation (v5)

Provides a blocking call to read a character from the console using semihosting.chardev, if specified. This takes some careful command line options to use stdio successfully as the serial ports, monitor and semihost all want to use stdio. Here's a sample set of command line options which share stdi

Re: [PATCH] Semihost SYS_READC implementation (v4)

Patchew URL: https://patchew.org/QEMU/20191024224622.12371-1-kei...@keithp.com/ Hi, This series failed the docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #!

Re: [PATCH] Semihost SYS_READC implementation (v4)

Patchew URL: https://patchew.org/QEMU/20191024224622.12371-1-kei...@keithp.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #

[Bug 1849879] [NEW] qemu-arm should accept vmrs apsr_nzcv, fpscr on M-profile

Public bug reported: I've noticed that qemu-arm for cortex-M considers vmrs apsr_nzcv, fpscr as an illegal instruction. In this case, rt==15 means APSR, and the instruction should be accepted and executed like for A-profile. I posted a small patch: https://lists.gnu.org/archive/html/qemu-devel/2

Re: [PATCH v6 06/11] qapi: add failover negotiated event

On Fri, Oct 25, 2019 at 04:03:54PM +0200, Markus Armbruster wrote: Bear with me, I know next to nothing about failover. Jens Freimann writes: This event is sent to let libvirt know that VIRTIO_NET_F_STANDBY feature was enabled. The primary device this virtio-net device is associated with, wil

Re: [PATCH v6 01/11] qdev/qbus: add hidden device support

* Jens Freimann (jfreim...@redhat.com) wrote: > This adds support for hiding a device to the qbus and qdev APIs. The > first user of this will be the virtio-net failover feature but the API > introduced with this patch could be used to implement other features as > well, for example hiding pci dev

Re: [PATCH 00/11] tests/acceptance: Fix 64-bit MIPS target tests

On 10/25/19 6:46 PM, Aleksandar Markovic wrote: On Thu, Oct 24, 2019 at 11:23 AM Aleksandar Markovic wrote: ping for Cleber and Eduardo I applied patches 7, 8, 9, 10, and 11 to MIPS queue. Thanks Aleksandar!

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