On Thu, Sep 19, 2019 at 02:18:40PM +0200, Eric Auger wrote:
> This series allows the memory_region_register_iommu_notifier()
> to fail. As of now, when a MAP notifier is attempted to be
> registered along with SMMUv3, Intel iommu without caching mode
> or AMD IOMMU, we exit in the IOMMU MR notify_f
On 20/09/2019 05:34, Andrew Jeffery wrote:
>
>
> On Fri, 20 Sep 2019, at 06:26, no-re...@patchew.org wrote:
>> Patchew URL: https://patchew.org/QEMU/20190919055002.6729-1-...@kaod.org/
>>
>>
>>
>> Hi,
>>
>> This series failed the docker-quick@centos7 build test. Please find the
>> testing comman
On Fri, Sep 20, 2019 at 12:34 AM Cole Robinson wrote:
>
> Trailing comma is not valid json:
>
> $ cat contrib/vhost-user-gpu/50-qemu-gpu.json.in | jq
> parse error: Expected another key-value pair at line 5, column 1
>
> Signed-off-by: Cole Robinson
oh json..
Reviewed-by: Marc-André Lureau
> -
Philippe Mathieu-Daudé writes:
> Hi Alex,
>
> On 9/10/19 10:43 AM, Alex Bennée wrote:
>> This prevents us trying to do builds which we can't complete.
>>
>> Signed-off-by: Alex Bennée
>>
>> diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include
>> index 7df8dbe1a17..50a400b
On Wed, 18 Sep 2019, at 04:55, Richard Henderson wrote:
> On 9/17/19 12:14 PM, Peter Maydell wrote:
> >> +static Property arm_cpu_gt_cntfrq_property =
> >> +DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq,
> >> + (1000 * 1000 * 1000) / GTIMER_SCALE);
> >
On Wed, 18 Sep 2019, at 01:44, Peter Maydell wrote:
> On Thu, 12 Sep 2019 at 07:56, Andrew Jeffery wrote:
> > diff --git a/target/arm/helper.c b/target/arm/helper.c
> > index 507026c9154b..09975704d47f 100644
> > --- a/target/arm/helper.c
> > +++ b/target/arm/helper.c
> > @@ -2409,7 +2409,21 @@
Drop the duplicate definition of CPUID_7_0_ECX_VBMI. And add some
comments, clean up comments over 80 chars per line.
There is an extra line in comment of CPUID_8000_0008_EBX_WBNOINVD,
remove the extra enter and spaces.
Signed-off-by: Tao Xu
---
target/i386/cpu.h | 163 +++
On Fri, Sep 20, 2019 at 6:32 AM Alistair Francis
wrote:
>
> On reset only a single L2 cache way is enabled, the others are exposed
> as memory that can be used by early boot firmware. This L2 region is
> generally disabled using the WayEnable register at a later stage in the
> boot process. To all
On Fri, Sep 20, 2019 at 6:32 AM Alistair Francis
wrote:
>
> Add a property that when set to true QEMU will jump from the ROM code to
> the start of flash memory instead of DRAM which is the default
> behaviour.
>
> Signed-off-by: Alistair Francis
> ---
> hw/riscv/sifive_u.c | 27
On Thu, 19 Sep 2019 at 05:52, Cédric Le Goater wrote:
>
> Signed-off-by: Cédric Le Goater
> ---
> hw/arm/aspeed.c | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 52993f84b461..4450e71e5547 100644
> --- a/hw/arm/aspeed.c
> +++
On Fri, Sep 20, 2019 at 6:34 AM Alistair Francis
wrote:
>
> Instead of using the DEFINE_MACHINE() macro to define the machine let's
> do it manually. This allows us to specify machine properties.
>
> This patch is no functional change.
>
> Signed-off-by: Alistair Francis
> ---
> hw/riscv/sifive_
On Fri, Sep 20, 2019 at 6:32 AM Alistair Francis
wrote:
>
> There doesn't seem to be details on what QSPI the HiFive Unleashed uses.
IMHO, this sentence should be removed as there are details available.
See the hifive-unleashed-a00.dts.
&qspi0 {
status = "okay";
flash@0 {
On Fri, Sep 20, 2019 at 6:36 AM Alistair Francis
wrote:
>
> Add the CFI01 PFlash to the RISC-V virt board. This is the same PFlash
> from the ARM Virt board and the implementation is based on the ARM Virt
> board. This allows users to specify flash files from the command line.
>
> Signed-off-by: A
On Thu, 19 Sep 2019 at 05:51, Cédric Le Goater wrote:
>
> It cleanups the current models for the Aspeed AST2400 and AST2500 SoCs
> and prepares ground for future SoCs. It removes the need of the
> 'silicon_rev' property.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
On Fri, Sep 20, 2019 at 6:35 AM Alistair Francis
wrote:
>
> If the user supplied pflash to QEMU then change the reset code to jump
> to the pflash base address instead of the DRAM base address.
>
> Signed-off-by: Alistair Francis
> ---
> hw/riscv/virt.c | 10 +-
> 1 file changed, 9 inser
On Thu, 19 Sep 2019 at 05:50, Cédric Le Goater wrote:
>
> From: Amithash Prasad
>
> When WDT_RESTART is written, the data is not the contents
> of the WDT_CTRL register. Hence ensure we are looking at
> WDT_CTRL to check if bit WDT_CTRL_1MHZ_CLK is set or not.
>
> Signed-off-by: Amithash Prasad
On Thu, 19 Sep 2019 at 05:51, Cédric Le Goater wrote:
>
> The AST2600 SoC SMC controller is a SPI only controller now and has a
> few extensions which we will need to take into account when SW
> requires it.
>
> - 4BYTE mode
> - HCLK divider has changed (SPI Training)
> - CE0-2 Read Timing Comp
On Thu, 19 Sep 2019 at 05:50, Cédric Le Goater wrote:
>
> The AST2600 timer has a third control register that is used to
> implement a set-to-clear feature for the main control register.
>
> On the AST2600, it is not configurable via 0x38 (control register 3)
> as it is on the AST2500.
>
> Based o
On Thu, 19 Sep 2019 at 05:51, Cédric Le Goater wrote:
>
> The I2C controller of the AST2400 and AST2500 SoCs have one IRQ shared
> by all I2C busses. The AST2600 SoC I2C controller has one IRQ per bus
> and 16 busses.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
On Thu, 19 Sep 2019 at 05:51, Cédric Le Goater wrote:
>
> The AST2600 timer replaces control register 2 with a interrupt status
> register. It is set by hardware when an IRQ occurs and cleared by
> software.
>
> Modify the vmstate version to take into account the new fields.
>
> Based on previous
On Thu, 19 Sep 2019 at 05:52, Cédric Le Goater wrote:
>
> The AST2600 SoC has an extra controller to set the PHY registers.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
On Thu, 19 Sep 2019 at 05:51, Cédric Le Goater wrote:
>
> It prepares ground for register differences between SoCs.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
On Thu, 19 Sep 2019 at 05:52, Cédric Le Goater wrote:
>
> It prepares ground for the AST2600.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
On Thu, 19 Sep 2019 at 05:51, Cédric Le Goater wrote:
>
> Use class handlers and class constants to differentiate the
> characteristics of the memory controller and remove the 'silicon_rev'
> property.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
On Thu, 19 Sep 2019 at 05:52, Cédric Le Goater wrote:
>
> Initial definitions for a simple machine using an AST2600 SoC (Cortex
> CPU).
>
> The Cortex CPU and its interrupt controller are too complex to handle
> in the common Aspeed SoC framework. We introduce a new Aspeed SoC
> class with instanc
On Thu, 19 Sep 2019, at 15:19, Cédric Le Goater wrote:
> From: Joel Stanley
>
> The SCU controller on the AST2600 SoC has extra registers. Increase
> the number of regs of the model and introduce a new field in the class
> to customize the MemoryRegion operations depending on the SoC model.
>
On Fri, 20 Sep 2019, at 06:26, no-re...@patchew.org wrote:
> Patchew URL: https://patchew.org/QEMU/20190919055002.6729-1-...@kaod.org/
>
>
>
> Hi,
>
> This series failed the docker-quick@centos7 build test. Please find the
> testing commands and
> their output below. If you have Docker inst
Yes, I first replicated the issue by removing "max_outputs=1", then
patched spice server, and the issue no longer happens.
QEMU 4.1.0 still changed something. If I understand correctly, it's now
in some circumstances saying there are 0 monitors, even though there's a
graphic card?
Fixing this in
Thanks xiang's continue upstream and test.
Hope maintainer can review it.
On 2019/9/17 20:39, Xiang Zheng wrote:
> Hi all,
>
> This patch series has been tested for both TCG and KVM scenes.
>
> 1) Test for TCG:
>- Re-compile qemu after applying the patch refered to
> https://patchwork.kern
Hi Peter, thanks for your review!
On 2019/9/19 21:25, Peter Maydell wrote:
> On Fri, 6 Sep 2019 at 09:33, Xiang Zheng wrote:
>>
>> From: Dongjiu Geng
>>
>> Add APEI/GHES detailed design document
>>
>> Signed-off-by: Dongjiu Geng
>> Signed-off-by: Xiang Zheng
>> ---
>> docs/specs/acpi_hest_ghe
On 2019/9/19 下午10:06, Michael S. Tsirkin wrote:
On Thu, Sep 19, 2019 at 05:37:48PM +0800, Jason Wang wrote:
On 2019/9/19 下午3:16, Tian, Kevin wrote:
+Paolo to help clarify here.
From: Jason Wang [mailto:jasow...@redhat.com]
Sent: Thursday, September 19, 2019 2:32 PM
On 2019/9/19 下午2:17, Ya
On 9/19/19 2:50 AM, Vladimir Sementsov-Ogievskiy wrote:
> 18.09.2019 22:57, John Snow wrote:
>>
>>
>> On 9/17/19 12:07 PM, Vladimir Sementsov-Ogievskiy wrote:
>>> Of course, QEMU_ALIGN_UP is a typo, it should be QEMU_ALIGN_DOWN, as we
>>> are trying to find aligned size which satisfy both source
On 2019/9/20 上午6:54, Tian, Kevin wrote:
From: Paolo Bonzini [mailto:pbonz...@redhat.com]
Sent: Thursday, September 19, 2019 7:14 PM
On 19/09/19 09:16, Tian, Kevin wrote:
why GPA1 and GPA2 should be both dirty?
even they have the same HVA due to overlaping virtual address space
in
two proces
On 9/19/19 3:02 AM, Vladimir Sementsov-Ogievskiy wrote:
> 18.09.2019 23:14, John Snow wrote:
>>
>>
>> On 9/17/19 12:07 PM, Vladimir Sementsov-Ogievskiy wrote:
>>> We shouldn't try to copy bytes beyond EOF. Fix it.
>>>
>>> Fixes: 9ded4a0114968e
>>> Signed-off-by: Vladimir Sementsov-Ogievskiy
>>>
On 9/19/2019 5:41 PM, Philippe Mathieu-Daudé wrote:
Hi Tao,
On 9/19/19 4:06 AM, Tao Xu wrote:
There is an extra line in comment of CPUID_8000_0008_EBX_WBNOINVD,
remove the extra enter and spaces.
Signed-off-by: Tao Xu
---
target/i386/cpu.h | 3 +--
1 file changed, 1 insertion(+), 2 deletio
On 9/19/19 3:36 PM, Oleinik, Alexander wrote:
> On Thu, 2019-09-19 at 14:56 -0400, John Snow wrote:
>> >
>> > On 9/19/19 6:37 AM, Stefan Hajnoczi wrote:
>>> > > On Wed, Sep 18, 2019 at 11:19:40PM +, Oleinik, Alexander wrote:
> > > When using qtest "in-process" communication, qtest_sendf
Patchew URL: https://patchew.org/QEMU/20190918231846.22538-1-alx...@bu.edu/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#! /bi
Patchew URL: https://patchew.org/QEMU/20190918231846.22538-1-alx...@bu.edu/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bi
Patchew URL: https://patchew.org/QEMU/20190918231846.22538-1-alx...@bu.edu/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190918231846.22538-1-alx...@bu.edu
Subject: [Qemu-devel] [PATCH v3 00/22] Add virtual device fuzzing suppor
Patchew URL: https://patchew.org/QEMU/20190918231846.22538-1-alx...@bu.edu/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
export ARC
This is a demo for using makefile dependencies for image requisites.
Honestly, I don't like it -- Makefile sorcery is a bit beyond my
comprehension.
This is as near as I could stab, and it has the unfortunate requisite
that it will generate all of the *.d files at first run and not in an
on-demand
These are listed as "partial" images, but have no user.
Remove them.
Signed-off-by: John Snow
---
tests/docker/Makefile.include| 4 +--
tests/docker/dockerfiles/debian-ports.docker | 36
tests/docker/dockerfiles/debian-sid.docker | 35 ---
There isn't a debian.dockerfile anymore,
so perform some ghost-busting.
Signed-off-by: John Snow
---
tests/docker/Makefile.include | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include
index 50a400b573..8825821127
We don't have a debian8-mxe dockerfile anymore.
Signed-off-by: John Snow
---
tests/docker/Makefile.include | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include
index 8825821127..7af476d957 100644
--- a/tests/docker/Make
Another handful of misc tidyups.
Note: this WILL conflict with the other cleanups already in-flight, but
I didn't have a convenient branch to base against at the time; but
it should be pretty trivial to resolve/respin.
John Snow (3):
docker: remove 'deprecated' image definitions
docker: remov
This reduces the size of a release build by about 10k.
Noticably, within the tlb miss helpers.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index a53b761b48..b1
There are some uint64_t uses that expect TARGET_PAGE_MASK to
extend for a 32-bit, so this must continue to be a signed type.
Define based on TARGET_PAGE_BITS not TARGET_PAGE_SIZE; this
will make a following patch more clear.
This should not have a functional effect so far.
Signed-off-by: Richard
Using a variable that is declared "const" for this tells the
compiler that it may read the value once and assume that it
does not change across function calls.
For target_page_size, this means we have only one assert per
function, and one read of the variable.
This reduces the size of qemu-system
This eliminates a set of runtime shifts. It turns out that we
require TARGET_PAGE_MASK more often than TARGET_PAGE_SIZE, so
redefine TARGET_PAGE_SIZE based on TARGET_PAGE_MASK instead of
the other way around.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 8 ++--
exec-vary.c
There's currently a fair amount of overhead in the way we currently
treat TARGET_PAGE_{BITS,SIZE,MASK} with TARGET_PAGE_BITS_VARY.
We have assertions that TARGET_PAGE_BITS has been finalized. Which
is fine, but the variable that controls the assertion may be assumed
to be modified by any function
The next patch will play a trick with "const" that will
confuse the compiler about the uses of target_page_bits
within exec.c. Moving everything to a new file prevents
this confusion.
No functional change so far.
Signed-off-by: Richard Henderson
---
Makefile.target | 2 +-
include/qemu-
These bits do not need to vary with the actual page size
used by the guest.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index d2d443c4f9..e0c8dc54
Use TARGET_PAGE_MASK twice instead of TARGET_PAGE_SIZE once.
This is functionally identical, but will help a following patch.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cp
This replaces paramiko with avocado.utils.ssh module, which is based
on a (open)ssh binary, supposedly more ubiquitous.
Signed-off-by: Cleber Rosa
---
tests/acceptance/linux_ssh_mips_malta.py | 74
tests/requirements.txt | 3 +-
2 files changed, 25 ins
> From: Paolo Bonzini [mailto:pbonz...@redhat.com]
> Sent: Thursday, September 19, 2019 7:14 PM
>
> On 19/09/19 09:16, Tian, Kevin wrote:
> >>> why GPA1 and GPA2 should be both dirty?
> >>> even they have the same HVA due to overlaping virtual address space
> in
> >>> two processes, they still cor
> From: Alex Williamson [mailto:alex.william...@redhat.com]
> Sent: Friday, September 20, 2019 1:21 AM
>
> On Wed, 18 Sep 2019 07:21:05 +
> "Tian, Kevin" wrote:
>
> > > From: Jason Wang [mailto:jasow...@redhat.com]
> > > Sent: Wednesday, September 18, 2019 2:04 PM
> > >
> > > On 2019/9/18 上午
Add the CFI01 PFlash to the RISC-V virt board. This is the same PFlash
from the ARM Virt board and the implementation is based on the ARM Virt
board. This allows users to specify flash files from the command line.
Signed-off-by: Alistair Francis
---
hw/riscv/Kconfig| 1 +
hw/riscv/virt.
If the user supplied pflash to QEMU then change the reset code to jump
to the pflash base address instead of the DRAM base address.
Signed-off-by: Alistair Francis
---
hw/riscv/virt.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
Instead of using the DEFINE_MACHINE() macro to define the machine let's
do it manually. This allows us to specify machine properties.
This patch is no functional change.
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_u.c | 27 +++
include/hw/riscv/sifive_u.h
On reset only a single L2 cache way is enabled, the others are exposed
as memory that can be used by early boot firmware. This L2 region is
generally disabled using the WayEnable register at a later stage in the
boot process. To allow firmware to target QEMU and the HiFive Unleashed
let's add the L
Add a property that when set to true QEMU will jump from the ROM code to
the start of flash memory instead of DRAM which is the default
behaviour.
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_u.c | 27 +++
include/hw/riscv/sifive_u.h | 2 ++
2 files change
There doesn't seem to be details on what QSPI the HiFive Unleashed uses.
To allow boot firmware developers to use QEMU to target the Unleashed
let's add a chunk of memory to represent the QSPI. This can be targeted
using QEMU's -device loader command line option.
Signed-off-by: Alistair Francis
-
This series aims to improve the use of QEMU for developing boot code. It
does a few things:
- sifive_u machine:
- Adds a chunk of memory in the Flash area. This allows boot loaders
to use this memory. I can't find details on the QSPI flash used on
the real board, so this is the best bet
On 9/19/19 10:10 AM, Alex Bennée wrote:
> The slirp sub-module complains about not being able to find the glib
> library on cross-compiles because it is using the default pkg-config
> tool (which isn't installed in our cross-build docker images).
> Preserve PKG_CONFIG in our host config and pass it
On 9/19/19 10:10 AM, Alex Bennée wrote:
> This is a generic floating point multiply and accumulate test for
> single precision floating point values. I've split of the common float
> functions into a helper library so additional tests can use the same
> common code.
>
> As I don't have references
On Thu, Sep 19, 2019 at 09:26:35PM +0200, Thomas Huth wrote:
> Am Thu, 19 Sep 2019 18:19:40 +0200
> schrieb Philippe Mathieu-Daudé :
>
> > Cc'ing Thomas
> >
> > On 9/19/19 6:14 PM, Cleber Rosa wrote:
> > > Instead of looking for a specific error, let's relax the pattern
> > > because different er
On 9/19/19 3:43 PM, John Snow wrote:
>
>
> On 9/19/19 3:48 PM, Tony Asleson wrote:
>> Initial attempt at returning a media error for ahci. This is certainly
>> wrong and needs serious improvement.
>>
>
> Hi; I have the unfortunate distinction of being the AHCI maintainer.
> Please CC me on futu
On 9/19/19 10:10 AM, Alex Bennée wrote:
> This is broadly similar to the existing fcvt test for ARM but using
> the generic float testing framework. We should be able to pare down
> the ARM fcvt test case to purely half-precision with or without the
> Alt HP provision.
>
> Signed-off-by: Alex Benn
Patchew URL: https://patchew.org/QEMU/20190919055002.6729-1-...@kaod.org/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/
Patchew URL: https://patchew.org/QEMU/20190919070918.16059-1-kra...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190919070918.16059-1-kra...@redhat.com
Subject: [Qemu-devel] [PULL 0/4] Ui 20190919 patches
Type
From: Corey Minyard
Signed-off-by: Corey Minyard
---
default-configs/i386-softmmu.mak | 1 +
hw/i386/Kconfig | 1 +
hw/ipmi/Kconfig | 5 +
hw/ipmi/Makefile.objs| 1 +
hw/ipmi/smbus_ipmi.c | 384 +++
5
On 09/19/19 21:56, Philippe Mathieu-Daudé wrote:
> On 9/19/19 9:08 PM, Laszlo Ersek wrote:
>> On 09/19/19 18:39, Philippe Mathieu-Daudé wrote:
>>> On 9/18/19 7:11 PM, Laszlo Ersek wrote:
It turns out that forcing python2 for running the edk2 "build" utility is
neither necessary nor suffic
From: Corey Minyard
This is so I2C devices can be found in the ACPI namespace. Currently
that's only IPMI, but devices can be easily added now.
Adding the devices required some PCI information, and the bus itself
to be added to the PCMachineState structure.
Note that this only works on Q35, th
From: Corey Minyard
Get ready for PCI and other BT interfaces.
No functional changes, just split the code into generic BT code
and ISA-specific BT code.
Signed-off-by: Corey Minyard
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ipmi/Makefile.objs | 2 +-
hw/ipmi/ipmi_bt.c | 426 ++
From: Corey Minyard
Pretty straightforward, just hook the current KCS and BT code into
the PCI system with the proper configuration.
Cc: Michael S. Tsirkin
Cc: M: Marcel Apfelbaum
Signed-off-by: Corey Minyard
---
default-configs/i386-softmmu.mak | 2 +
hw/i386/Kconfig |
On 9/19/19 10:10 AM, Alex Bennée wrote:
> diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
> index 6c4a471aeae..e8a1a1495fc 100755
> --- a/tests/tcg/configure.sh
> +++ b/tests/tcg/configure.sh
> @@ -54,6 +54,7 @@ fi
> : ${cross_cc_cflags_ppc="-m32"}
> : ${cross_cc_ppc64="powerpc-linux
The bit shifting trick worked because the number of bytes per frame was
always a power-of-two (since QEMU only supports mono, stereo and 8, 16
and 32 bit samples). But if we want to add support for surround sound,
this no longer holds true.
Signed-off-by: Kővágó, Zoltán
---
audio/alsaaudio.c
From: Corey Minyard
This is for IPMI, which will behave differently if the UUID is
not set.
Signed-off-by: Corey Minyard
Cc: Fam Zheng
Cc: Michael S. Tsirkin
Cc: Marc-André Lureau
---
include/hw/qdev-properties.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/hw/qdev-pro
From: Corey Minyard
This will be required for getting IPMI SSIF (SMBus interface) into
the ACPI tables.
Cc: Michael S. Tsirkin
Cc: Igor Mammedov
Signed-off-by: Corey Minyard
---
hw/acpi/aml-build.c | 40 +
include/hw/acpi/aml-build.h | 18 +
This way we no longer need vararg functions, improving compile time
error detection. Also now it's possible to check actually what commands
are supported, without needing to manually update ctl_caps.
Signed-off-by: Kővágó, Zoltán
---
audio/alsaaudio.c | 62 --
audio/audio.
From: Corey Minyard
Add the watchdog pretimeout to the bits that cause an interrupt on attn.
Otherwise the user won't know.
Signed-off-by: Corey Minyard
---
hw/ipmi/ipmi_bmc_sim.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_s
From: Corey Minyard
Pass in the CRS so that it can be set to the SMBus for IPMI later.
Cc: Michael S. Tsirkin
Cc: Igor Mammedov
Signed-off-by: Corey Minyard
---
hw/acpi/ipmi-stub.c| 2 +-
hw/acpi/ipmi.c | 13 +++--
hw/i386/acpi-build.c | 2 +-
include/hw/acpi/ipmi.h |
From: Corey Minyard
Get ready for PCI and other KCS interfaces.
No functional changes, just split the code into the generic KCS code
and the ISA-specific code.
Signed-off-by: Corey Minyard
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ipmi/Makefile.objs | 2 +-
hw/ipmi/ipmi_kcs.c
Add an option to change the channel map used by pulseaudio. If not
specified, falls back to an OSS compatible channel map.
Signed-off-by: Kővágó, Zoltán
---
audio/paaudio.c | 18 ++
qapi/audio.json | 7 +--
qemu-options.hx | 9 +
3 files changed, 28 insertions(+),
From: Corey Minyard
PCI device I/O must be >= 8 bytes in length or they don't work.
Allow the size to be passed in, the default size of 2 or 3
won't work.
Signed-off-by: Corey Minyard
---
hw/ipmi/ipmi_bt.c | 19 +++
hw/ipmi/ipmi_kcs.c | 23 +++--
From: Corey Minyard
Not all devices have fwinfo (like the coming PCI one), so ignore
them if the their fwinfo function is NULL.
Cc: Michael S. Tsirkin
Cc: Igor Mammedov
Signed-off-by: Corey Minyard
---
hw/smbios/smbios_type_38.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/smbio
hanging on to these changes far too long.
The following changes since commit a77d20bafcd4cb7684168a9b4c6dc2a321aaeb50:
Merge remote-tracking branch 'remotes/kraxel/tags/ui-20190919-pull-request'
into staging (2019-09-19 17:16:07 +0100)
are available in the Git repository at:
https:
Usage notes: hw->samples became hw->{mix,conv}_buf->size, except before
initialization (audio_pcm_hw_alloc_resources_*), hw->samples gives the
initial size of the STSampleBuffer. The next commit tries to fix this
inconsistency.
Signed-off-by: Kővágó, Zoltán
---
audio/audio.c | 122
From: Corey Minyard
Using the UUID that qemu generates probably isn't the best thing
to do, allow it to be passed in via properties, and use QemuUUID
for the type.
If the UUID is not set, return an unsupported command error. This
way we are not providing an all-zero (or randomly generated) GUID
From: Corey Minyard
The wrong logic was used for detection (so it wouldn't work at all)
and the wrong interface was used to inject the NMI if the detection
logic was correct.
Signed-off-by: Corey Minyard
---
hw/ipmi/ipmi.c | 6 +++---
hw/ipmi/ipmi_bmc_sim.c | 2 +-
2 files changed, 4 i
Implementation of the previously added mixing-engine option.
Signed-off-by: Kővágó, Zoltán
---
audio/audio.c | 70 ++
audio/audio_template.h | 20
2 files changed, 78 insertions(+), 12 deletions(-)
diff --git a/audio/audio.c b/audio/
From: Corey Minyard
It wasn't returning the set timeout like it should have been.
Signed-off-by: Corey Minyard
---
hw/ipmi/ipmi_bmc_sim.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c
index 8f63bb7181..afb99e33d7 100644
--- a/hw/ipmi/ipmi
From: Corey Minyard
The IPMI BT tests had a race condition, if it receive an IPMI command
to enable interrupt, it would write the message to enable interrupts
after it wrote the command response. So the test code could
receive the command response and issue the next command before the
device han
This assumption is no longer true when mixeng is turned off.
Signed-off-by: Kővágó, Zoltán
---
hw/usb/dev-audio.c | 28 +---
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/hw/usb/dev-audio.c b/hw/usb/dev-audio.c
index ae42e5a2f1..74c99b1f12 100644
--- a/h
This commit removes the ad-hoc rate-limiting code from noaudio and
wavaudio, and replaces them with a (slightly modified) code from
spiceaudio. This way multiple write calls (for example when the
circular buffer wraps around) do not cause problems.
Signed-off-by: Kővágó, Zoltán
---
audio/audio.
Signed-off-by: Kővágó, Zoltán
---
audio/sdlaudio.c | 87 +++-
1 file changed, 42 insertions(+), 45 deletions(-)
diff --git a/audio/sdlaudio.c b/audio/sdlaudio.c
index 14b11f0335..f7ac8cd101 100644
--- a/audio/sdlaudio.c
+++ b/audio/sdlaudio.c
@@ -41,8
With stereo playback, they need about 375 minutes of continuous audio
playback to overflow, which is usually not a problem (as stopping and
later resuming playback resets the counters). But with 7.1 audio, they
only need about 95 minutes to overflow.
After the overflow, the buf->prod % USBAUDIO_P
+0100)
are available in the Git repository at:
git://git.kraxel.org/qemu tags/audio-20190919-pull-request
for you to fetch changes up to cf0c1c2aa32db5d658c3c797ad995a6d571bad96:
audio: fix ALSA period-length typo in documentation (2019-09-19 10:32:48
+0200
This will allow us to disable mixeng when we use a decent backend.
Disabling mixeng have a few advantages:
* we no longer convert the audio output from one format to another, when
the underlying audio system would just convert it to a third format.
We no longer convert, only the underlying sys
Signed-off-by: Kővágó, Zoltán
---
Notes:
Changes from v3:
* fix compilation on 32-bit targets
audio/wavaudio.c | 54
1 file changed, 9 insertions(+), 45 deletions(-)
diff --git a/audio/wavaudio.c b/audio/wavaudio.c
index b6eeeb4e26.
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