On Fri, Sep 20, 2019 at 6:32 AM Alistair Francis <alistair.fran...@wdc.com> wrote: > > On reset only a single L2 cache way is enabled, the others are exposed > as memory that can be used by early boot firmware. This L2 region is > generally disabled using the WayEnable register at a later stage in the > boot process. To allow firmware to target QEMU and the HiFive Unleashed > let's add the L2 LIM (LooselyIntegrated Memory). > > Ideally we would want to adjust the size of this chunk of memory as the > L2 Cache Controller WayEnable register is incremented. Unfortunately I > don't see a nice way to handle reducing or blocking out the L2 LIM while > still allowing it be re returned to all enabled from a reset. > > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > --- > hw/riscv/sifive_u.c | 15 +++++++++++++++ > include/hw/riscv/sifive_u.h | 1 + > 2 files changed, 16 insertions(+) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 9f8e84bf2e..de6e197882 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -65,6 +65,7 @@ static const struct MemmapEntry { > [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, > [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, > [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, > + [SIFIVE_U_L2LIM] = { 0x8000000, 0x1e00000 },
The size should be 0x2000000. > [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, > [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, > [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, > @@ -431,6 +432,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, > Error **errp) > const struct MemmapEntry *memmap = sifive_u_memmap; > MemoryRegion *system_memory = get_system_memory(); > MemoryRegion *mask_rom = g_new(MemoryRegion, 1); > + MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); > qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES]; > char *plic_hart_config; > size_t plic_hart_config_len; > @@ -459,6 +461,19 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, > Error **errp) > memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, > mask_rom); > > + /* Add L2-LIM at reset size. nits: wrong multi-line comment format > + * This should be reduced in size as the L2 Cache Controller WayEnable > + * register is incremented. Unfortunately I don't see a nice (or any) way > + * to handle reducing or blocking out the L2 LIM while still allowing it > + * be re returned to all enabled after a reset. For the time being, just > + * leave it enabled all the time. This won't break anything, but will be > + * too generous to misbehaving guests. > + */ > + memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", > + memmap[SIFIVE_U_L2LIM].size, &error_fatal); > + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base, > + l2lim_mem); > + > /* create PLIC hart topology configuration string */ > plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * > ms->smp.cpus; > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > index e4df298c23..50e3620c02 100644 > --- a/include/hw/riscv/sifive_u.h > +++ b/include/hw/riscv/sifive_u.h > @@ -58,6 +58,7 @@ enum { > SIFIVE_U_DEBUG, > SIFIVE_U_MROM, > SIFIVE_U_CLINT, > + SIFIVE_U_L2LIM, > SIFIVE_U_PLIC, > SIFIVE_U_PRCI, > SIFIVE_U_UART0, > -- Regards, Bin