On Fri, Sep 20, 2019 at 6:34 AM Alistair Francis
<alistair.fran...@wdc.com> wrote:
>
> Instead of using the DEFINE_MACHINE() macro to define the machine let's
> do it manually. This allows us to specify machine properties.
>
> This patch is no functional change.
>
> Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
> ---
> hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++----
> include/hw/riscv/sifive_u.h | 7 ++++++-
> 2 files changed, 29 insertions(+), 5 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 9c5d791320..c3949fb316 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -310,8 +310,7 @@ static void create_fdt(SiFiveUState *s, const struct
> MemmapEntry *memmap,
> static void riscv_sifive_u_init(MachineState *machine)
> {
> const struct MemmapEntry *memmap = sifive_u_memmap;
> -
> - SiFiveUState *s = g_new0(SiFiveUState, 1);
> + SiFiveUState *s = RISCV_U_MACHINE(machine);
> MemoryRegion *system_memory = get_system_memory();
> MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> MemoryRegion *flash0 = g_new(MemoryRegion, 1);
> @@ -545,8 +544,15 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
> Error **errp)
> memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
> }
>
> -static void riscv_sifive_u_machine_init(MachineClass *mc)
> +static void riscv_sifive_u_machine_instance_init(Object *obj)
> +{
> +
nits: remove this blank line
> +}
> +
> +static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data)
> {
> + MachineClass *mc = MACHINE_CLASS(oc);
> +
> mc->desc = "RISC-V Board compatible with SiFive U SDK";
> mc->init = riscv_sifive_u_init;
> mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT +
> SIFIVE_U_COMPUTE_CPU_COUNT;
> @@ -554,7 +560,20 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
> mc->default_cpus = mc->min_cpus;
> }
>
> -DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
> +static const TypeInfo riscv_sifive_u_machine_init_typeinfo = {
nits: riscv_sifive_u_machine_typeinfo (no _init for consistency with others)
> + .name = MACHINE_TYPE_NAME("sifive_u"),
> + .parent = TYPE_MACHINE,
> + .class_init = riscv_sifive_u_machine_class_init,
> + .instance_init = riscv_sifive_u_machine_instance_init,
> + .instance_size = sizeof(SiFiveUState),
> +};
> +
> +static void riscv_sifive_u_machine_init_register_types(void)
> +{
> + type_register_static(&riscv_sifive_u_machine_init_typeinfo);
> +}
> +
> +type_init(riscv_sifive_u_machine_init_register_types)
nits: I would move the machine declaration to after the sifive_u SoC
declaration in this file.
>
> static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
> {
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index 2a08e2a5db..a921079fbe 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -44,12 +44,17 @@ typedef struct SiFiveUSoCState {
> CadenceGEMState gem;
> } SiFiveUSoCState;
>
> +#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")
> +#define RISCV_U_MACHINE(obj) \
> + OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE)
> +
> typedef struct SiFiveUState {
> /*< private >*/
> - SysBusDevice parent_obj;
> + MachineState parent_obj;
>
> /*< public >*/
> SiFiveUSoCState soc;
> +
> void *fdt;
> int fdt_size;
> } SiFiveUState;
> --
Regards,
Bin
