On 08/18/2015 01:42 AM, Alexander Bezzubikov wrote:
> Signed-off-by: Alexander Bezzubikov
> ---
> hw/ide/Makefile.objs | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/ide/Makefile.objs b/hw/ide/Makefile.objs
> index 729e9bd..f54f275 100644
> --- a/hw/ide/Makefile.objs
On 08/18/2015 01:42 AM, Alexander Bezzubikov wrote:
> Signed-off-by: Alexander Bezzubikov
> ---
> hw/scsi/scsi-disk.c| 12
> include/hw/scsi/scsi.h | 13 +
> 2 files changed, 13 insertions(+), 12 deletions(-)
>
> diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c
On 08/15/2015 11:21 PM, Peter Crosthwaite wrote:
> I'm trying to debug why TCI doesn't work for the Microblaze example at
> http://wiki.qemu.org/Testing. My debug led me to the return addresses
> for exceptions being too far forward and this adjustment looked
> related so I gave this change a shot,
Changes v1 -> v2:
* Fix build error on patch 1/4
This implements some extras code cleanups in the PC code:
* Move some local variables from pc_init1() and pc_q35_init() to
PCMachineState, so initialization functions can get that info from a
PCMachineState* argument directly
* Move some compat
This includes linux/arch/powerpc/include/uapi/asm/eeh.h while
updating linux header files. The specific header file, introduced
by Linux upstream commit ed3e81f ("powerpc/eeh: Move PE state
constants around"), is used by EEH on sPAPR platform.
Signed-off-by: Gavin Shan
---
scripts/update-linux-h
The patch supports RTAS call "ibm,errinjct" to allow injecting
EEH errors to VFIO PCI devices. The implementation is similiar
to EEH support for VFIO PCI devices: The RTAS request is captured
by QEMU and routed to sPAPRPHBClass::eeh_inject_error() where the
request is translated to VFIO container I
Signed-off-by: Alexander Bezzubikov
---
hw/ide/bridge.h | 9 +
hw/ide/internal.h | 3 ++-
hw/ide/qdev.c | 40
3 files changed, 51 insertions(+), 1 deletion(-)
create mode 100644 hw/ide/bridge.h
diff --git a/hw/ide/bridge.h b/hw/ide/bridge
Signed-off-by: Alexander Bezzubikov
---
hw/scsi/scsi-disk.c| 12
include/hw/scsi/scsi.h | 13 +
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c
index f67d816..9d5f0a4 100644
--- a/hw/scsi/scsi-disk.c
+++ b/hw/
On 08/14/2015 06:15 AM, Paolo Bonzini wrote:
> +atomic_mb_set(¤t_cpu, cpu);
...
> +cpu_exit(atomic_rcu_read(¤t_cpu));
Mixing java and rcu style sync to the same data structure?
> + * ensure tcg_exit_req is read before exit_request
> + *
On 2015-08-13 14:12, Leon Alrae wrote:
> On 10/07/2015 10:57, Pavel Dovgalyuk wrote:
> > @@ -2364,14 +2363,12 @@ static void gen_st_cond (DisasContext *ctx,
> > uint32_t opc, int rt,
> > #if defined(TARGET_MIPS64)
> > case OPC_SCD:
> > case R6_OPC_SCD:
> > -save_cpu_state(ctx, 1
On Mon, Aug 17, 2015 at 07:39:14PM +1000, Benjamin Herrenschmidt wrote:
> On Sun, 2015-07-05 at 09:19 +1000, Benjamin Herrenschmidt wrote:
> > he current code walks up the bus tree for an iommu, however it passes
> > to the iommu_fn() callback the bus/devfn of the immediate child of
> > the level w
On 08/17/2015 02:09 PM, Chen Gang wrote:
On 8/18/15 01:31, Richard Henderson wrote:
On 08/15/2015 11:16 AM, Chen Gang wrote:
But what you said is really quite valuable to me!! we can treat the flag
as a caller saved context, then can let the caller can use callee freely
(in fact, I guess, the
Remove arguments that can be found in PCMachineState.
Signed-off-by: Eduardo Habkost
---
Changes v1 -> v2:
* Change prototype on xen-hvm-stub.c too
---
hw/i386/pc_piix.c| 4 +---
hw/i386/pc_q35.c | 4 +---
include/hw/xen/xen.h | 4 ++--
xen-hvm-stub.c | 3 +--
xen-hvm.c
On 2015-08-17 18:25, Artyom Tarasenko wrote:
> On Mon, Aug 17, 2015 at 5:40 PM, Richard Henderson wrote:
> > On 08/17/2015 07:19 AM, Artyom Tarasenko wrote:
> >> Well, on the other hand, every access goes via helper_check_align.
> >> There is a comment /* XXX remove alignment check */.
> >> I wond
Rather than allow arbitrary shift+trunc, only concern ourselves
with low and high parts. This is all that was being used anyway.
Signed-off-by: Richard Henderson
---
target-tricore/translate.c | 12 ++--
tcg/README | 14 ++
tcg/aarch64/tcg-target.h | 3 ++-
From: Aurelien Jarno
Add two accessor functions temp_is_const and temp_is_copy, to make the
code more readable and make code change easier.
Cc: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Aurelien Jarno
---
tcg/optimize.c | 131 ++
On 8/18/15 01:31, Richard Henderson wrote:
> On 08/15/2015 11:16 AM, Chen Gang wrote:
>
>> But what you said is really quite valuable to me!! we can treat the flag
>> as a caller saved context, then can let the caller can use callee freely
>> (in fact, I guess, the real hardware treats it as calle
This way we can set legacy_acpi_table_size on the machine_options()
functions, instead of requirng code in pc_compat_*() functions.
Signed-off-by: Eduardo Habkost
---
hw/i386/pc_piix.c| 40 +++-
include/hw/i386/pc.h | 1 +
2 files changed, 20 insertions(+
From: Aurelien Jarno
The tcg_gen_trunc_shr_i64_i32 function takes a 64-bit argument and
returns a 32-bit value. Directly call tcg_gen_op3 with the correct
types instead of calling tcg_gen_op3i_i32 and abusing the TCG types.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/
From: Aurelien Jarno
Softmmu unaligned load/stores currently goes through through the slow
path for two reasons:
- to support unaligned access on host with strict alignement
- to correctly handle accesses crossing pages
x86 is only concerned by the second reason. Unaligned accesses are
avoid
From: Aurelien Jarno
Now that copies and constants are tracked separately, we can allow
constant to have copies, deferring the choice to use a register or a
constant to the register allocation pass. This prevent this kind of
regular constant reloading:
-OUT: [size=338]
+OUT: [size=298]
mov
This way we don't need code in pc_compat_*() functions to set the legacy
acpi_data_size value.
Signed-off-by: Eduardo Habkost
---
hw/i386/pc.c | 17 ++---
hw/i386/pc_piix.c| 2 +-
hw/i386/pc_q35.c | 2 +-
include/hw/i386/pc.h | 6 --
4 files changed, 12 inserti
On Thu, Aug 13, 2015 at 11:30:57AM -0400, Richard Smith wrote:
> On 08/09/2015 09:48 PM, Ed Swierk wrote:
>
>
> >References to coreboot commits: * Original commit adding code reading
> >register offsets 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 to
> >Intel 440bx code in coreboot:
> >cb8eab48
From: Aurelien Jarno
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/README | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/tcg/README b/tcg/README
index 61b3899..a22f251 100644
--- a/tcg/README
+++ b/tcg/README
@@ -466,13 +466,25 @@ On a 32
Signed-off-by: Richard Henderson
---
tcg/s390/tcg-target.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index 96c3d65..be51c8b 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -1504,2
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 37 -
1 file changed, 24 insertions(+), 13 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 7f7ab7e..bc3a539 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarc
On Thu, Aug 13, 2015 at 02:06:04PM +0300, Michael S. Tsirkin wrote:
> On Fri, Aug 07, 2015 at 04:55:56PM -0300, Eduardo Habkost wrote:
[...]
> > @@ -1159,7 +1158,7 @@ static void xen_wakeup_notifier(Notifier *notifier,
> > void *data)
> > }
> >
> > /* return 0 means OK, or -1 means critical is
Commit 19109131 disabled the sdhci-pci support because it used
drive_get_next(). This patch reenables sdhci-pci and changes it to
pass the drive via a qdev property - for example:
-device sdhci-pci,drive=drive0 -drive id=drive0,if=sd,file=myimage
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Kevi
This commit adds support for non stereo audio playback. This commit
adds two new properties to usb-audio:
* channels = the number of channels
* channel-config = the channel config to use. Should be 3 for stereo,
0x3f for 5.1 and 0x63f for 7.1 audio. See USB Device Class Definition
for Audio
Which currently only means removing some checks. Old code won't require
more than two channels, but new code will need it.
Signed-off-by: Kővágó, Zoltán
---
audio/alsaaudio.c | 7 ---
audio/audio.c | 2 +-
2 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/audio/alsaaudio.c b
On 08/15/2015 11:16 AM, Chen Gang wrote:
> OK, thanks, but for float(uns)sisf2 and float(uns)sidf2, we can not only
> simply move. :-(
Oh yes, I see that now. Unfortunate.
> But what you said is really quite valuable to me!! we can treat the flag
> as a caller saved context, then can let the ca
Add an option to change the channel map used by pulseaudio. If not
specified, falls back to an ALSA compatible channel map.
Signed-off-by: Kővágó, Zoltán
---
audio/paaudio.c | 18 +++---
qapi/audio.json | 5 -
qemu-options.hx | 9 +
3 files changed, 24 insertions(+), 8
This assumption is no longer true when mixeng is turned off.
Signed-off-by: Kővágó, Zoltán
---
hw/usb/dev-audio.c | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/hw/usb/dev-audio.c b/hw/usb/dev-audio.c
index 48ac992..f916ccc 100644
--- a/hw/us
This patch series adds support to more than two channels of audio (5.1,
7.1, etc.). Currently only usb-audio frontend and alsa and pa backends
are updated. Using more than two channels requires turning off mixeng
(-audiodev backend,id=foo,out.mixeng=off,...).
Currently you have to specify the nu
On Mon, Aug 17, 2015 at 5:40 PM, Richard Henderson wrote:
> On 08/17/2015 07:19 AM, Artyom Tarasenko wrote:
>> Well, on the other hand, every access goes via helper_check_align.
>> There is a comment /* XXX remove alignment check */.
>> I wonder how this can be done in a more efficient way?
>
> N
On Mon, Aug 17, 2015 at 5:44 PM, Richard Henderson wrote:
> On 08/17/2015 04:35 AM, Artyom Tarasenko wrote:
>> Hi Richard,
>>
>> this patch seems to break a build when USE_LIVENESS_ANALYSIS is undefined.
>
> I suppose that's possible. If so, it must be a trivial error somewhere.
> Why in the worl
On 08/17/2015 04:35 AM, Artyom Tarasenko wrote:
> Hi Richard,
>
> this patch seems to break a build when USE_LIVENESS_ANALYSIS is undefined.
I suppose that's possible. If so, it must be a trivial error somewhere.
Why in the world would you want !USE_LIVENESS_ANALYSIS?
Are you simply trying to s
On 08/17/2015 07:19 AM, Artyom Tarasenko wrote:
> Well, on the other hand, every access goes via helper_check_align.
> There is a comment /* XXX remove alignment check */.
> I wonder how this can be done in a more efficient way?
Not ever access does so. There are only 3 memory related calls to c
On Thu, Jul 30, 2015 at 9:55 AM, Aurelien Jarno wrote:
> On 2015-07-30 05:47, Dennis Luehring wrote:
>> so your aarch64 is just less todo for qemu - not EVERY >= 16bit memory
>> access needs swapping or needs check for unaligned access to emulate
>> bus-erros
>
> On recent Intel CPU, the byteswapp
On Fri, Jul 24, 2015 at 04:21:03PM +0100, Peter Maydell wrote:
> Implement the AArch32 ATS1H* operations which perform
> Hyp mode stage 1 translations.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
> ---
> target-arm/helper.c | 22 ++
> 1 file changed, 2
On Fri, Jul 24, 2015 at 04:21:02PM +0100, Peter Maydell wrote:
> Apply the correct conditions in the ats_access() function for
> the ATS12NSO* address translation operations:
> * succeed at EL2 or EL3
> * normal UNDEF trap from NS EL1
> * trap to EL3 from S EL1 (only possible if EL3 is AArch64)
Am 14.08.2015 um 22:01 schrieb Alex Bennée:
Peter Lieven writes:
Hi,
some time a go I stumbled across a regression in the KVM Module that has been
introduced somewhere
between 3.17 and 3.19.
I have a rather old openSUSE guest with an XFS filesystem which realiably
crashes after some live m
Hi Richard,
this patch seems to break a build when USE_LIVENESS_ANALYSIS is undefined.
Regards,
Artyom
On Fri, Feb 13, 2015 at 6:43 AM, Richard Henderson wrote:
> The previous setup required ops and args to be completely sequential,
> and was error prone when it came to both iteration and optim
Am 31.07.2015 um 17:43 schrieb Aurelien Jarno:
> >Anyway I have extracted this code into a C file (see attached file) that
> >can more easily compiled to 32 or 64 bit using -m32 or -m64. I observe
> >the same behavior than sysbench, even with qemu-user (which is not
> >surprising as the above cod
On 15/08/2015 12:03, Paolo Bonzini wrote:
>
>
> On 15/08/2015 11:57, Pavel Dovgalyuk wrote:
>> Hi, Paolo!
>>
>> Will you apply these patches to 2.5?
>
> Yes, I'll put them in my next pull request.
Hi Pavel,
unfortunately I do have some more review comments; that can happen when
going back to
And since Ubuntu Wily ships 2.3, I presume this is also fixed in Ubuntu
in Wily. I'll mark that Fix Released too, and add a task for Trusty.
** Changed in: qemu (Ubuntu)
Status: New => Fix Released
** Also affects: qemu (Ubuntu Trusty)
Importance: Undecided
Status: New
** Change
Based on Max's comment this is Fix Released upstream.
** Also affects: qemu (Ubuntu)
Importance: Undecided
Status: New
** Changed in: qemu
Status: New => Fix Released
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
Commit ef546f1275f6563e8934dd5e338d29d9f9909ca6 ("virtio: add
feature checking helpers") introduced a helper __virtio_has_feature.
We don't want to use reserved identifiers, though, so let's
rename __virtio_has_feature to virtio_has_feature and virtio_has_feature
to virtio_vdev_has_feature.
Signed
On Sun, 2015-07-05 at 09:19 +1000, Benjamin Herrenschmidt wrote:
> he current code walks up the bus tree for an iommu, however it passes
> to the iommu_fn() callback the bus/devfn of the immediate child of
> the level where the callback was found, rather than the original
> bus/devfn where the sear
[root@PEK112301 qemu]# git bisect log
git bisect start
# bad: [074a9925e1cfd659d5376dcaccd1436d3840e611] Merge remote-tracking branch
'remotes/cody/tags/block-pull-request' into staging
git bisect bad 074a9925e1cfd659d5376dcaccd1436d3840e611
# good: [dfa83a6bae960e3e3a3186264d75790cfd727bce] U
* Peter Crosthwaite (crosthwaitepe...@gmail.com) wrote:
> Is there a functional reason for making this change, or pure
> organisational? Either way the patch is ok, I'm just looking for the
> motivation as this stuff did pop up in the multi-arch refactorings at
> one stage and I did think about mov
On Mon, 2015-08-17 at 17:34 +1000, Benjamin Herrenschmidt wrote:
> Currently, we get to the slow path for any unaligned access in the
> backend, because we effectively preserve the bottom address bits
> below the alignment requirement when comparing with the TLB entry,
> so any non-0 bit there will
To simplify the addition of new block modules, add a script that generates
include/qemu/module_block.h automatically from the modules' source code.
This script assumes that the QEMU coding style rules are followed.
Signed-off-by: Marc Marí
---
.gitignore | 1 +
Makefile
The current module infrastructure has been improved to enable dynamic module
loading.
This reduces the load time for very simple guests. For the following
configuration (very loaded)
./configure --enable-sdl --enable-gtk --enable-vte --enable-curses \
--enable-vnc --enable-vnc-{jpeg,tls,sasl,
Extend the current module interface to allow for block drivers to be loaded
dynamically on request.
The only block drivers that can be converted into modules are the drivers
that don't perform any init operation except for registering themselves. This
is why libiscsi has been disabled as a module.
Good catch, thanks stefanha for your kindly reminds with such good tools
(git-bisect) to determine which commit caused this problem. I'm very
sorry that i did not try it as your instruction timely, mainly that i
focus on the openstack(nova&cinder) currently in the new company and
have to adapt to t
On ppc64 especially, we flush the tlb on any slbie or tlbie instruction.
However, those instructions often come in bursts of 3 or more (context
switch will favor a series of slbie's for example to an slbia if the
SLB has less than a certain number of entries in it, and tlbie's can
happen in a seri
This is set to true when the index is for an instruction fetch
translation.
The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS
acessors.
All targets ignore it for now, and all other callers pass "false".
This will allow targets who wish to split the mmu index between
instructio
Currently, we get to the slow path for any unaligned access in the
backend, because we effectively preserve the bottom address bits
below the alignment requirement when comparing with the TLB entry,
so any non-0 bit there will cause the compare to fail.
For the same number of instructions, we can
We rework the way the MMU indices are calculated, providing separate
indices for I and D side based on MSR:IR and MSR:DR respectively,
and thus no longer need to flush the TLB on context changes. This also
adds correct support for HV as a separate address space.
Signed-off-by: Benjamin Herrenschmi
We don't use the resulting accessors and this gets in the way of
the split I/D TLB work.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 6f76674..5dfd195 100644
--- a/target-ppc/cpu.h
+++ b
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