On Thu, Jul 30, 2015 at 9:55 AM, Aurelien Jarno <aurel...@aurel32.net> wrote: > On 2015-07-30 05:47, Dennis Luehring wrote: >> so your aarch64 is just less todo for qemu - not EVERY >= 16bit memory >> access needs swapping or needs check for unaligned access to emulate >> bus-erros > > On recent Intel CPU, the byteswapping comes for free (MOVBE > instruction). > > About the unaligned access it's actually the reverse. The fact that > aarch64 does unaligned access means they have to go through the slow > path (I have posted a patch to improve that). On sparc given that all > access are aligned means there are more chances to go through the fast > path.
Well, on the other hand, every access goes via helper_check_align. There is a comment /* XXX remove alignment check */. I wonder how this can be done in a more efficient way? Inlining the check and using a brcond instruction would require that all TCG temps would have to be changed to locals, which in turn would produce a performance impact. Are there other ways of doing it? Artyom -- Regards, Artyom Tarasenko SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu
