On Fri, Jul 24, 2015 at 04:21:03PM +0100, Peter Maydell wrote:
> Implement the AArch32 ATS1H* operations which perform
> Hyp mode stage 1 translations.
>
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
> ---
> target-arm/helper.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 67d108e..b9ce965 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1607,6 +1607,17 @@ static void ats_write(CPUARMState *env, const
> ARMCPRegInfo *ri, uint64_t value)
> A32_BANKED_CURRENT_REG_SET(env, par, par64);
> }
>
> +static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
> + uint64_t value)
> +{
> + int access_type = ri->opc2 & 1;
> + uint64_t par64;
> +
> + par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
> +
> + A32_BANKED_CURRENT_REG_SET(env, par, par64);
> +}
> +
> static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo
> *ri)
> {
> if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
> @@ -2770,6 +2781,17 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
> .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
> .access = PL2_W, .accessfn = at_s1e2_access,
> .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
> + /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
> + * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
> + * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
> + * to behave as if SCR.NS was 1.
> + */
> + { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
> + .access = PL2_W,
> + .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
> + { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
> + .access = PL2_W,
> + .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
> #endif
> REGINFO_SENTINEL
> };
> --
> 1.9.1
>
