Hi,
> Applied, thanks.
>
> You forgot to add your maintainer's signoff to one of Ben's patches.
> Since it was a one-liner I didn't think it was worth bouncing the
> pullreq for, but you might want to consider adding something to your
> pre-pull sanity checks.
checkpatch already does that and
Previously, qemu block driver of sheepdog used hard-coded VDI object size.
This patch enables users to handle "block_size_shift" value for
calculating VDI object size.
When you start qemu, you don't need to specify additional command option.
But when you create the VDI which doesn't have default
On 19/01/2015 22:31, Michael S. Tsirkin wrote:
> On Mon, Jan 19, 2015 at 05:56:24PM +0100, Paolo Bonzini wrote:
>> > See v2 for motivation.
>> >
>> > v2->v3: dropped pointer passing and patch 4.
> Thanks!
> Igor - ok with you?
FWIW I'm okay with moving stuff back to the SSDT as part of Igor's o
> From: Paolo Bonzini [mailto:pbonz...@redhat.com]
> On 19/01/2015 14:10, Pavel Dovgaluk wrote:
> >>> > >
> >>> > > Because 'A' is written only inside some of the replay_run_event
> >>> > > callbacks.
> >>> > > It depends on type of the event and it's processing function inside
> >>> > > the QEMU
On 2015/1/19 19:36, Gerd Hoffmann wrote:
On Mo, 2015-01-19 at 17:28 +0800, Tiejun Chen wrote:
From: "Michael S. Tsirkin"
Xen wants to supply a different pci and host devices,
inheriting i440fx devices. Make types configurable.
Description is misleading, this isn't about xen but about IGD
pas
On 2015/1/20 12:28, Jike Song wrote:
On 01/20/2015 10:52 AM, Chen, Tiejun wrote:
On 2015/1/19 19:40, Gerd Hoffmann wrote:
On Mo, 2015-01-19 at 17:28 +0800, Tiejun Chen wrote:
+static void xen_igd_passthrough_i440fx_class_init(ObjectClass *klass,
+
Use the asynchronous interface of ioctl. This will not make the VM
unresponsive if the ioctl takes a long time.
Signed-off-by: Fam Zheng
---
hw/block/virtio-blk.c | 125 +++---
1 file changed, 79 insertions(+), 46 deletions(-)
diff --git a/hw/block/vi
There are user complaints on guest's unresponsiveness when ioctl is blocked due
to the lost connection to backend or other issues. This series changes scsi
request processing of virtio-blk to an asynchronous manner.
Fam Zheng (2):
virtio-blk: Pass req to virtio_blk_handle_scsi_req
virtio-blk
In preparation for calling blk_aio_ioctl. Also make the function static
as no other files need it.
Signed-off-by: Fam Zheng
---
hw/block/virtio-blk.c | 9 +
include/hw/virtio/virtio-blk.h | 3 ---
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/hw/block/virtio-blk
On Mon, Jan 12, 2015 at 9:32 AM, Bharata B Rao
wrote:
> 1st patch fixes PC DIMMs capacity calculation and the 2nd patch does
> code movement so that pc_existing_dimms_capacity() can be used by
> other architectures.
>
> Bharata B Rao (2):
> pc: Fix DIMMs capacity calculation
> pc-dimm: Make pc
> -Original Message-
> From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
> Sent: Tuesday, January 20, 2015 1:15 AM
> To: Xu, Quan
> Cc: qemu-devel@nongnu.org; xen-de...@lists.xen.org;
> stefano.stabell...@eu.citrix.com
> Subject: Re: [v3 3/5] Qemu-Xen-vTPM: Register Xen s
On 2015/1/19 19:45, Gerd Hoffmann wrote:
On Mo, 2015-01-19 at 17:28 +0800, Tiejun Chen wrote:
+DEF("gfx_passthru", 0, QEMU_OPTION_gfx_passthru,
+"-gfx_passthru enable Intel IGD passthrough by XEN\n",
+QEMU_ARCH_ALL)
+STEXI
+@item -gfx_passthru
+@findex -gfx_passthru
+Enable Intel IGD p
On 2015/1/19 19:40, Gerd Hoffmann wrote:
On Mo, 2015-01-19 at 17:28 +0800, Tiejun Chen wrote:
+static void xen_igd_passthrough_i440fx_class_init(ObjectClass *klass,
+ void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+
+dc->desc = "IG
On 2015/1/19 19:36, Gerd Hoffmann wrote:
On Mo, 2015-01-19 at 17:28 +0800, Tiejun Chen wrote:
From: "Michael S. Tsirkin"
Xen wants to supply a different pci and host devices,
inheriting i440fx devices. Make types configurable.
Description is misleading, this isn't about xen but about IGD
I
> -Original Message-
> From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
> Sent: Tuesday, January 20, 2015 1:15 AM
> To: Xu, Quan
> Cc: qemu-devel@nongnu.org; xen-de...@lists.xen.org;
> stefano.stabell...@eu.citrix.com
> Subject: Re: [v3 2/5] Qemu-Xen-vTPM: Xen frontend d
On 2015/1/19 21:58, Michael S. Tsirkin wrote:
On Mon, Jan 19, 2015 at 12:57:18PM +0100, Gerd Hoffmann wrote:
On Mo, 2015-01-19 at 17:28 +0800, Tiejun Chen wrote:
Currently IGD drivers always need to access PCH by 1f.0. But we
Obvious question: q35?
q35 already has a isa bridge @ 0x1f.0. Gue
> -Original Message-
> From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
> Sent: Tuesday, January 20, 2015 1:19 AM
> To: Xu, Quan
> Cc: qemu-devel@nongnu.org; xen-de...@lists.xen.org;
> stefano.stabell...@eu.citrix.com
> Subject: Re: [v3 3/5] Qemu-Xen-vTPM: Register Xen s
> -Original Message-
> From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
> Sent: Tuesday, January 20, 2015 1:53 AM
> To: Stefano Stabellini
> Cc: Xu, Quan; qemu-devel@nongnu.org; xen-de...@lists.xen.org;
> lcapitul...@redhat.com; ebl...@redhat.com; arm...@redhat.com;
> al
On Mon, 2015-01-19 at 16:55 +0100, Igor Mammedov wrote:
> On Fri, 16 Jan 2015 13:45:06 +0800
> Zhu Guihua wrote:
>
> > If hot add 100MiB memory like this:
> > (monitor) object_add memory-backend-ram,id=ram0,size=100M
> > (monitor) device_add pc-dimm,id=d0,memdev=ram0
> >
> > The hotplug operatio
On Mon, Jan 19, 2015 at 11:30:51AM -0800, Richard Henderson wrote:
> On 01/19/2015 11:00 AM, Peter Maydell wrote:
> > Alternatively (better!), for a lot of the tlb_flush()es triggered
> > by target-arm code we could be more precise about the affected
> > mmu_idx values, since the common case is goi
Add 32-bit to/from 64-bit register synchronization on register gets and puts.
Set EL1_32BIT feature flag passed to KVM
Signed-off-by: Greg Bellows
---
target-arm/kvm64.c | 21 +
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/target-arm/kvm64.c b/target-arm/kvm
Add AArch32 to AArch64 register sychronization functions.
Replace manual register synchronization with new functions in
aarch64_cpu_do_interrupt() and HELPER(exception_return)().
Signed-off-by: Greg Bellows
---
target-arm/helper-a64.c | 5 +--
target-arm/internals.h | 89 ++
Hello,
I’d like to simulate mouse/keyboard input events to a qemu guest. I am planning
to hijack the sdl_refresh function in ui/sdl.c. Is that the right approach?
Also, is there a way to build QEMU as a library that can be called from another
application that can send such inputs?
- Manoj
Adjust the kernel load offset by 0x8000 if not a zImage.
Signed-off-by: Pranavkumar Sawargaonkar
Signed-off-by: Greg Bellows
---
hw/arm/boot.c | 33 -
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 52ebd8b..b581c
Added machvirt parsing of feature keywords added to the -cpu command line
option. Parsing occurs during machine initialization.
Signed-off-by: Greg Bellows
---
hw/arm/virt.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
Adds a CPU feature parsing function and assigns to the CPU class. The only
feature added was "-aarch64" which disabled the AArch64 execution state on a
64-bit ARM CPU.
Also adds stripping of features from CPU model string in acquiring the ARM CPU
by name.
Signed-off-by: Greg Bellows
---
target
Added support for running an AArch32 guest on a AArch64 KVM host. Support has
only been added to the QEMU machvirt machine. The addition of CPU properties
specifiable from the command line were added to allow disablement of AArch64
execution state hereby forcing EL1 to be AArch32. The new CPU co
Subject was:
Re: [PATCH v7] block/raw-posix.c: Fixes raw_getlength()
on Mac OS X so that it reports the correct length of a real CD
This patch allows Mac OS X to use a real CDROM disc in QEMU.
Testing this patch will require using QEMU v2.2.0 because the
current git version has a bug in it that
On Fri, Dec 19, 2014 at 02:02:37AM +, Igor Mammedov wrote:
> keeping bios-linker-loader.c i386 specific would break build
> of mips target which is built with CONFIG_ACPI which would
> dependend on it in following patch that adds acpi_def_block()
> term. Also UEFI for ARM target is going to use
As m48t59 devices can only be created with m48t59_init() or m48t59_init_isa(),
we know exactly which nvram types are required. Register only those three
types.
Remove .model and .size properties as they can be infered from nvram name.
Rename type to 'isa-*' (and 'sysbus-*') to do like other device
Remove left-overs from header file.
Move some functions only used by PReP to hw/ppc/prep.c
Signed-off-by: Hervé Poussineau
---
hw/ppc/ppc.c | 161 -
hw/ppc/prep.c | 161 +
hw/sparc/
-device m48t59_isa can now be used to create a fully functional nvram.
Signed-off-by: Hervé Poussineau
---
hw/timer/m48t59.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c
index 31509d5..967a313 100644
--- a
Signed-off-by: Hervé Poussineau
---
hw/timer/m48t59.c | 59 +
include/hw/timer/m48t59.h | 24 ++
2 files changed, 83 insertions(+)
diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c
index c46b63c..c5e74ce 100644
--- a/hw/tim
Hi,
This patchset QOM'ifies the m48t59 timer.
Patch 1 allows the creation of the m4859 ISA device from the command line.
Patch 2 QOM'ifies the device.
Patches 3 add a Nvram interface to m48txx devices, so that callers can
detect the device and use it without knowing m48txx internals.
Patch 4 is us
Le 19/01/2015 12:35, Mark Cave-Ayland a écrit :
This patch lays the groundwork for switching sun4u over from ioport NVRAM
access to MMIO NVRAM access.
Patch 1 introduces a new year_offset property which is the offset between the
year value stored in hardware and the actual year. In particular, S
On Mon, Jan 19, 2015 at 01:42:25PM +0100, Paolo Bonzini wrote:
>
>
> On 19/12/2014 03:02, Igor Mammedov wrote:
> > Replace template patching and runtime
> > calculation in _CRS() method with static _CRS
> > defined in SSDT.
> >
> > It also drops manual hole patching for reserved
> > PCI/MEM/CPU
On Mon, Jan 19, 2015 at 01:36:36PM +0100, Paolo Bonzini wrote:
>
>
> On 19/12/2014 03:02, Igor Mammedov wrote:
> > keeping bios-linker-loader.c i386 specific would break build
> > of mips target which is built with CONFIG_ACPI which would
> > dependend on it in following patch that adds acpi_def_
On Mon, Jan 19, 2015 at 09:23:38PM +0800, arei.gong...@huawei.com wrote:
> From: Gonglei
>
> Because vhost-scsi module do not support VHOST_SCSI_GET_TPGT
> at present, so I use "#if 0" handle it, and set the target
> default to 1. In addition, channel and lun both are 0 for
> bootable vhost-scsi
On Mon, Jan 19, 2015 at 05:00:38PM +0100, Markus Armbruster wrote:
> Andreas Färber writes:
>
> > Hi Markus,
> >
> > Am 19.01.2015 um 15:52 schrieb Markus Armbruster:
> >> I posted this series as RFC back in October, but it depended on
> >> patches then still under review, so I put it aside, and
Signed-off-by: Hervé Poussineau
---
hw/mips/mips_r4k.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c
index 5b982f2..3e90e27 100644
--- a/hw/mips/mips_r4k.c
+++ b/hw/mips/mips_r4k.c
@@ -165,7 +165,8 @@ void mips_
Currently, keep current behaviour by always using get_system_memory().
Also use QOM casts when possible.
Signed-off-by: Hervé Poussineau
---
hw/alpha/typhoon.c |2 +-
hw/i386/pc_piix.c|2 +-
hw/isa/i82378.c |3 ++-
hw/isa/isa-bus.c | 11 ---
hw/isa/lpc_ich9.
Also remove address_space and address_space_io parameters, which
where always get_system_memory() and get_system_io().
Signed-off-by: Hervé Poussineau
---
hw/mips/mips_jazz.c | 21 -
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/hw/mips/mips_jazz.c b/hw/mip
On Mon, Jan 19, 2015 at 05:56:24PM +0100, Paolo Bonzini wrote:
> See v2 for motivation.
>
> v2->v3: dropped pointer passing and patch 4.
Thanks!
Igor - ok with you?
> Paolo Bonzini (3):
> pc: append ssdt-misc.dsl to the DSDT
> pc: rename ssdt-misc to dsdt-common
> pc: move common parts of
Create a custom address space for PCI memory region and use it for the PCI bus.
However, continue to hardcode VGA window address at 0x1000 instead of
calculating its address dynamically.
Signed-off-by: Hervé Poussineau
---
I would be quite happy if someone knowing gt64xxx better than me can
Now that isa_mem_base variable is always 0, we can remove its usage.
Signed-off-by: Hervé Poussineau
---
hw/display/cirrus_vga.c |2 +-
hw/display/vga-isa.c|2 +-
hw/display/vga.c|3 +--
hw/isa/isa-bus.c|1 -
include/hw/isa/isa.h|2 --
5 files changed,
piix4 is only used on MIPS Malta board, which gives get_system_memory()
to pci_register_bus().
Signed-off-by: Hervé Poussineau
---
hw/isa/piix4.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 0cacc3b..a9916df 100644
--- a/hw/isa/piix
Do assorted changes in memory-mapped rtc interface.
Also fix size of ISA I/O memory region, which should be 0x1 bytes.
Signed-off-by: Hervé Poussineau
---
hw/mips/mips_jazz.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/hw/mips/mips_jazz.
Hi,
This patchset removes the isa_mem_base variable in VGA display devices.
This variable is a global variable telling at which address is the
ISA memory base address in the system memory address space.
Once removed, we're paving the way to new QEMU functionalities:
- supporting other MMIO ISA de
On Wed, Jan 07, 2015 at 02:49:40PM +0800, Tang Chen wrote:
> Memory and CPU hot unplug are both asynchronize procedures.
> When the unplug operation happens, unplug request cb is called first.
> And when ghest OS finished handling unplug, unplug cb will be called
> to do the real removal of device.
On Mon, Jan 19, 2015 at 08:57:55PM +0100, Paolo Bonzini wrote:
>
>
> On 19/01/2015 20:33, Michael S. Tsirkin wrote:
> >>> > > so we probably should apply anyway the patch of
> >>> > > mine that allows the DSDT size to change; and we probably should pay
> >>> > > attention to SSDT, and version it.
Le 19/01/2015 16:01, Andreas Färber a écrit :
Also, wasn't Hervé's(?) plan to get rid of mem_base completely by always
passing a pointer to ISADevice/ISABus around? It should only be needed
when somewhere NULL is being passed, no?
Yes, I've a patch series which is removing the isa_mem_base vari
On 2015-01-19 at 16:04, Eric Blake wrote:
On 01/19/2015 01:49 PM, Max Reitz wrote:
With the series adding unalignment checks and the series reworking the
zero cluster expansion code overlapping, the unalignment checks have not
been implemented in the latter code.
This series fixes it.
There ar
On 01/19/2015 05:08 AM, Markus Armbruster wrote:
John Snow writes:
On 01/16/2015 10:36 AM, Max Reitz wrote:
On 2015-01-12 at 11:30, John Snow wrote:
From: Fam Zheng
The new command pair is added to manage user created dirty bitmap. The
dirty bitmap's name is mandatory and must be unique
On 01/19/2015 01:49 PM, Max Reitz wrote:
> With the series adding unalignment checks and the series reworking the
> zero cluster expansion code overlapping, the unalignment checks have not
> been implemented in the latter code.
>
> This series fixes it.
>
> There are other places which would requ
Signed-off-by: Max Reitz
---
tests/qemu-iotests/060 | 15 +++
tests/qemu-iotests/060.out | 13 +
2 files changed, 28 insertions(+)
diff --git a/tests/qemu-iotests/060 b/tests/qemu-iotests/060
index 73863bf..c81319c 100755
--- a/tests/qemu-iotests/060
+++ b/tests/qemu-
This adds checks for unaligned L2 table offsets and unaligned data
cluster offsets (actually the preallocated offsets for zero clusters) to
the zero cluster expansion function.
Signed-off-by: Max Reitz
---
block/qcow2-cluster.c | 21 +
1 file changed, 21 insertions(+)
diff -
With the series adding unalignment checks and the series reworking the
zero cluster expansion code overlapping, the unalignment checks have not
been implemented in the latter code.
This series fixes it.
There are other places which would require unalignment checks, like the
offsets of L1 tables,
Instead of re-querying the AHCI device for the FB and CLB buffers, save
the pointer we gave to the device during initialization and reference
these values instead.
Signed-off-by: John Snow
Reviewed-by: Paolo Bonzini
---
tests/ahci-test.c | 42 --
tests/
These macros were a bad idea: They relied upon certain arguments being
present locally with a specific name.
With the endgoal being to factor out AHCI helper functions outside of
the test file itself, these have to be replaced by more explicit helper
setter/getter functions.
Signed-off-by: John S
With global state removed, code responsible for booting up,
verifying, and initializing the AHCI HBA is extracted and
inserted into libqos/ahci.c, which would allow for other
qtests in the future to quickly grab a meaningfully initialized
reference to an AHCI HBA.
Even without other users, functio
Introduce a set of "static inline" register helpers that are intended to
replace the current set of macros with more functional versions that are
better suited to inclusion in libqos than porcelain macros.
As a stopgap measure before eliminating the porcelain macros, define them
to use the new fun
Make helper routines rely on the earmarked
guest allocator object with AHCIQState/QOSSTate instead.
Signed-off-by: John Snow
Reviewed-by: Paolo Bonzini
---
tests/ahci-test.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/tests/ahci-test.c b/tests/ahci-tes
Create an operations structure so that the libqos interface can be
architecture agnostic, and create a pc-specific interface to functions
like qtest_boot.
Move the libqos object in the Makefile from being ahci-test only to
being linked with all tests that utilize the libqos features.
Signed-off-b
Rely on the PCI Device's bus pointer instead.
One less global to worry about.
Signed-off-by: John Snow
Reviewed-by: Paolo Bonzini
---
tests/ahci-test.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/tests/ahci-test.c b/tests/ahci-test.c
index 96fb45c..0cc56ab
Store the HBA memory base address in the new state object, to simplify
function prototypes and encourage a more functional testing style.
This causes a lot of churn, but this patch is as "simplified" as I could
get it to be. This patch is therefore fairly mechanical and straightforward:
Any case w
Extract defines and other information to ahci.h, to be shared with other
tests if they so please.
At the very least, reduce clutter in the test file itself.
Signed-off-by: John Snow
Reviewed-by: Paolo Bonzini
---
tests/ahci-test.c | 319 +--
tests/
The intent of this file is to serve as a misc. utilities file to be
shared amongst tests that are utilizing libqos facilities.
In a later patch, migration test helpers will be added to libqos.c that
will allow simplified testing of migration cases where libqos is
"Just Enough OS" for migrations te
Add a va_list variant of the qtest_boot function.
Signed-off-by: John Snow
Reviewed-by: Paolo Bonzini
---
tests/libqos/libqos.c | 25 +++--
tests/libqos/libqos.h | 1 +
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/tests/libqos/libqos.c b/tests/libqos/libq
Move barsize, ahci_fingerprint and capabilities registers into
the AHCIQState object, removing global ahci-related state
from the ahci-test.c file.
More churn, less globals.
Signed-off-by: John Snow
Reviewed-by: Paolo Bonzini
---
tests/ahci-test.c | 80 +--
Allow a generic interface to alloc_init_flags,
not just through pc_alloc_init_flags.
Signed-off-by: John Snow
Reviewed-by: Paolo Bonzini
---
tests/libqos/malloc-pc.c | 4 +---
tests/libqos/malloc.c| 8
tests/libqos/malloc.h| 2 ++
3 files changed, 11 insertions(+), 3 deletions(
To avoid the architecture-specific implementations of the generic qtest
allocator having to know about fields within the allocator, add a
page_size setter method for users or arch specializations to use.
The allocator will assume a default page_size for general use, but it
can always be overridden.
This series aims to do two main things:
(1) Eliminate global state out of the ahci-test file so that
the tests are more functional. This will allow me to write
migration tests more easily. These tests are already written
and will be submitted upstream after these refactor series.
(2)
Move the list-specific initialization over into
malloc.c, to keep all of the list implementation
details within the same file.
The allocation and freeing of these structures are
now both back within the same layer.
Signed-off-by: John Snow
Reviewed-by: Paolo Bonzini
---
tests/libqos/malloc-pc.
Am 19.01.2015 um 16:22 schrieb Artyom Tarasenko:
> On Mon, Jan 19, 2015 at 4:01 PM, Andreas Färber wrote:
>> Am 19.01.2015 um 13:57 schrieb Artyom Tarasenko:
>>> On Mon, Jan 19, 2015 at 1:45 PM, Paolo Bonzini wrote:
On 19/01/2015 12:35, Mark Cave-Ayland wrote:
> Similar to m48t59_init(),
On 19/01/2015 19:13, Andreas Färber wrote:
> Am 19.01.2015 um 12:24 schrieb Paolo Bonzini:
>> Due to a typo, instead of disabling KVM_FEATURE_PV_EOI (bit
>> 6) these machine types are disabling bits 1 and 2, which are
>> KVM_FEATURE_NOP_IO_DELAY and KVM_FEATURE_MMU_OP. Not a big deal
>> because
On 19/01/2015 20:33, Michael S. Tsirkin wrote:
>>> > > so we probably should apply anyway the patch of
>>> > > mine that allows the DSDT size to change; and we probably should pay
>>> > > attention to SSDT, and version it.
> Oh, missed that.
> You mean this: "Add padding after the DSDT"?
Yes.
>
On Mon, Jan 19, 2015 at 09:29:57PM +0200, Michael S. Tsirkin wrote:
> On Mon, Jan 19, 2015 at 06:26:55PM +0100, Paolo Bonzini wrote:
> >
> >
> > On 19/01/2015 18:14, Igor Mammedov wrote:
> > > I'm fine with moving "SMC out of the per-machine-type AML", should be
> > > a separate patch anyway. But
On 01/19/2015 11:00 AM, Peter Maydell wrote:
> Alternatively (better!), for a lot of the tlb_flush()es triggered
> by target-arm code we could be more precise about the affected
> mmu_idx values, since the common case is going to be
> "NS EL1 did something that needs a TLB flush", and by definition
On Mon, Jan 19, 2015 at 06:26:55PM +0100, Paolo Bonzini wrote:
>
>
> On 19/01/2015 18:14, Igor Mammedov wrote:
> > I'm fine with moving "SMC out of the per-machine-type AML", should be
> > a separate patch anyway. But patch-able SMC being in DSDT is our mistake
> > that we allowed it to slip ther
On 01/19/2015 11:16 AM, Marc-André Lureau wrote:
> Hey
>
> Thanks for proposing passthrough mode. It can be useful in some cases,
> although it's good to mention it's not safe to concurrently share a
> card with other applications since no locking is provided (and I don't
> know if and how it's po
On Mon, Jan 19, 2015 at 1:03 PM, Peter Maydell
wrote:
> On 19 January 2015 at 18:05, Greg Bellows wrote:
> >
> >
> > On Mon, Jan 19, 2015 at 9:17 AM, Peter Maydell >
> > wrote:
> >> +if (ri->type & ARM_CP_CONST) {
> >> +return true;
> >> +}
> >
> >
> > Had to refresh my memory o
On Mon, Jan 19, 2015 at 1:07 PM, Peter Maydell
wrote:
> On 19 January 2015 at 19:05, Greg Bellows wrote:
> >
> >
> > On Mon, Jan 19, 2015 at 1:03 PM, Peter Maydell >
> > wrote:
> >> Doh. I inverted the name and polarity but forgot to change the function
> >> body. (I have no idea why that didn'
On 19 January 2015 at 19:05, Greg Bellows wrote:
>
>
> On Mon, Jan 19, 2015 at 1:03 PM, Peter Maydell
> wrote:
>> Doh. I inverted the name and polarity but forgot to change the function
>> body. (I have no idea why that didn't blow up). Will fix (and test a
>> bit more thoroughly...)
>>
>
> FYI,
On 19 January 2015 at 18:05, Greg Bellows wrote:
>
>
> On Mon, Jan 19, 2015 at 9:17 AM, Peter Maydell
> wrote:
>> +if (ri->type & ARM_CP_CONST) {
>> +return true;
>> +}
>
>
> Had to refresh my memory on this. It appears we changed the name (polarity)
> of the function based on ou
On 19 January 2015 at 17:44, Richard Henderson wrote:
> On 01/19/2015 05:22 AM, Peter Maydell wrote:
>> Richard: do you have a feel for how expensive it is to
>> have lots and lots of mmu modes? I might be able to
>> merge "S EL1" with "NS EL1 stage 1+2" and ditto "S EL0"
>> with "NS EL0 stage1 +
On 19 January 2015 at 17:19, Greg Bellows wrote:
>> { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
>> - .type = ARM_CP_NO_MIGRATE,
>> + .type = ARM_CP_ALIAS,
>>.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
>>.access = PL1_RW,
>>.fieldoffset = offseto
On Mon, 19 Jan 2015, Paolo Bonzini wrote:
> >> The reason I asked is simply because ISA devices never do MMIO (apart
> >> for the VGA window).
> >
> > You mean in the QEMU world? At least physical SCSI and Ethernet
> > adapters had a MMIO space for the onboard ROM.
>
> Uh right, ROMs count as MM
Hello,
there is an issue which is not a bug itself (as anyone who plays with
Windows should be advised to use hypervclock timers), but it can
indicate some issue with interrupt handling.
Assume two launch strings (attached), and execution of
'{"execute":"cpu-add","arguments":{"id":1}}'
the "reg
Am 19.01.2015 um 12:24 schrieb Paolo Bonzini:
> Due to a typo, instead of disabling KVM_FEATURE_PV_EOI (bit
> 6) these machine types are disabling bits 1 and 2, which are
> KVM_FEATURE_NOP_IO_DELAY and KVM_FEATURE_MMU_OP. Not a big deal
> because they aren't very important and KVM_FEATURE_MMU_OP i
Programmingkid writes:
> On Jan 16, 2015, at 3:22 AM, Markus Armbruster wrote:
>
>> Programmingkid writes:
>>
>>> This patch allows Mac OS X to use a real CDROM disc in
>>> QEMU. Testing this patch will require using QEMU v2.2.0 because the
>>> current git version has a bug in it that prevents
On Mon, Jan 19, 2015 at 9:17 AM, Peter Maydell
wrote:
> Add assertion checking when cpreg structures are registered that they
> either forbid raw-access attempts or at least make an attempt at
> handling them. Also add an assert in the raw-accessor-of-last-resort,
> to avoid silently doing a read
On Mon, 19 Jan 2015, Stefano Stabellini wrote:
> Hi Quan,
> thanks for the update: this version is much much better than the
> previous one.
>
> I am not familiar enough with QAPI, HMP and TPM to review the first and
> the last patches though.
I meant the first and the fourth. The last one is fin
Paolo Bonzini writes:
> On 13/01/2015 04:34, John Snow wrote:
>> +tests/ahci-test$(EXESUF): tests/ahci-test.o $(libqos-pc-obj-y) \
>> + tests/libqos/ahci.o
>
> Why not add this to libqos-pc-obj-y or libqos-obj-y?
>
>>
>> + * Allocate space in the guest using information
On 01/19/2015 12:15 PM, Paolo Bonzini wrote:
On 13/01/2015 04:34, John Snow wrote:
+tests/ahci-test$(EXESUF): tests/ahci-test.o $(libqos-pc-obj-y) \
+ tests/libqos/ahci.o
Why not add this to libqos-pc-obj-y or libqos-obj-y?
No strong reason, it's just that I am
On 01/19/2015 09:32 AM, Programmingkid wrote:
>
> On Jan 16, 2015, at 3:22 AM, Markus Armbruster wrote:
>
>> Programmingkid writes:
>>
>>> This patch allows Mac OS X to use a real CDROM disc in QEMU. Testing this
>>> patch will require using QEMU v2.2.0 because the current git version has a
>>
On 01/19/2015 05:22 AM, Peter Maydell wrote:
> Richard: do you have a feel for how expensive it is to
> have lots and lots of mmu modes? I might be able to
> merge "S EL1" with "NS EL1 stage 1+2" and ditto "S EL0"
> with "NS EL0 stage1 + 2" but we'd need to do more TLB
> flushing and it's not clear
On Fri, 2015-01-16 at 13:21 +0100, Maik Broemme wrote:
> Hi Alex,
>
> Maik Broemme wrote:
> > Hi Alex,
> >
> > Maik Broemme wrote:
> > > Hi Alex,
> > >
> > > Alex Williamson wrote:
> > > > On Fri, 2014-02-14 at 01:01 +0100, Maik Broemme wrote:
> > > > > Hi Alex,
> > > > >
> > > > > Maik Broe
On Wed, 7 Jan 2015 14:49:40 +0800
Tang Chen wrote:
> Memory and CPU hot unplug are both asynchronize procedures.
> When the unplug operation happens, unplug request cb is called first.
> And when ghest OS finished handling unplug, unplug cb will be called
> to do the real removal of device.
>
>
On Fri, Jan 16, 2015 at 07:02:55PM +, Peter Maydell wrote:
> On 16 January 2015 at 16:16, Peter Maydell wrote:
> > I think we're very soon going to need to bite the bullet and
> > make this code have a concept of the current "translation
> > regime", as the ARM ARM terms it...
>
> In fact I t
On Fri, Jan 16, 2015 at 04:16:02PM +, Peter Maydell wrote:
> On 13 January 2015 at 15:48, Andrew Jones wrote:
> > Cleanup XN/PXN handling in get_phys_addr_lpae, and implement all but
> > EL2 support of the following ARMv8 sections
> >
> > D4.5.1 Memory access control: Access permissions for
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