On 10/29/2014 02:41 AM, Yongbok Kim wrote:
> +void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
> + uint32_t ws, uint32_t imm)
> +{
> +wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
> +wr_t *pws = &(env->active_fpu.fpr[ws].wr);
> +wr_t wx, *pwx = &wx;
On 10/29/2014 02:41 AM, Yongbok Kim wrote:
> +case OPC_BNZ_B:
> +case OPC_BNZ_H:
> +case OPC_BNZ_W:
> +case OPC_BNZ_D:
> +gen_check_zero_element(bcond, df, wt);
> +tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
You know gen_check_zero_element returns a boolean.
On 10/29/2014 02:41 AM, Yongbok Kim wrote:
> +static inline void msa_move_v(wr_t *pwd, wr_t *pws)
> +{
> +uint32_t i;
> +
> +for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
> +pwd->d[i] = pws->d[i];
> +}
> +}
Why bother? This is "*pwd = *pws".
r~
On 10/29/2014 02:41 AM, Yongbok Kim wrote:
> +for (i = 0; i < 32; i++) {
> +int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
> +msa_wr_d[i * 2] =
> +tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2]);
> +off = offsetof(CPUMIPSState, ac
On Wed, Nov 05, 2014 at 09:47:47AM +0100, Gerd Hoffmann wrote:
> On Mi, 2014-11-05 at 00:49 +0800, Amos Kong wrote:
> > qemu_input_find_handler() prefers a handler associated with con.
> > But if none exists, it takes any. This patch added a parameter
> > to strictly check console, in case we want
On 2014/11/6 13:01, Amos Kong wrote:
> On Thu, Nov 06, 2014 at 12:51:23PM +0800, Gonglei wrote:
>> On 2014/11/5 23:32, Peter Maydell wrote:
>>
>>> Hi; I've just tagged v2.2.0-rc0 in master, so we're now officially
>>> in hardfreeze, and only accepting bug fixes from here onward.
>>> Mike Roth shou
On Wed, Nov 05, 2014 at 04:29:35PM +0200, Marcel Apfelbaum wrote:
> If the pci bridge enters in error flow as part
> of init process it will only delete the shpc mmio
> subregion but not remove it from the properties list,
> resulting in segmentation fault when the bridge runs
> the exit function.
On Wed, Nov 05, 2014 at 03:43:14PM +0100, Marc-André Lureau wrote:
> It seems "name" is not mandatory, and the following command line (based
> on one generated by current libvirt) will crash qemu at start:
>
> qemu-system-x86_64 \
> -device virtio-serial-pci \
> -device virtserialport,name
On Thu, Nov 06, 2014 at 12:51:23PM +0800, Gonglei wrote:
> On 2014/11/5 23:32, Peter Maydell wrote:
>
> > Hi; I've just tagged v2.2.0-rc0 in master, so we're now officially
> > in hardfreeze, and only accepting bug fixes from here onward.
> > Mike Roth should have the rc0 tarballs out sometime lat
On 2014/11/5 23:32, Peter Maydell wrote:
> Hi; I've just tagged v2.2.0-rc0 in master, so we're now officially
> in hardfreeze, and only accepting bug fixes from here onward.
> Mike Roth should have the rc0 tarballs out sometime later today.
>
> I've updated http://wiki.qemu.org/Planning/2.2 to li
On Wed, Nov 05, 2014 at 12:19:34PM +0100, Eric Blake wrote:
> On 11/05/2014 12:11 PM, Max Reitz wrote:
>
> +err->msg = g_strdup_printf("%s: %s", msg1,
> strerror(abs(os_errno)));
>
> >> I don't, we really should fix the callers.
> >
> > Of course I understand, but this patch do
On 2014/11/5 23:27, Joel Schopp wrote:
>
> On 11/05/2014 03:12 AM, Shannon Zhao wrote:
>> Hi Rémy,
>>
>> On 2014/11/5 16:26, GAUGUEY Rémy 228890 wrote:
>>> Hi Shannon,
>>>
Type of backend bandwith(GBytes/sec)
virtio-net 0.66
vhost-net 1.49
vh
> -Original Message-
> From: Paolo Bonzini [mailto:paolo.bonz...@gmail.com] On Behalf Of Paolo
> Bonzini
> Sent: Wednesday, November 05, 2014 11:55 PM
> To: Michael S. Tsirkin
> Cc: Markus Armbruster; SeokYeon Hwang; qemu-devel@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH] pci: fixed mis
> -Original Message-
> From: SeokYeon Hwang [mailto:syeon.hw...@samsung.com]
> Sent: Wednesday, November 05, 2014 10:13 PM
> To: 'Paolo Bonzini'; 'Max Reitz'; 'qemu-devel@nongnu.org'
> Cc: 'arm...@redhat.com'; 'paolo.bonz...@gmail.com'
> Subject: RE: [PATCH] error: fixed error_set_errno() t
On 2014/11/5 16:43, Eric Auger wrote:
> On 10/27/2014 12:23 PM, Li Liu wrote:
>>
>>
>> On 2014/10/27 17:37, Peter Maydell wrote:
>>> On 25 October 2014 09:24, john.liuli wrote:
To get the interrupt reason to support such VIRTIO_NET_F_STATUS
features I add a new register offset VIRTIO_M
Please review this patch.
Thanks.
> -Original Message-
> From: SeokYeon Hwang [mailto:syeon.hw...@samsung.com]
> Sent: Friday, October 31, 2014 5:04 PM
> To: qemu-devel@nongnu.org
> Cc: aneesh.ku...@linux.vnet.ibm.com; SeokYeon Hwang
> Subject: [PATCH] 9pfs: changed to use event_notifier
Yeah I wanted to get out what I had after all the patches. I am planning
to rebar tomorrow.
Greg
On Nov 5, 2014 5:37 PM, "Peter Maydell" wrote:
> On 5 November 2014 23:22, Greg Bellows wrote:
> > This patch extends arm_excp_unmasked() to use lookup tables for
> determining
> > whether IRQ and
On Wed, Nov 05, 2014 at 07:48:10PM +0200, Michael S. Tsirkin wrote:
> On Wed, Nov 05, 2014 at 05:02:41PM +0800, Hu Tao wrote:
> > Hi,
> >
> > This is v2 of PCI clenaup series. See each patch for the detail.
>
> Thanks for the patches!
>
> Pls note this is all not 2.2 material.
> Pls resubmit aft
> -Original Message-
> From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
> Sent: Thursday, November 06, 2014 2:24 AM
> To: Xu, Quan
> Cc: Stefano Stabellini; qemu-devel@nongnu.org; xen-de...@lists.xen.org
> Subject: RE: [PATCH 2/4] Qemu-Xen-vTPM: Register Xen stubdom vTPM
On 5 November 2014 23:22, Greg Bellows wrote:
> This patch extends arm_excp_unmasked() to use lookup tables for determining
> whether IRQ and FIQ exceptions are masked. The lookup tables are based on the
> ARMv8 and ARMv7 specification physical interrupt masking tables.
>
> If EL3 is using AArch6
From: Fabian Aggeler
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 53b311a..4c36e2e 10064
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure
and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v8 -> v9
- Changed contextidr structure definiti
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
DFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v3 -> v4
- Reverted esr/dfsr back to array-based notation as a union
From: Fabian Aggeler
Adds secure and non-secure bank register suport for TTBCR.
Added new struct to compartmentalize the TCR data and masks. Removed old
tcr/ttbcr data and added a 4 element array of the new structs in cp15. This
allows for one entry per EL. Added a CP register definition for T
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
VBAR has a secure and a non-secure instance, which are mapped to
VBAR_EL1 and VBAR_EL3.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Revert unnecessary CPreg definition ch
From: Fabian Aggeler
Adds secure and non-secure bank register suport for TTBR0 and TTBR1.
Changes include adding secure and non-secure instances of ttbr0 and ttbr1 as
well as a CP register definition for TTBR0_EL3. Added a union containing
both EL based array fields and secure and non-secure fie
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFAR and DFAR have a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Reordered CP register component order
- Removed
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFSR has a secure and a non-secure instance. Adds IFSR32_EL2 definition and
storage.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v8 -> v9
- Added definition for IFSR32_EL2
- Changed ifs
From: Fabian Aggeler
Add checks of SCR AW/FW bits when performing writes of CPSR. These SCR bits
are used to control whether the CPSR masking bits can be adjusted from
non-secure state.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v8 -> v9
- Move cpsr_write mask filtering a
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
DACR has a secure and a non-secure instance. Adds definition for DACR32_EL2.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v8 -> v9
- Added definition for DACR32_EL2
- Changed dacr cp15 f
Added CP register defintions for SDER and SDER32_EL3 as well as cp15.sder for
register storage.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Fixed declaration order of the SDER register components
v7 -> v8
From: Fabian Aggeler
Rename CSSELR (cache size selection register) and add secure
instance (AArch32).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Replaced call to ARM_CP_SECSTATE_TEST with direct access
v7 -> v8
- Fix CSSELR CP regist
From: Fabian Aggeler
Prepare for cp register banking by inserting every cp register twice,
once for secure world and once for non-secure world.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v8 -> v9
- Fixed setting of secure field in add_cpreg_to_hashtable so it uses secstate
From: Fabian Aggeler
Implements SCTLR_EL3 and uses secure/non-secure instance when
needed.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v8 -> v9
- Remove the v8 check in arm_cpu_reset when setting regs[15]
- Fix SCTLR definition component order
v5 -> v6
- Changed _el field
From: Fabian Aggeler
Implements NSACR register with corresponding read/write functions
for ARMv7 and ARMv8.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Removed unused NSACR constants
- Added TODO for trap
Added CP register info entries for the ARMv7 MAIR0/1 secure banks.
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Added endianness support to the MAIR field structure definition.
v5 -> v6
- Changed _el field variants to be array based
---
target-arm/cpu.h| 21 +
Adds a dedicated function and a lookup table for determining the target
exception level of IRQ and FIQ exceptions. The lookup table is taken from the
ARMv7 and ARMv8 specification exception routing tables.
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Fixed target_el_t
From: Fabian Aggeler
Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Fixed declaration order of the MVBAR register
From: Fabian Aggeler
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
--
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
PAR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Cleaned-up ats_write() to only call A32_BANKED_CURRENT_REG_
From: Sergey Fedorov
This patch is based on idea found in patch at
git://github.com/jowinter/qemu-trustzone.git
f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by
Johannes Winter .
The TBFLAG captures the SCR NS secure state at the time when a TB is created so
the correct bank is accessed on system reg
Added additional NS-bit to CPREG hash encoding. Updated hash lookup
locations to specify hash bit currently set to non-secure.
Signed-off-by: Greg Bellows
---
v8 -> v9
- Fixed CP_REG_NS_MASK
- Changed ENCODE_CP_REG argument order so ns follows is64
- Replaced use of CP_REG_NS_MASK with CP_REG_
From: Fabian Aggeler
Define a new ARM CP register info list for the ARMv7 Security Extension
feature. Register that list only for ARM cores with Security Extension/EL3
support. Moving AArch32 SCR into Security Extension register group.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
From: Fabian Aggeler
Prepare ARMCPRegInfo to support specifying two fieldoffsets per
register definition. This will allow us to keep one register
definition for banked registers (different offsets for secure/
non-secure world).
Also added secure state tracking field and flags. This allows for
i
From: Fabian Aggeler
If EL3 is in AArch32 state certain cp registers are banked (secure and
non-secure instance). When reading or writing to coprocessor registers
the following macros can be used.
- A32_BANKED macros are used for choosing the banked register based on provided
input security ar
This patch extends arm_excp_unmasked() to use lookup tables for determining
whether IRQ and FIQ exceptions are masked. The lookup tables are based on the
ARMv8 and ARMv7 specification physical interrupt masking tables.
If EL3 is using AArch64 IRQ/FIQ masking is ignored in all exception levels
oth
Version 9 of the ARM processor security extension (TrustZone) support. This
patchset includes changes to support the processor security extensions
on ARMv7 aarch32 with hooks for later enabling v8 aarch64/32.
Summary of changes from v8 -> v9
- Squashed patch 18 into 17
- Reverted async unmask tab
On 10/23/2014 04:12 AM, Marc Marí wrote:
The allocator in malloc-pc has been extracted, so it can be used in every arch.
This operation showed that both the alloc and free functions can be also
generic.
Because of this, the QGuestAllocator has been removed from is function to wrap
the alloc and
On 05.11.14 13:31, Eric Auger wrote:
> On 11/05/2014 11:59 AM, Alexander Graf wrote:
>>
>>
>> On 31.10.14 15:05, Eric Auger wrote:
>>> vfio-calxeda-xgmac now can be instantiated using the -device option.
>>> The node creation function generates a very basic dt node composed
>>> of the compat, reg
Added definition for IFSR32_EL2 and changed fields to uint64_t in v9.
On 31 October 2014 11:18, Peter Maydell wrote:
> On 30 October 2014 21:28, Greg Bellows wrote:
> > From: Fabian Aggeler
> >
> > When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
> > IFSR has a secure and a n
On 05.11.14 23:00, Samuel Mendoza-Jonas wrote:
> On 05/11/14 19:05, Alexander Graf wrote:
>>
>>
>> On 05.11.14 07:17, Samuel Mendoza-Jonas wrote:
>>> If a TCG guest reboots during a running migration HTAB entries are not
>>> marked dirty, and the destination boots with an invalid HTAB.
>>>
>>> Wh
On 05/11/14 19:05, Alexander Graf wrote:
>
>
> On 05.11.14 07:17, Samuel Mendoza-Jonas wrote:
>> If a TCG guest reboots during a running migration HTAB entries are not
>> marked dirty, and the destination boots with an invalid HTAB.
>>
>> When a reboot occurs reset the state of HTAB migration, an
VCPU topologies, whose number of cores or hyperthreads doesn't equal
a power of two, won't assign all APIC IDs.
We require an APIC ID for every CPU, so the number of wasted APIC IDs
lowers our maximal CPU count.
We exited while printing how high APIC ID of last CPU is, while users
are likely inter
On 05/11/14 18:57, Alexander Graf wrote:
>
>
> On 05.11.14 07:17, Samuel Mendoza-Jonas wrote:
>> If a guest reboots during a running migration, changes to the
>> hash page table are not necessarily updated on the destination.
>> Opening a new file descriptor to the HTAB forces the migration
>> ha
The number of available APIC IDs depends on chosen topology, because
core/smt choices different from a power of two waste some IDs.
Signed-off-by: Radim Krčmář
---
target-i386/cpu.c | 16
target-i386/cpu.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/target-i386/cpu.c
A not-a-bug reported that QEMU fails when cores=6,maxcpus=240,
https://bugzilla.redhat.com/show_bug.cgi?id=1159264
The error message is
qemu-kvm: max_cpus is too large. APIC ID of last CPU is 317
Misconfiguration, but how large can maxcpus be?
There probably aren't many QEMU users with knowledg
The APIC ID topology is made of three elements:
smt, core and pkg id; bit width of first two is determined by the
actual number of hyperthreads/cores and pkg gets the rest.
Basic xAPIC unit tests are included.
Signed-off-by: Radim Krčmář
---
target-i386/topology.h | 13 +
tests/tes
Actually it is possible to make it simpler and avoid the gotos altogether
with the changes I have made using the following conditional:
+/* Use the target EL, current execution state and SCR/HCR settings to
+ * determine whether the corresponding CPSR bit is used to mask the
+ * interr
On Wednesday, November 05, 2014 08:08:06 PM Peter Maydell wrote:
> On 5 November 2014 19:46, Paul Moore wrote:
> > On Wednesday, November 05, 2014 05:08:20 PM Peter Maydell wrote:
> >> On 5 November 2014 16:47, Eduardo Otubo wrote:
> >> > Right now seccomp is breaking the compilation of Qemu on ar
On Wed, 5 Nov 2014, Leon Alrae wrote:
> > qemu-umips-cu1-ex.diff
> > Index: qemu-git-trunk/target-mips/translate.c
> > ===
> > --- qemu-git-trunk.orig/target-mips/translate.c 2014-10-27
> > 04:26:57.0 +
> > +++ qemu-g
On 5 November 2014 19:46, Paul Moore wrote:
> On Wednesday, November 05, 2014 05:08:20 PM Peter Maydell wrote:
>> On 5 November 2014 16:47, Eduardo Otubo wrote:
>> > Right now seccomp is breaking the compilation of Qemu on armv7l due
>> > to libsecomp current lack of support for this arch. This pr
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
first release candidate for the QEMU 2.2 release. This release is meant
for testing purposes and should not be used in a production environment.
http://wiki.qemu.org/download/qemu-2.2.0-rc0.tar.bz2
You can help im
On Wednesday, November 05, 2014 05:08:20 PM Peter Maydell wrote:
> On 5 November 2014 16:47, Eduardo Otubo wrote:
> > Right now seccomp is breaking the compilation of Qemu on armv7l due
> > to libsecomp current lack of support for this arch. This problem is
> > already fixed on libseccomp upstream
On Wed, 5 Nov 2014, Xu, Quan wrote:
> > -Original Message-
> > From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
> > Sent: Wednesday, November 05, 2014 7:01 PM
> > To: Xu, Quan
> > Cc: Stefano Stabellini; qemu-devel@nongnu.org; xen-de...@lists.xen.org
> > Subject: RE: [PATC
On Wed, Nov 05, 2014 at 05:02:41PM +0800, Hu Tao wrote:
> Hi,
>
> This is v2 of PCI clenaup series. See each patch for the detail.
Thanks for the patches!
Pls note this is all not 2.2 material.
Pls resubmit after 2.2 is out.
> changes:
> v2:
> - remove patch 3 from v1 which is incorrect.
>
Hi Eric,
On Fri, 2014-10-31 at 14:05 +, Eric Auger wrote:
> Introduce the VFIODevice struct that is going to be shared by
> VFIOPCIDevice and VFIOPlatformDevice.
>
> Additional fields will be added there later on for review
> convenience.
>
> the group's device_list becomes a list of VFIODev
On Wed, 2014-11-05 at 17:02 +0800, Hu Tao wrote:
> Since the limit parameter is always set to the size of pci device's
> configuration space, and we can determine the size from the type of pci
> device.
>
> Signed-off-by: Hu Tao
> ---
> hw/pci/pci_host.c | 15 +++
> hw/pci/pc
On Tuesday 04 November 2014 09:13:31 Michael Tokarev wrote:
> >> The whole thing needs to be rewritten to use a shell script to create
> >> smb.conf and to call smbd. It's something I wanted to do for very long
> >> time, the only question is where to put this script so a user can
> >> easily cust
On Wed, 2014-11-05 at 17:02 +0800, Hu Tao wrote:
> PCI_HOST_BRIDGE_CONFIG_ADDR and PCI_HOST_BRIDGE_CONFIG_DATA are
> defined in PCI specification, so move them to common place.
>
> Signed-off-by: Hu Tao
> ---
> hw/pci-host/piix.c| 8
> hw/pci-host/prep.c| 6 --
> h
On Wed, 2014-11-05 at 17:02 +0800, Hu Tao wrote:
> This makes code more readable.
>
> Signed-off-by: Hu Tao
> ---
> include/hw/pci/pci.h | 39 ---
> 1 file changed, 20 insertions(+), 19 deletions(-)
>
> diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
On Wed, 2014-11-05 at 17:02 +0800, Hu Tao wrote:
> This makes code more readable.
>
> Signed-off-by: Hu Tao
> ---
> hw/mips/gt64xxx_pci.c | 4 ++--
> hw/pci/pci_host.c | 5 +++--
> include/hw/pci/pci_host.h | 5 +
> 3 files changed, 10 insertions(+), 4 deletions(-)
>
> diff --gi
On 5 November 2014 16:47, Eduardo Otubo wrote:
> Right now seccomp is breaking the compilation of Qemu on armv7l due
> to libsecomp current lack of support for this arch. This problem is
> already fixed on libseccomp upstream but no release date for that is
> scheduled to far. This patch disables
On 11/05/2014 03:12 AM, Shannon Zhao wrote:
> Hi Rémy,
>
> On 2014/11/5 16:26, GAUGUEY Rémy 228890 wrote:
>> Hi Shannon,
>>
>>> Type of backend bandwith(GBytes/sec)
>>> virtio-net 0.66
>>> vhost-net 1.49
>>> vhost-net with irqfd2.01
>>>
>>> Test cmd: ./iperf
> -Original Message-
> From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
> Sent: Wednesday, November 05, 2014 7:01 PM
> To: Xu, Quan
> Cc: Stefano Stabellini; qemu-devel@nongnu.org; xen-de...@lists.xen.org
> Subject: RE: [PATCH 2/4] Qemu-Xen-vTPM: Register Xen stubdom vTP
Right now seccomp is breaking the compilation of Qemu on armv7l due
to libsecomp current lack of support for this arch. This problem is
already fixed on libseccomp upstream but no release date for that is
scheduled to far. This patch disables support for seccomp on armv7l
temporarily until libsecco
** Also affects: virtinst (Ubuntu)
Importance: Undecided
Status: New
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1387881
Title:
qemu fails to recognize full virtualization
Status in QE
I can reproduce this in a VM:
1) boot a clean cloud images (uvt-kvm create lp1387881)
2) apt-get install virtinst
3) sudo virt-install --name juju-bootstrap --ram=2048 --vcpus=1 --hvm
--virt-type=kvm --pxe --boot network,hd --os-variant=ubuntutrusty --graphics
vnc --noautoconsole --os-type=linux
Hi,
[snip--for full message see
https://groups.google.com/d/msg/android-emulator-dev/dltBnUW_HzU/2tSZNLaVzmQJ]
> 5) Relationship with upstream
>
> In an ideal world, we would not need a fork, and all code would live on
> the upstream QEMU git.
>
> In reality, things are different: there is litt
From: Heinz Graalfs
Trigger recalculating sets of file descriptors for the main loop's poll()
in order to make sure a possibly removed FD 0 from the poll() file
descriptor array is re-added. FD 0 is removed from the decriptor array
when the console's can_read() callback returns 0.
Signed-off-by:
From: Thomas Huth
When running "sparse" with the s390x kvm.c code, it complains that
"constant 0x00400f1d4033 is so big it is long" - let's fix this
by appending a proper suffix.
Signed-off-by: Thomas Huth
Reviewed-by: David Hildenbrand
Acked-by: Cornelia Huck
Signed-off-by: Cornelia Huck
From: Frank Blaschka
The second byte of the opcode is encoded in the lowest byte of the ipb
field, not the lowest byte of the ipa field.
Signed-off-by: Frank Blaschka
Signed-off-by: Cornelia Huck
Reviewed-by: Thomas Huth
---
target-s390x/kvm.c |8
1 file changed, 4 insertions(+)
From: Heinz Graalfs
Force recalculation of file descriptor sets for main loop's poll(),
in order to be able to readd a possibly removed input file descriptor
after can_read() returned 0 (zero).
Signed-off-by: Heinz Graalfs
Reviewed-by: David Hildenbrand
Signed-off-by: Cornelia Huck
---
hw/ch
From: Heinz Graalfs
As the SCLP line mode console input length is limited by the available
SCCB buffer space, it might lock up if the input does not fit into the
buffer.
With this patch, characters that don't fit are 'eaten' up to the next
CR/LF and the input line is sent truncated to the guest.
The following changes since commit 6e76d125f244e10676b917208f2a074729820246:
Update version for v2.2.0-rc0 release (2014-11-05 15:21:04 +)
are available in the git repository at:
git://github.com/cohuck/qemu tags/s390x-20141105
for you to fetch changes up to
On 11/5/2014 2:32 AM, Alexander Graf wrote:
>
>
> On 05.11.14 08:13, Aravinda Prasad wrote:
>> This patch adds FWNMI support in qemu for powerKVM
>> guests by handling the ibm,nmi-register rtas call.
>> Whenever OS issues ibm,nmi-register RTAS call, the
>> machine check notification address is sa
* Markus Armbruster (arm...@redhat.com) wrote:
> I'll try to explain all solutions fairly. Isn't easy when you're as
> biased towards one of them as I am. Please bear with me.
>
>
> = The trust boundary between image contents and meta-data =
>
> A disk image consists of image contents and meta
Restore the order of helpers that used to be: unary operations (generic,
then MIPS-specific), binary operations (generic, then MIPS-specific),
compare operations. At one point FMA operations were inserted at a
random place in the file, disregarding the preexisting order, and later
on even more
Remove the `FLOAT_OP' macro, unused since commit
b6d96beda3a6cbf20a2d04a609eff78adebd8859 [Use temporary registers for
the MIPS FPU emulation.].
Signed-off-by: Maciej W. Rozycki
---
qemu-mips-op-helper-float_op.diff
Index: qemu-git-trunk/target-mips/op_helper.c
=
Move the call to `update_fcr31' in `helper_float_cvtw_s' after the
exception flag check, for consistency with the remaining helpers that do
it last too.
Signed-off-by: Maciej W. Rozycki
---
I hope there's no question about this, please apply.
Maciej
qemu-mips-op-helper-cvtw_s-fcr31.diff
In
Signed-off-by: Maciej W. Rozycki
---
qemu-mips-translate-init-format.diff
Index: qemu-git-trunk/target-mips/translate_init.c
===
--- qemu-git-trunk.orig/target-mips/translate_init.c2014-11-02
18:50:58.838990867 +
+++ qemu-git
Signed-off-by: Maciej W. Rozycki
---
qemu-mips-translate-decode-opc-format.diff
Index: qemu-git-trunk/target-mips/translate.c
===
--- qemu-git-trunk.orig/target-mips/translate.c 2014-11-02 18:51:04.838001276
+
+++ qemu-git-trunk/
On Wed, 5 Nov 2014, Leon Alrae wrote:
> The actual microMIPS CPU definition is indeed a worthwile addition -
> thanks. It was on my TODO list to upstream such a CPU but I haven't got
> round to it.
You may still be able to contribute here, by adding microMIPS DSP CPUs.
Regrettably I wasn't abl
Hi; I've just tagged v2.2.0-rc0 in master, so we're now officially
in hardfreeze, and only accepting bug fixes from here onward.
Mike Roth should have the rc0 tarballs out sometime later today.
I've updated http://wiki.qemu.org/Planning/2.2 to list -rc dates;
as usual, one a week, with the hope th
On 04/11/2014 15:41, Maciej W. Rozycki wrote:
> Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit
> and the CP0.Config3.DSP bit for the artificial mips32r5-generic and
> mips64dspr2 processors. They have the DSPr2 ASE enabled in `insn_flags'
> and CPUs that implement that A
On 03/11/2014 19:08, Maciej W. Rozycki wrote:
> Make microMIPS FP branches respect CP0.Status.CU1 and trap with a
> Coprocessor Unusable exception if COP1 has been disabled; also trap if
> no FPU is present at all.
>
> Standard MIPS FP instruction encodings have a more regular structure and
> b
On 04/11/2014 15:39, Maciej W. Rozycki wrote:
> Add the M14K and M14Kc processors from MIPS Technologies that are the
> original implementation of the microMIPS ISA. They are dual instruction
> set processors, implementing both the microMIPS and the standard MIPSr32
> ISA.
>
> These processors
On 04/11/2014 15:37, Maciej W. Rozycki wrote:
> Make the data type used for the CP0.Config4 and CP0.Config5 registers
> and their mask signed, for consistency with the remaining 32-bit CP0
> registers, like CP0.Config0, etc.
>
> Signed-off-by: Maciej W. Rozycki
> ---
> qemu-mips-config-int32_t.
On 03/11/2014 18:36, Maciej W. Rozycki wrote:
> Fix the regression introduced with commit
> 47934d0aadc075b05ce2d9e8a44fa6a46edd1afa [hw: move ISA bridges and
> devices to hw/isa/, configure with default-configs/], by removing
> CONFIG_VT82C686 from configurations that previously did not enable
Maybe, but it is cleaner and works later on down the road when we add EL2
registers that use the same write functions.
I'm fine either way if you feel strongly about it.
On 5 November 2014 09:15, Peter Maydell wrote:
> On 5 November 2014 15:09, Greg Bellows wrote:
> > Ah... I was confused and
On 5 November 2014 09:56, Alexander Graf wrote:
> Hi Peter,
>
> This is my current patch queue for s390. Please pull.
>
> Alex
>
>
> The following changes since commit d5b4dc3b50175f0c34f3cf4b053e123fb37f5aed:
>
> Merge remote-tracking branch 'remotes/afaerber/tags/qom-devices-for-peter'
> int
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