On 10/29/2014 02:41 AM, Yongbok Kim wrote:
> + for (i = 0; i < 32; i++) {
> + int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
> + msa_wr_d[i * 2] =
> + tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2]);
> + off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
> + msa_wr_d[i * 2 + 1] =
> + tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2 +
> 1]);
> + }
> +
You've got to be extremely careful here, since now you have two TCG registers
covering the same data -- the msa register you define here and the fpu_f64
register.
You can get away with this ONLY if you never use both within the same TB. And
I strongly suspect you're not going to do that. You're planning to use msa_wr
for msa insns and fpu_f64 with fpu insns because it "seems right".
r~
