On 04/11/2014 15:39, Maciej W. Rozycki wrote:
> Add the M14K and M14Kc processors from MIPS Technologies that are the
> original implementation of the microMIPS ISA. They are dual instruction
> set processors, implementing both the microMIPS and the standard MIPSr32
> ISA.
>
> These processors correspond to the M4K and 4KEc CPUs respectively,
> except with support for the microMIPS instruction set added, support for
> the MCU ASE added and two extra interrupt lines, making a total of 8
> hardware interrupts plus 2 software interrupts. The remaining parts of
> the microarchitecture, in particular the pipeline, stayed unchanged.
>
> The presence of the microMIPS ASE is is reflected in the configuration
> added. We currently have no support for the MCU ASE, including in
> particular the ACLR, ASET and IRET instructions in either encoding, and
> we have no support for the extra interrupt lines, including bits in
> CP0.Status and CP0.Cause registers, so these features are not marked,
> making our support diverge from real hardware.
>
> Signed-off-by: Sandra Loosemore <san...@codesourcery.com>
> Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
> ---
> Hopefully we'll get the missing features sometime sooner rather than
> later, they should not be difficult to add. Meanwhile having actual
> microMIPS CPUs to select is I think a worthwhile addition. Please
> apply.
>
> Maciej
>
> qemu-mips-m14k.diff
> Index: qemu-git-trunk/target-mips/translate_init.c
> ===================================================================
> --- qemu-git-trunk.orig/target-mips/translate_init.c 2014-11-03
> 19:09:06.000000000 +0000
> +++ qemu-git-trunk/target-mips/translate_init.c 2014-11-04
> 00:33:42.268947442 +0000
> @@ -344,6 +344,47 @@ static const mips_def_t mips_defs[] =
> .mmu_type = MMU_TYPE_R4000,
> },
> {
> + .name = "M14K",
> + .CP0_PRid = 0x00019b00,
> + /* Config1 implemented, fixed mapping MMU,
> + no virtual icache, uncached coherency. */
> + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23)
> |
> + (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
> + .CP0_Config1 = MIPS_CONFIG1,
> + .CP0_Config2 = MIPS_CONFIG2,
> + .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
> + .CP0_LLAddr_rw_bitmask = 0,
> + .CP0_LLAddr_shift = 4,
> + .SYNCI_Step = 32,
> + .CCRes = 2,
> + .CP0_Status_rw_bitmask = 0x1258FF17,
> + .SEGBITS = 32,
> + .PABITS = 32,
> + .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
> + .mmu_type = MMU_TYPE_FMT,
> + },
> + {
> + .name = "M14Kc",
> + /* This is the TLB-based MMU core. */
> + .CP0_PRid = 0x00019c00,
> + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
> + (MMU_TYPE_R4000 << CP0C0_MT),
> + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
> + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
> + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
> + .CP0_Config2 = MIPS_CONFIG2,
> + .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
> + .CP0_LLAddr_rw_bitmask = 0,
> + .CP0_LLAddr_shift = 4,
> + .SYNCI_Step = 32,
> + .CCRes = 2,
> + .CP0_Status_rw_bitmask = 0x1278FF17,
> + .SEGBITS = 32,
> + .PABITS = 32,
> + .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
> + .mmu_type = MMU_TYPE_R4000,
> + },
> + {
> /* A generic CPU providing MIPS32 Release 5 features.
> FIXME: Eventually this should be replaced by a real CPU model. */
> .name = "mips32r5-generic",
>
The actual microMIPS CPU definition is indeed a worthwile addition -
thanks. It was on my TODO list to upstream such a CPU but I haven't got
round to it.
Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Regards,
Leon
