[Mesa-dev] [PATCH 2/2] r600g: use default action for fdiv/rcp opcode

--- src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c index 00c068d..2521582 100644 --- a/src/gallium/drivers/radeo

[Mesa-dev] [PATCH 1/2] gallivm: Have a default emit function for min/max opcode

--- src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c | 31 ++ 1 file changed, 31 insertions(+) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c index ff21879..070945c 100644 --- a/src/gallium/auxiliary/gall

[Mesa-dev] [PATCH 2/2] r600g: use default action for min/max opcode in tgsi to llvm

--- src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 4 1 file changed, 4 deletions(-) diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c index 2521582..9cb0e9a 100644 --- a/src/gallium/drivers/radeon/radeon_setup_tgsi

[Mesa-dev] [PATCH] gallivm: have a default emit function for fdiv/rcp

--- src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c | 25 ++ 1 file changed, 25 insertions(+) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c index 17f288f..cd57fae 100644 --- a/src/gallium/auxiliary/gall

[Mesa-dev] [PATCH] gallivm: Have a default emit function for min/max opcode

--- src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c | 29 ++ 1 file changed, 29 insertions(+) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c index cd57fae..cc4bd2e 100644 --- a/src/gallium/auxiliary/gall

[Mesa-dev] [PATCH 1/2] radeon/llvm: replace int_AMDGPU_rcp by fdiv (1.0, x) in RECIP pattern

--- lib/Target/AMDGPU/R600Instructions.td | 4 ++-- lib/Target/AMDGPU/SIInstructions.td | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/Target/AMDGPU/R600Instructions.td b/lib/Target/AMDGPU/R600Instructions.td index 9259680..d75c32e 100644 --- a/lib/Target/AMDGPU/R600

[Mesa-dev] [PATCH 2/2] radeon/llvm: add a pattern for min/max

--- lib/Target/AMDGPU/R600ISelLowering.cpp | 47 lib/Target/AMDGPU/R600Instructions.td | 12 +++-- lib/Target/AMDGPU/SIISelLowering.cpp | 49 ++ lib/Target/AMDGPU/SIInstructions.td| 10 +-- 4 files changed, 114 inserti

[Mesa-dev] [PATCH] radeon/llvm: add a pattern for min/max

--- lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 53 lib/Target/AMDGPU/AMDGPUISelLowering.h | 1 + lib/Target/AMDGPU/R600ISelLowering.cpp | 5 +++ lib/Target/AMDGPU/SIISelLowering.cpp | 6 4 files changed, 65 insertions(+) diff --git a/lib/Target/AMD

[Mesa-dev] [PATCH] radeon/llvm: add a pattern for min/max

--- lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 58 lib/Target/AMDGPU/AMDGPUISelLowering.h | 1 + lib/Target/AMDGPU/R600ISelLowering.cpp | 6 lib/Target/AMDGPU/SIISelLowering.cpp | 6 4 files changed, 71 insertions(+) diff --git a/lib/Target/AM

Re: [Mesa-dev] Mesa (master): r600g: Use default mul/mad function for tgsi-to-llvm

telling if we have a glsl or an opencl shader. Vincent - Mail original - > De : Tom Stellard > À : Michel Dänzer > Cc : Vincent Lejeune ; mesa-dev@lists.freedesktop.org > Envoyé le : Jeudi 6 décembre 2012 18h05 > Objet : Re: [Mesa-dev] Mesa (master): r600g: Use default m

[Mesa-dev] [PATCH 1/3] radeon/llvm: Split Word0 and Word1 in Export instruction

--- .../AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp | 4 +- lib/Target/AMDGPU/R600ISelLowering.cpp | 6 +- lib/Target/AMDGPU/R600Instructions.td | 99 -- 3 files changed, 60 insertions(+), 49 deletions(-) diff --git a/lib/Target/AMDGPU/MCTargetDes

[Mesa-dev] [PATCH 2/3] radeon/llvm: Add a field for Export node (compMask) and factorise code handling store intrinsic

--- lib/Target/AMDGPU/R600ISelLowering.cpp | 91 -- lib/Target/AMDGPU/R600Instructions.td | 9 ++-- 2 files changed, 58 insertions(+), 42 deletions(-) diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp index 7787599..1b6

[Mesa-dev] [PATCH 3/3] radeon/llvm: Add an intrinsic to handle stream outputs.

--- .../AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp | 2 + lib/Target/AMDGPU/R600ISelLowering.cpp | 31 +++ lib/Target/AMDGPU/R600Instructions.td | 65 ++ lib/Target/AMDGPU/R600Intrinsics.td| 2 + lib/Target/AMDGPU/R600Machi

[Mesa-dev] [PATCH] r600g: tgsi to llvm emits stream output intrinsics.

--- src/gallium/drivers/r600/eg_asm.c| 2 ++ src/gallium/drivers/r600/r600_asm.c | 2 ++ src/gallium/drivers/r600/r600_llvm.c | 21 + src/gallium/drivers/r600/r600_shader.c | 3 ++- src/gallium/drivers/radeon/radeon_llvm.h | 1 + 5 files changed, 28 inser

[Mesa-dev] [PATCH 1/2] radeon/llvm: add an intrinsic converting clipvertex to clipdistance

--- lib/Target/AMDGPU/R600ISelLowering.cpp | 21 - lib/Target/AMDGPU/R600Instructions.td | 12 lib/Target/AMDGPU/R600Intrinsics.td| 2 ++ lib/Target/AMDGPU/R600RegisterInfo.td | 21 - 4 files changed, 54 insertions(+), 2 deletions(-) dif

[Mesa-dev] [PATCH 2/2] radeon/llvm: add store.vertex.{position, param} intrinsics

--- lib/Target/AMDGPU/R600ISelLowering.cpp| 51 +++ lib/Target/AMDGPU/R600Instructions.td | 5 +++ lib/Target/AMDGPU/R600Intrinsics.td | 4 +++ lib/Target/AMDGPU/R600MachineFunctionInfo.cpp | 1 + lib/Target/AMDGPU/R600MachineFunctionInfo.h |

[Mesa-dev] [PATCH 1/2] r600g: tgsi to llvm emits stream output intrinsics.

--- src/gallium/drivers/r600/eg_asm.c| 2 ++ src/gallium/drivers/r600/r600_asm.c | 2 ++ src/gallium/drivers/r600/r600_llvm.c | 20 src/gallium/drivers/r600/r600_shader.c | 3 ++- src/gallium/drivers/radeon/radeon_llvm.h | 1 + 5 files changed, 27 insert

[Mesa-dev] [PATCH 2/2] r600g: tgsi to llvm emits vertex export

--- src/gallium/drivers/r600/r600_llvm.c | 119 --- src/gallium/drivers/r600/r600_shader.c | 11 ++- src/gallium/drivers/radeon/radeon_llvm.h | 1 + 3 files changed, 120 insertions(+), 11 deletions(-) diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/ga

[Mesa-dev] [PATCH 1/2] radeon/llvm: support for multiple const buffer

--- lib/Target/AMDGPU/AMDGPUIntrinsics.td | 2 +- .../AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp | 26 +++- lib/Target/AMDGPU/R600ISelLowering.cpp | 57 +++- lib/Target/AMDGPU/R600Instructions.td | 4 +- lib/Target/AMDGPU/R600RegisterInfo.td

[Mesa-dev] [PATCH 2/2] radeon/llvm: add store.vertex.{position, param} intrinsics

--- lib/Target/AMDGPU/R600ISelLowering.cpp| 51 +++ lib/Target/AMDGPU/R600Instructions.td | 5 +++ lib/Target/AMDGPU/R600Intrinsics.td | 4 +++ lib/Target/AMDGPU/R600MachineFunctionInfo.cpp | 1 + lib/Target/AMDGPU/R600MachineFunctionInfo.h |

[Mesa-dev] [PATCH 1/2] r600g: tgsi to llvm emits kcache bank

--- src/gallium/drivers/r600/r600_llvm.c | 6 -- src/gallium/drivers/r600/r600_shader.c | 4 +++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/gallium/drivers/r600/r600_llvm.c index 79f6cf0..5efde2d 100644 --- a/src/gallium/driver

[Mesa-dev] [PATCH 2/2] r600g: tgsi to llvm emits vertex export

--- src/gallium/drivers/r600/r600_llvm.c | 126 --- src/gallium/drivers/r600/r600_shader.c | 11 ++- src/gallium/drivers/radeon/radeon_llvm.h | 1 + 3 files changed, 127 insertions(+), 11 deletions(-) diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/ga

[Mesa-dev] [PATCH] r600g: tgsi to llvm emits store.swizzle intrinsic for vs/fs output

--- src/gallium/drivers/r600/r600_llvm.c | 197 ++- src/gallium/drivers/r600/r600_shader.c | 6 +- src/gallium/drivers/radeon/radeon_llvm.h | 1 + 3 files changed, 147 insertions(+), 57 deletions(-) diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/gal

[Mesa-dev] [PATCH] radeon/llvm: add a llvm.R600.store.swizzle intrinsics

This intrinsic is translated to ALLOC_EXPORT_WORD1_SWIZ, hence its name. It is used to store vs/fs outputs --- lib/Target/AMDGPU/R600ISelLowering.cpp | 23 +-- lib/Target/AMDGPU/R600Instructions.td | 11 +++ lib/Target/AMDGPU/R600Intrinsics.td| 2 ++ 3 files chang

[Mesa-dev] [PATCH] [WIP]radeon/llvm: Loads from globaladdr ptr turned into const buf read

--- lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 1 + lib/Target/AMDGPU/AMDGPUISelLowering.h | 1 + lib/Target/AMDGPU/AMDGPUMCInstLower.cpp | 6 lib/Target/AMDGPU/AMDILISelDAGToDAG.cpp | 49 - lib/Target/AMDGPU/R600ISelLowering.cpp | 61 +

[Mesa-dev] [PATCH] r600g[WIP]: tgsi to llvm emits pointer to globaladdr load for constant buffer data

--- src/gallium/drivers/r600/r600_llvm.c | 23 +-- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/gallium/drivers/r600/r600_llvm.c index 22f5f11..2b885c9 100644 --- a/src/gallium/drivers/r600/r600_llvm.c +++ b/src/gal

[Mesa-dev] [PATCH] R600: rework handling of the constants

From: Vadim Girlin Remove Cxxx registers, add new special register - "ALU_CONST" and new operand for each alu src - "sel". ALU_CONST is used to designate that the new operand contains the value to override src.sel, src.kc_bank, src.chan for constants in the driver. v2[Vince

[Mesa-dev] [PATCH] r600g: rework handling of the constants

>From Vadim Girlin patch --- src/gallium/drivers/r600/r600_llvm.c | 4 ++-- src/gallium/drivers/r600/r600_shader.c | 35 +- 2 files changed, 28 insertions(+), 11 deletions(-) diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/gallium/drivers/r600/r600_llvm

[Mesa-dev] [PATCH] r600g: rework handling of the constants

>From Vadim Girlin patch --- src/gallium/drivers/r600/r600_llvm.c | 19 ++ src/gallium/drivers/r600/r600_shader.c | 35 +- 2 files changed, 37 insertions(+), 17 deletions(-) diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/gallium/drivers/

[Mesa-dev] [PATCH] r600g: rework handling of the constants

>From Vadim Girlin patch --- src/gallium/drivers/r600/r600_llvm.c | 19 ++ src/gallium/drivers/r600/r600_shader.c | 35 +- 2 files changed, 37 insertions(+), 17 deletions(-) diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/gallium/drivers/

[Mesa-dev] [PATCH 1/4] R600: Factorise VTX_WORD0 and VTX_WORD1 in tblgen def

--- lib/Target/AMDGPU/R600Instructions.td | 110 -- 1 file changed, 65 insertions(+), 45 deletions(-) diff --git a/lib/Target/AMDGPU/R600Instructions.td b/lib/Target/AMDGPU/R600Instructions.td index 66c9249..7921fe1e 100644 --- a/lib/Target/AMDGPU/R600Instructions

[Mesa-dev] [PATCH 2/4] R600: Add a CONST_ADDRESS node to model constant buf read

--- lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 1 + lib/Target/AMDGPU/AMDGPUISelLowering.h | 1 + lib/Target/AMDGPU/R600Instructions.td| 11 ++- 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/lib/Target/AMDGPU/AMDGPUISelLo

[Mesa-dev] [PATCH 3/4] R600: rework handling of the constants

From: Vadim Girlin Remove Cxxx registers, add new special register - "ALU_CONST" and new operand for each alu src - "sel". ALU_CONST is used to designate that the new operand contains the value to override src.sel, src.kc_bank, src.chan for constants in the driver. v2[Vince

[Mesa-dev] [PATCH 4/4] R600: Fold CONST_ADDRESS when possible

--- lib/Target/AMDGPU/AMDILISelDAGToDAG.cpp | 27 ++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/lib/Target/AMDGPU/AMDILISelDAGToDAG.cpp b/lib/Target/AMDGPU/AMDILISelDAGToDAG.cpp index 6f156df..6e07734 100644 --- a/lib/Target/AMDGPU/AMDILISelDAGToDAG.cpp

[Mesa-dev] [PATCH 1/2] r600g: rework handling of the constants

>From Vadim Girlin patch --- src/gallium/drivers/r600/r600_llvm.c | 27 +++ src/gallium/drivers/r600/r600_shader.c | 39 -- .../drivers/radeon/radeon_setup_tgsi_llvm.c| 4 +++ 3 files changed, 54 insertions(+), 16 deletions(-) dif

[Mesa-dev] [PATCH 2/2] r600g: tgsi to llvm emits store.swizzle intrinsic for vs/fs output

--- src/gallium/drivers/r600/r600_llvm.c | 194 ++- src/gallium/drivers/r600/r600_shader.c | 6 +- src/gallium/drivers/radeon/radeon_llvm.h | 1 + 3 files changed, 144 insertions(+), 57 deletions(-) diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/gal

[Mesa-dev] [PATCH 2/5] R600: Factorise VTX_WORD0 and VTX_WORD1 in tblgen def

--- lib/Target/R600/R600Instructions.td | 110 +--- 1 file changed, 65 insertions(+), 45 deletions(-) diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td index c3539ab..112f769 100644 --- a/lib/Target/R600/R600Instructions.td +++

[Mesa-dev] [PATCH 1/5] R600: rework handling of the constants

From: Vadim Girlin Remove Cxxx registers, add new special register - "ALU_CONST" and new operand for each alu src - "sel". ALU_CONST is used to designate that the new operand contains the value to override src.sel, src.kc_bank, src.chan for constants in the driver. --- lib/Target/R600/AMDILISelD

[Mesa-dev] [PATCH 4/5] R600: use pointers for constants

--- lib/Target/R600/AMDGPU.h | 1 + lib/Target/R600/AMDGPUTargetMachine.cpp| 1 + lib/Target/R600/AMDIL.h| 19 +++- lib/Target/R600/AMDILISelDAGToDAG.cpp | 104 + lib/Target/R600/MCTargetDesc/R6

[Mesa-dev] [PATCH 5/5] R600: Fold CONST_ADDRESS when possible

--- lib/Target/R600/AMDILISelDAGToDAG.cpp | 61 ++- lib/Target/R600/R600ISelLowering.cpp | 14 +++- 2 files changed, 73 insertions(+), 2 deletions(-) diff --git a/lib/Target/R600/AMDILISelDAGToDAG.cpp b/lib/Target/R600/AMDILISelDAGToDAG.cpp index 8fbf153..567

[Mesa-dev] [PATCH 1/3] r600g/llvm: rework handling of the constants

From: Vadim Girlin Pack kc_bank, const_index and chan into the load.const operand, unpack them in r600_alu_from_byte_stream and use to override sel, kc_bank and chan for the constants. Expected operand value is (((512 + (kc_bank << 12) + const_index) << 2) + chan). --- src/gallium/drivers/r600/

[Mesa-dev] [PATCH 1/2] r600g: tgsi to llvm emits stream output intrinsics.

--- src/gallium/drivers/r600/eg_asm.c| 2 ++ src/gallium/drivers/r600/r600_asm.c | 2 ++ src/gallium/drivers/r600/r600_llvm.c | 20 src/gallium/drivers/r600/r600_shader.c | 3 ++- src/gallium/drivers/radeon/radeon_llvm.h | 1 + 5 files changed, 27 insert

[Mesa-dev] [PATCH 2/3] r600g/llvm:translate ARL opcode to a simple cast

--- src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c index d390f92..acbd387 100644 --- a/src/gallium/dri

[Mesa-dev] [PATCH 2/2] r600g: tgsi to llvm emits store.swizzle intrinsic for vs/fs output

--- src/gallium/drivers/r600/r600_llvm.c | 194 ++- src/gallium/drivers/r600/r600_shader.c | 6 +- src/gallium/drivers/radeon/radeon_llvm.h | 1 + 3 files changed, 144 insertions(+), 57 deletions(-) diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/gal

[Mesa-dev] [PATCH 3/3] r600g/llvm: tgsi to llvm now emits pointers for constants

--- src/gallium/drivers/r600/r600_llvm.c | 24 +- src/gallium/drivers/r600/r600_shader.c | 7 +-- .../drivers/radeon/radeon_setup_tgsi_llvm.c| 4 3 files changed, 23 insertions(+), 12 deletions(-) diff --git a/src/gallium/drivers/r6

[Mesa-dev] [PATCH 1/2] radeon/llvm: simplify stream outputs intrinsic

--- lib/Target/R600/R600ISelLowering.cpp| 32 - lib/Target/R600/R600Instructions.td | 24 +++--- lib/Target/R600/R600Intrinsics.td | 2 +- lib/Target/R600/R600MachineFunctionInfo.cpp | 1 - lib/Target/R600/R600MachineFunctionI

[Mesa-dev] [PATCH 2/2] radeon/llvm: add a llvm.R600.store.swizzle intrinsics

This intrinsic is translated to ALLOC_EXPORT_WORD1_SWIZ, hence its name. It is used to store vs/fs outputs --- lib/Target/R600/R600ISelLowering.cpp | 23 +-- lib/Target/R600/R600Instructions.td | 11 +++ lib/Target/R600/R600Intrinsics.td| 2 ++ 3 files changed, 34

[Mesa-dev] [PATCH 1/2] r600g: tgsi to llvm emits stream output intrinsics.

--- src/gallium/drivers/r600/eg_asm.c| 2 ++ src/gallium/drivers/r600/r600_asm.c | 2 ++ src/gallium/drivers/r600/r600_llvm.c | 32 src/gallium/drivers/r600/r600_shader.c | 3 ++- src/gallium/drivers/radeon/radeon_llvm.h | 1 + 5 files change

[Mesa-dev] [PATCH 2/2] r600g: tgsi to llvm emits store.swizzle intrinsic for vs/fs output

--- src/gallium/drivers/r600/r600_llvm.c | 197 ++- src/gallium/drivers/r600/r600_shader.c | 6 +- src/gallium/drivers/radeon/radeon_llvm.h | 1 + 3 files changed, 146 insertions(+), 58 deletions(-) diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/gal

[Mesa-dev] [PATCH 1/2] R600: Consider bitcast when folding const_address node.

--- lib/Target/R600/AMDILISelDAGToDAG.cpp | 3 +++ lib/Target/R600/R600ISelLowering.cpp | 6 ++ 2 files changed, 9 insertions(+) diff --git a/lib/Target/R600/AMDILISelDAGToDAG.cpp b/lib/Target/R600/AMDILISelDAGToDAG.cpp index 567b3e2..ece26ef 100644 --- a/lib/Target/R600/AMDILISelDAGToDAG.c

[Mesa-dev] [PATCH 2/2] R600: Fold clamp, neg, abs

--- lib/Target/R600/AMDILISelDAGToDAG.cpp | 51 --- 1 file changed, 48 insertions(+), 3 deletions(-) diff --git a/lib/Target/R600/AMDILISelDAGToDAG.cpp b/lib/Target/R600/AMDILISelDAGToDAG.cpp index ece26ef..84223f6 100644 --- a/lib/Target/R600/AMDILISelDAGToDAG.cp

[Mesa-dev] [PATCH] R600: Consider bitcast when folding const_address node.

--- lib/Target/R600/AMDILISelDAGToDAG.cpp | 3 +++ lib/Target/R600/R600ISelLowering.cpp | 8 2 files changed, 11 insertions(+) diff --git a/lib/Target/R600/AMDILISelDAGToDAG.cpp b/lib/Target/R600/AMDILISelDAGToDAG.cpp index 567b3e2..ece26ef 100644 --- a/lib/Target/R600/AMDILISelDAGToDA

[Mesa-dev] [PATCH] R600: Fold remaining CONST_COPY after expand pseudo inst

--- lib/Target/R600/AMDGPUTargetMachine.cpp | 2 +- lib/Target/R600/R600LowerConstCopy.cpp | 162 +--- 2 files changed, 152 insertions(+), 12 deletions(-) diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp index 7b069e7..

Re: [Mesa-dev] [PATCH] glsl_to_tgsi: indirect array information

- Mail original - > De : Vadim Girlin > À : Christoph Bumiller > Cc : mesa-dev@lists.freedesktop.org > Envoyé le : Mercredi 23 janvier 2013 0h44 > Objet : Re: [Mesa-dev] [PATCH] glsl_to_tgsi: indirect array information > > On 01/22/2013 10:59 PM, Christoph Bumiller wrote: >> On 21.01.

Re: [Mesa-dev] [PATCH] glsl_to_tgsi: indirect array information

- Mail original - > De : Vadim Girlin > À : Vincent Lejeune > Cc : "mesa-dev@lists.freedesktop.org" > Envoyé le : Mercredi 23 janvier 2013 1h21 > Objet : Re: [Mesa-dev] [PATCH] glsl_to_tgsi: indirect array information > > On 01/23/2013

[Mesa-dev] [PATCH 1/2] R600: Fold remaining CONST_COPY after expand pseudo inst

v2:fix a bug with write masked inst --- lib/Target/R600/AMDGPUTargetMachine.cpp | 2 +- lib/Target/R600/R600LowerConstCopy.cpp | 164 +--- 2 files changed, 154 insertions(+), 12 deletions(-) diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMD

[Mesa-dev] [PATCH 2/2] R600: Do not fold vector inst

--- lib/Target/R600/AMDILISelDAGToDAG.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Target/R600/AMDILISelDAGToDAG.cpp b/lib/Target/R600/AMDILISelDAGToDAG.cpp index 84223f6..2cc4724 100644 --- a/lib/Target/R600/AMDILISelDAGToDAG.cpp +++ b/lib/Target/R600/AMDILISelDAGT

[Mesa-dev] [PATCH] R600: improve inputs/interpolation handling

reuse those regs, lowering reg pressure. Signed-off-by: Vadim Girlin v2[Vincent Lejeune]: Rebased against current llvm master --- lib/Target/R600/AMDGPUISelLowering.cpp | 2 - lib/Target/R600/AMDGPUISelLowering.h| 2 - lib/Target/R600/R600ExpandSpecialInstrs.cpp

[Mesa-dev] [PATCH] r600g: improve inputs/interpolation handling with llvm backend

From: Vadim Girlin Get rid of special handling for reserved regs. Use one intrinsic for all kinds of interpolation. Signed-off-by: Vadim Girlin v2[Vincent Lejeune]: Rebased against current master --- src/gallium/drivers/r600/r600_llvm.c | 195 +++ src/gallium

[Mesa-dev] [PATCH] R600: Do not fold vector inst

--- lib/Target/R600/AMDILISelDAGToDAG.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/Target/R600/AMDILISelDAGToDAG.cpp b/lib/Target/R600/AMDILISelDAGToDAG.cpp index 84223f6..b08d39f 100644 --- a/lib/Target/R600/AMDILISelDAGToDAG.cpp +++ b/lib/Target/R600/AMDILISelDA

[Mesa-dev] [PATCH] R600: Fold remaining CONST_COPY after expand pseudo inst

--- lib/Target/R600/AMDGPUTargetMachine.cpp | 2 +- lib/Target/R600/R600LowerConstCopy.cpp | 167 +--- 2 files changed, 157 insertions(+), 12 deletions(-) diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp index 7b069e7..

[Mesa-dev] [PATCH] r600g/llvm: Fix for bug 59588 (llvm rv780 etqw gpu lock

--- src/gallium/drivers/r600/r600_llvm.c | 38 ++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/gallium/drivers/r600/r600_llvm.c index 32b8e56..d28182b 100644 --- a/src/gallium/drivers/r600/r600_llvm.c +

[Mesa-dev] [PATCH] R600: Make store_dummy intrinsic more general by passing export type

--- lib/Target/R600/R600Instructions.td | 9 +++-- lib/Target/R600/R600Intrinsics.td | 4 ++-- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td index 13293b6..3537906 100644 --- a/lib/Target/R600/R600Ins

[Mesa-dev] [PATCH] r600g/llvm: Add dummy export for vs output

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=59588 --- src/gallium/drivers/r600/r600_llvm.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/gallium/drivers/r600/r600_llvm.c index 32b8e56..913dccc 100644

[Mesa-dev] [PATCH] R600: Fold remaining CONST_COPY after expand pseudo inst

--- lib/Target/R600/AMDGPUTargetMachine.cpp | 2 +- lib/Target/R600/R600LowerConstCopy.cpp | 170 +--- 2 files changed, 160 insertions(+), 12 deletions(-) diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp index 7b069e7..

[Mesa-dev] [PATCH 1/4] R600: Use MULADD_IEEE instruction for mad pattern

--- lib/Target/R600/AMDGPUISelLowering.cpp | 6 +++--- lib/Target/R600/AMDILISelLowering.cpp | 3 ++- lib/Target/R600/R600Instructions.td| 8 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.c

[Mesa-dev] [PATCH 2/4] R600: Do not fold modifier/litterals in vector inst

This fixes a couple of regressions on (probably not just) cayman --- lib/Target/R600/AMDILISelDAGToDAG.cpp | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/lib/Target/R600/AMDILISelDAGToDAG.cpp b/lib/Target/R600/AMDILISelDAGToDAG.cpp index 84223f6..7fc3a2f 100644 --- a/l

[Mesa-dev] [PATCH 3/4] R600: Fold zero/one in export instructions

--- lib/Target/R600/R600ISelLowering.cpp | 111 --- lib/Target/R600/R600Instructions.td | 20 ++- lib/Target/R600/R600Intrinsics.td| 3 - 3 files changed, 55 insertions(+), 79 deletions(-) diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/

[Mesa-dev] [PATCH 4/4] R600: Export instructions are no longer terminator

This allows MachineInstScheduler to reorder them, and thus make scheduling more efficient. --- lib/Target/R600/R600Instructions.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td index 3c043aa..82a63

[Mesa-dev] [PATCH] R600: Do not fold modifier/litterals in vector inst

This fixes a couple of regressions on (probably not just) cayman --- lib/Target/R600/AMDILISelDAGToDAG.cpp | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/lib/Target/R600/AMDILISelDAGToDAG.cpp b/lib/Target/R600/AMDILISelDAGToDAG.cpp index 84223f6..7fc3a2f 100644 --- a/l

[Mesa-dev] [PATCH] R600: Use MULADD_IEEE instruction for mad pattern

--- lib/Target/R600/AMDGPUISelLowering.cpp | 10 +++--- lib/Target/R600/AMDGPUISelLowering.h | 1 - lib/Target/R600/AMDILISelLowering.cpp | 3 ++- lib/Target/R600/AMDILInstrInfo.td | 1 - lib/Target/R600/AMDILIntrinsics.td | 10 -- lib/Target/R600/R600Instructions.td

[Mesa-dev] [PATCH] R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern

--- lib/Target/R600/AMDGPUISelLowering.cpp | 10 +++--- lib/Target/R600/AMDGPUISelLowering.h | 1 - lib/Target/R600/AMDILISelLowering.cpp | 3 ++- lib/Target/R600/AMDILInstrInfo.td | 1 - lib/Target/R600/AMDILIntrinsics.td | 10 -- lib/Target/R600/R600Instructions.td

[Mesa-dev] [PATCH 1/2] R600/SI: Turn BUILD_VECTOR into Reg_Sequence

--- lib/Target/R600/AMDILISelDAGToDAG.cpp | 24 1 file changed, 24 insertions(+) diff --git a/lib/Target/R600/AMDILISelDAGToDAG.cpp b/lib/Target/R600/AMDILISelDAGToDAG.cpp index b125ba8..2f34fe3 100644 --- a/lib/Target/R600/AMDILISelDAGToDAG.cpp +++ b/lib/Target/R600/AMD

[Mesa-dev] [PATCH 2/2] R600: initial scheduler code

single VLIW group). Also it tries to reduce clause switching by grouping instruction of the same kind (ALU/FETCH/CF) together. Vincent Lejeune: - Support for VLIW4 Slot assignement - Recomputation of ScheduleDAG to get more parallelism opportunities --- lib/Target/R600/AMDGPUTargetMachine.cpp | 17

Re: [Mesa-dev] [PATCH] R600: Fix regression with shadow array sampler on pre-SI GPUs.

- Mail original - > De : Michel Dänzer > À : Vincent Lejeune > Cc : mesa-dev@lists.freedesktop.org > Envoyé le : Lundi 11 février 2013 17h53 > Objet : [PATCH] R600: Fix regression with shadow array sampler on pre-SI GPUs. > > From: Michel Dänzer >

[Mesa-dev] [PATCH] R600/SI: Do not fold single instruction with more that 3 kcache read

It fixes around 100 tfb piglit tests and 16 glean tests. NOTE: This is a candidate for the Mesa stable branch. --- lib/Target/R600/AMDILISelDAGToDAG.cpp | 2 ++ lib/Target/R600/R600LowerConstCopy.cpp | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/Target/R600/AMDILISelD

[Mesa-dev] Various Patches

Hi, these are previous patches I reformatted to fix my git user name. Regards, Vincent ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/3] mesa : move bindbuffer{base, range} from transformfeedback.c

BindBuffer* functions are part of tfb extension. They are however used by others extensions such as uniform buffer object. This patch moves the BindBuffer* definition to to bufferobj.c where it acts as a dispatcher calling original tfb function ; BindBuffer* functions can be used by

[Mesa-dev] [PATCH 2/3] gallium: rework some utilities functions to support 2d indexing

This patch adds a 2d ureg_src constructor, and add a field in st_src_reg inside glsl_to_tgsi that hold potential 2d index. 2d indexing is required at least for uniform buffer object support --- src/gallium/auxiliary/tgsi/tgsi_ureg.h | 12 src/mesa/state_tracker/st_gl

[Mesa-dev] [PATCH 3/3] gallium: fix function description

ureg_DECL_constant2D does not return anything. --- src/gallium/auxiliary/tgsi/tgsi_ureg.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c b/src/gallium/auxiliary/tgsi/tgsi_ureg.c index cada435..5d8dbba 100644 --- a/src/gallium/

[Mesa-dev] [PATCH] mesa : move bindbuffer{base, range} from transformfeedback.c

BindBuffer* functions are part of tfb extension. They are however used by others extensions such as uniform buffer object. This patch moves the BindBuffer* definition to to bufferobj.c where it acts as a dispatcher calling original tfb function ; BindBuffer* functions can be used by

[Mesa-dev] [PATCH] mesa: initial data structures for Uniform Buffer Objects

v2:Big cleanup of data structures used --- src/mesa/main/config.h|4 ++ src/mesa/main/mtypes.h| 18 src/mesa/main/shaderobj.c | 29 - src/mesa/program/prog_parameter.h |1 + src/mesa/program/prog_uniform.c |4 ++ src/mesa/pr

[Mesa-dev] UBO support update, working on some demo

Hi, Here are an updated set of patches adding UBO support to Mesa. It still work in progress, however I got some demo working on gallium (namely blinking-teapot submitted to mesa-demos via another patch). However not every gallium works, nouveau and softpipe does but llvmpipe crashes (seems not t

[Mesa-dev] [PATCH 1/9] glapi: Add Uniform Buffer Object API

v2: Fix a typo spotted by Eric Anholt. --- src/mapi/glapi/gen/ARB_Uniform_Buffer_Object.xml | 115 ++ src/mapi/glapi/gen/Makefile |1 + src/mapi/glapi/gen/gl_API.xml|2 + 3 files changed, 118 insertions(+), 0 deletions(-) cr

[Mesa-dev] [PATCH 3/9] mesa : advertise GL_ARB_Uniform_Buffer_Object extension

--- src/glsl/glsl_parser_extras.cpp |1 + src/glsl/glsl_parser_extras.h |2 ++ src/mesa/main/mfeatures.h |1 + 3 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp index 0b4ccac..71b4c5c 100644 --- a/sr

[Mesa-dev] [PATCH 4/9] mesa: Uniform Buffer Objects data structures

v2:Big cleanup of data structures used v3:Data structures moved to mtypes.h --- src/mesa/main/config.h|4 ++ src/mesa/main/mtypes.h| 109 + src/mesa/main/shaderobj.c | 25 - src/mesa/program/prog_parameter.h |

[Mesa-dev] [PATCH 5/9] glsl: change IR to add UBO information

--- src/glsl/ir.cpp|1 + src/glsl/ir.h |6 ++ src/glsl/ir_clone.cpp |1 + src/glsl/opt_dead_code.cpp |6 ++ 4 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/glsl/ir.cpp b/src/glsl/ir.cpp index a5eca5a..bf11e4f 100644 --- a/sr

[Mesa-dev] [PATCH 6/9] glsl: parser UBO support

v2:Instance name an UBO array are not supported. The parser will now return an error message if they are met. --- src/glsl/ast.h | 23 +++ src/glsl/ast_to_hir.cpp | 75 +- src/glsl/glsl_lexer.ll |3 +- src/glsl/glsl_parser.yy | 333 +

[Mesa-dev] [PATCH 7/9] glsl : Linker support for UBO

v2 : - Fix format issue thank to Brian Paul comments. - UBOs are now sent to program correctly. --- src/glsl/link_uniforms.cpp |2 +- src/glsl/linker.cpp| 310 +++- 2 files changed, 309 insertions(+), 3 deletions(-) diff --git a/src/gl

[Mesa-dev] [PATCH 8/9] mesa: add Uniform Buffer Object API implementation

3-D graphics library + * + * Copyright (C) 2004-2011 Brian Paul All Rights Reserved. + * Copyright (C) 2009-2011 VMware, Inc. All Rights Reserved. + * Copyright © 2010-2011 Intel Corporation + * Copyright (C) 2011 Vincent Lejeune. + * + * Permission is hereby granted, free of charge, to any person

[Mesa-dev] [PATCH 9/9] gallium : st_glsl_to_tgsi handles UBO

Reserved. - * Copyright (C) 2009-2011 VMware, Inc. All Rights Reserved. - * Copyright © 2010-2011 Intel Corporation - * Copyright (C) 2011 Vincent Lejeune. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files

[Mesa-dev] [PATCH] glsl: change IR to add UBO information

--- src/glsl/ir.cpp |1 + src/glsl/ir.h |6 ++ src/glsl/ir_clone.cpp |1 + 3 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/glsl/ir.cpp b/src/glsl/ir.cpp index a5eca5a..bf11e4f 100644 --- a/src/glsl/ir.cpp +++ b/src/glsl/ir.cpp @@ -1335,6 +1335,7 @@

[Mesa-dev] [PATCH 1/2] mesa: add Uniform Buffer Object API implementation

2009-2011 VMware, Inc. All Rights Reserved. + * Copyright © 2010-2011 Intel Corporation + * Copyright (C) 2011 Vincent Lejeune. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to d

[Mesa-dev] [PATCH 2/2] gallium : st_glsl_to_tgsi handles UBO

--- src/mesa/state_tracker/st_atom_constbuf.c |8 +++ src/mesa/state_tracker/st_extensions.c |4 + src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 92 ++-- 3 files changed, 59 insertions(+), 45 deletions(-) diff --git a/src/mesa/state_tracker/st_atom_constbuf.c

[Mesa-dev] [PATCH] nvc0/nvfx:PIPE_SHADER_CAP_OUTPUT query returns 0.

glsl to tgsi pass now queries for reading output register cap from drivers. This made nvc0/nvfx complain about unknow PIPE_CAP that breaks piglit tests. This patch fix this. --- src/gallium/drivers/nv50/nv50_screen.c |2 ++ src/gallium/drivers/nvc0/nvc0_screen.c |2 ++ 2 files cha

[Mesa-dev] [PATCH] ARB_Uniform_Buffer_Object: layout(std140) test

@@ -0,0 +1,169 @@ +/* + * Copyright © 2011 Intel Corporation + * Copyright 2011 Vincent Lejeune + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without r

[Mesa-dev] [PATCH 1/2] ARB_Uniform_Buffer_Object: layout(std140) test

et_api() diff --git a/tests/spec/arb_uniform_buffer_object/standard-layout.c b/tests/spec/arb_uniform_buffer_object/standard-layout.c new file mode 100644 index 000..d156647 --- /dev/null +++ b/tests/spec/arb_uniform_buffer_object/standard-layout.c @@ -0,0 +1,168 @@ +/* + * Copyright © 2011 Intel Corporation + *

[Mesa-dev] [PATCH 2/2] ARB_Uniform_Buffer_Object: Draw test

diff --git a/tests/spec/arb_uniform_buffer_object/draw_test.c b/tests/spec/arb_uniform_buffer_object/draw_test.c new file mode 100644 index 000..e053d14 --- /dev/null +++ b/tests/spec/arb_uniform_buffer_object/draw_test.c @@ -0,0 +1,227 @@ +/* + * Copyright © 2011 Marek Olšák + * Copyright © 2011 V

[Mesa-dev] [PATCH] glsl: Add additionnal type alias for convenience.

ivec2, ivec3, bvec2, bvec3 and bvec4 have now a "_type" suffixed alias to identify them easily. These types are currently not widely used inside glsl, however they are refered in UBO spec. It's an opportunity to add them. --- src/glsl/builtin_types.h |5 + src/glsl/glsl_types.h|5 +

[Mesa-dev] [PATCH 1/4] ARB_Uniform_Buffer_Object: layout(std140) test

_target_api() diff --git a/tests/spec/arb_uniform_buffer_object/standard-layout.c b/tests/spec/arb_uniform_buffer_object/standard-layout.c new file mode 100644 index 000..3061136 --- /dev/null +++ b/tests/spec/arb_uniform_buffer_object/standard-layout.c @@ -0,0 +1,168 @@ +/* + * Copyright © 2011 I

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