---
src/gallium/drivers/r600/r600_llvm.c | 24 +++++++++++++---------
src/gallium/drivers/r600/r600_shader.c | 7 +++++--
.../drivers/radeon/radeon_setup_tgsi_llvm.c | 4 ++++
3 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_llvm.c
b/src/gallium/drivers/r600/r600_llvm.c
index 110ba64..d76b9c9 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -25,16 +25,20 @@ static LLVMValueRef llvm_fetch_const(
enum tgsi_opcode_type type,
unsigned swizzle)
{
- /* load.const's operand currently goes through the compiler unmodified,
- * encoding expected by the bytestream reader is
- * ((512 + (4096 * kc_bank) + const_index)*4 + chan)
- */
- LLVMValueRef idx = lp_build_const_int32(bld_base->base.gallivm,
- radeon_llvm_reg_index_soa(reg->Register.Index + 512,
swizzle));
- LLVMValueRef cval = build_intrinsic(bld_base->base.gallivm->builder,
- "llvm.AMDGPU.load.const", bld_base->base.elem_type,
- &idx, 1, LLVMReadNoneAttribute);
-
+ LLVMValueRef offset[2] = {
+
LLVMConstInt(LLVMInt64TypeInContext(bld_base->base.gallivm->context), 0, false),
+ lp_build_const_int32(bld_base->base.gallivm,
reg->Register.Index)
+ };
+ if (reg->Register.Indirect) {
+ struct lp_build_tgsi_soa_context *bld =
lp_soa_context(bld_base);
+ LLVMValueRef index =
LLVMBuildLoad(bld_base->base.gallivm->builder,
bld->addr[reg->Indirect.Index][reg->Indirect.SwizzleX], "");
+ offset[1] = LLVMBuildAdd(bld_base->base.gallivm->builder,
offset[1], index, "");
+ }
+ LLVMTypeRef const_ptr_type =
LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4),
1024),2);
+ LLVMValueRef const_ptr =
LLVMBuildIntToPtr(bld_base->base.gallivm->builder,
lp_build_const_int32(bld_base->base.gallivm, 0), const_ptr_type, "");
+ LLVMValueRef ptr = LLVMBuildGEP(bld_base->base.gallivm->builder,
const_ptr, offset, 2, "");
+ LLVMValueRef cvecval = LLVMBuildLoad(bld_base->base.gallivm->builder,
ptr, "");
+ LLVMValueRef cval =
LLVMBuildExtractElement(bld_base->base.gallivm->builder, cvecval,
lp_build_const_int32(bld_base->base.gallivm, swizzle), "");
return bitcast(bld_base, type, cval);
}
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 6056831..76e33d4 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -539,7 +539,10 @@ static int r600_vtx_from_byte_stream(struct
r600_shader_ctx *ctx,
fprintf(stderr, "Error adding vtx\n");
}
/* Use the Texture Cache */
- ctx->bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX;
+ if (ctx->bc->chip_class >= EVERGREEN)
+ ctx->bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX;
+ else
+ ctx->bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
return bytes_read;
}
@@ -1276,7 +1279,7 @@ static int r600_shader_from_tgsi(struct r600_screen
*rscreen,
}
#ifdef R600_USE_LLVM
- if (use_llvm && ctx.info.indirect_files) {
+ if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files &
(1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
fprintf(stderr, "Warning: R600 LLVM backend does not support "
"indirect adressing. Falling back to TGSI "
"backend.\n");
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index acbd387..4eb8603 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -324,6 +324,10 @@ emit_store(
}
switch(reg->Register.File) {
+ case TGSI_FILE_ADDRESS:
+ temp_ptr = bld->addr[reg->Register.Index][chan_index];
+ LLVMBuildStore(builder, value, temp_ptr);
+ continue;
case TGSI_FILE_OUTPUT:
temp_ptr =
bld->outputs[reg->Register.Index][chan_index];
break;
--
1.8.0.1
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
