[Mesa-dev] [PATCH 02/12] i965/rbc: Set aux surface unconditionally for sampling engine

ation backing this though. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 46 ++-- 1 file changed, 43 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri

[Mesa-dev] [PATCH 09/12] intel/blorp: Allow single slice converter to suppress number of layers

Signed-off-by: Topi Pohjolainen --- src/intel/blorp/blorp_blit.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index 170c381..026061b 100644 --- a/src/intel/blorp/blorp_blit.c +++ b/src/intel/blorp/blorp_blit.c @@ -1271,9

[Mesa-dev] [PATCH 07/12] i965/blorp: Instruct vertex fetcher to provide prim instance id

This will indicate target layer (Render Target Array Index) needed for layered clears. v2: Use 3DSTATE_VF_SGVS for gen8+ Signed-off-by: Topi Pohjolainen --- src/intel/blorp/blorp_genX_exec.h | 26 ++ 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/src

[Mesa-dev] [PATCH 01/12] i965/rbc: Allow integer formats as advertised in isl_format.c

From: Topi Pohjolainen Blorp consults brw_is_color_fast_clear_compatible() to see if any restrictions apply for fast clear in addition to the capablities advertised in isl_format.c::format_info[]. On Gen8+ integer formats are backlisted for plain old fast clear but there is no reason why

[Mesa-dev] [PATCH 10/12] intel/blorp: Add plumbing for setting color clear layer count

Signed-off-by: Topi Pohjolainen --- src/intel/blorp/blorp.h | 6 +++--- src/intel/blorp/blorp_clear.c | 16 +--- src/mesa/drivers/dri/i965/brw_blorp.c | 6 +++--- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/src/intel/blorp/blorp.h b/src

[Mesa-dev] [PATCH 07/12] i965/blorp: Instruct vertex fetcher to provide prim instance id

This will indicate target layer (Render Target Array Index) needed for layered clears. v2: Use 3DSTATE_VF_SGVS for gen8+ Signed-off-by: Topi Pohjolainen --- src/intel/blorp/blorp_genX_exec.h | 26 ++ 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/src

[Mesa-dev] [PATCH 08/12] intel/blorp: Allow multiple layers

Signed-off-by: Topi Pohjolainen --- src/intel/blorp/blorp.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c index 4dbba01..17c1ff4 100644 --- a/src/intel/blorp/blorp.c +++ b/src/intel/blorp/blorp.c @@ -119,6 +119,9

[Mesa-dev] [PATCH 12/12] i965/blorp: Use hw generetad primitive copies for layered clears

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 36 --- 1 file changed, 12 insertions(+), 24 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index ce8b848..c487c0c 100644 --- a

[Mesa-dev] [PATCH 02/12] i965/rbc: Set aux surface unconditionally for sampling engine

ation backing this though. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 46 ++-- 1 file changed, 43 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri

[Mesa-dev] [PATCH 11/12] i965/blorp: Sanity check all layers before actual clear

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 6339932..ce8b848 100644 --- a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 03/12] isl/gen8+: Allow 3D auxiliary surfaces

Otherwise once mcs buffer gets allocated without delay for lossless compression (same as we do for msaa), assert starts to fire in piglit case: tex3d. The test uses depth of one which is in fact supported even now. Signed-off-by: Topi Pohjolainen --- src/intel/isl/isl.c | 7 ++- 1 file

[Mesa-dev] [PATCH 06/12] i965/meta: Split conversion of color and setting it

And fix a mangled comment while at it. Signed-off-by: Topi Pohjolainen CC: Ben Widawsky CC: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_blorp.c | 7 +++- src/mesa/drivers/dri/i965/brw_meta_util.c | 56 +-- src/mesa/drivers/dri/i965/brw_meta_util.h | 10

[Mesa-dev] [PATCH 04/12] i965/rbc: Allocate mcs directly

. By doing it directly allows to drop quite a bit unnecessary complexity. Patch leaves brw_predraw_set_aux_buffers() a no-op. Subsequent patches will re-use it and it seemed cleaner to leave it instead of removing and re-introducing. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 06/12] i965/meta: Split conversion of color and setting it

And fix a mangled comment while at it. Signed-off-by: Topi Pohjolainen CC: Ben Widawsky CC: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_blorp.c | 7 +++- src/mesa/drivers/dri/i965/brw_meta_util.c | 56 +-- src/mesa/drivers/dri/i965/brw_meta_util.h | 10

[Mesa-dev] [PATCH 12/12] i965/blorp: Use hw generetad primitive copies for layered clears

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 36 --- 1 file changed, 12 insertions(+), 24 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index ce8b848..c487c0c 100644 --- a

[Mesa-dev] [PATCH 09/12] intel/blorp: Allow single slice converter to suppress number of layers

Signed-off-by: Topi Pohjolainen --- src/intel/blorp/blorp_blit.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index 170c381..026061b 100644 --- a/src/intel/blorp/blorp_blit.c +++ b/src/intel/blorp/blorp_blit.c @@ -1271,9

[Mesa-dev] [PATCH 05/12] i965/blorp: Skip redundant re-fast clear for non-compressed

Originally re-clears where skipped but when lossless compression was introduced the re-clears where errorneously enabled also for non-compressed fast clears. Signed-off-by: Topi Pohjolainen CC: Ben Widawsky CC: Kenneth Graunke CC: Harri Syrja Cc: Chad Versace --- src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 11/12] i965/blorp: Sanity check all layers before actual clear

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 6339932..ce8b848 100644 --- a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 04/12] i965/rbc: Allocate mcs directly

From: Topi Pohjolainen such as we do for compressed msaa. In case of non-compressed simgle sampled buffers the allocation of mcs is deferred until there is actually a clear operation that needs the mcs. In case of render buffer compression the mcs buffer always needed and there is no real reason

[Mesa-dev] i965: Hardware assisted layered clears

Jason Ekstrand Topi Pohjolainen (12): i965/rbc: Allow integer formats as advertised in isl_format.c i965/rbc: Set aux surface unconditionally for sampling engine isl/gen8+: Allow 3D auxiliary surfaces i965/rbc: Allocate mcs directly i965/blorp: Skip redundant re-fast clear for non-compressed

[Mesa-dev] [PATCH 08/12] intel/blorp: Allow multiple layers

Signed-off-by: Topi Pohjolainen --- src/intel/blorp/blorp.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c index 4dbba01..17c1ff4 100644 --- a/src/intel/blorp/blorp.c +++ b/src/intel/blorp/blorp.c @@ -119,6 +119,9

[Mesa-dev] [v2 5/6] isl/gen8+: Allow 1D and 3D auxiliary surfaces

constraining it either. Signed-off-by: Topi Pohjolainen --- src/intel/isl/isl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index c7639d0..3dfdf20 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -1329,7 +1329,8

[Mesa-dev] [v2 4/6] i965/rbc: Set aux surface sampling engine according to rb settings

ation backing this though. v2 (Jason): Prepare also for the case where surface is sampled with non-compressible format forcing also rendering without compression. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 74 ++

[Mesa-dev] [v2 1/6] i965/rbc: Allow integer formats as advertised in isl_format.c

e the lossless compression being effectively turned off for integer formats. Once the mcs buffer is allocated beforehand, the assertion addressed here would start triggering. v2: Drop the assert instead of relaxing it (Jason) Fix typo while at it. Signed-off-by: Topi Pohjolainen --- src/mesa/dr

[Mesa-dev] i965: Allocate mcs directly for lossless compressed

surfaces without aux buffer (i.e., as non-compressed. 2) Sampling a compressed buffer which is resolved needs to be set with auxiliary buffer if the same surface is also going to written in the same rendering pass. CC: Jason Ekstrand Topi Pohjolainen (6): i965/rbc: Allow integer form

[Mesa-dev] [v2 3/6] i965: Track non-compressible sampling of renderbuffers

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.c | 16 src/mesa/drivers/dri/i965/brw_context.h | 10 ++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 ++-- 3 files changed, 36 insertions(+), 2 deletions

[Mesa-dev] [v2 2/6] i965: Replace boolean rb surface state setup argument with flags

And add plumbing to provide it all the way to surface state emitter. This is not used yet but will be in subsequent patches to carry additional constraints. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 2 +- src/mesa/drivers/dri/i965/brw_state.h

[Mesa-dev] [v2 6/6] i965/rbc: Allocate mcs directly

. By doing it directly allows to drop quite a bit unnecessary complexity. Patch leaves brw_predraw_set_aux_buffers() a no-op. Subsequent patches will re-use it and it seemed cleaner to leave it instead of removing and re-introducing. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965

[Mesa-dev] [4.1/6] i965: Add sanity check for non-compressible texture views

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 34 1 file changed, 34 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 054c5c8..7bd4a97 100644

[Mesa-dev] [v3 4/6] i965/rbc: Consult rb settings for texture surface setup

ation backing this though. v2 (Jason): Prepare also for the case where surface is sampled with non-compressible format forcing also rendering without compression. v3: Split asserts and decision making. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri

[Mesa-dev] [v3 3/6] i965: Track non-compressible sampling of renderbuffers

v3: - Actually set the flags when needed instead of falsely overwriting them (Jason). - Use more generic name for flag (dropped RENDERBUFFER) - Consult also shader images Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.c | 32

[Mesa-dev] [v2 19/26] i965: Restrict fast color clear on first slice only

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 8 1 file changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 526c8ec..452efef 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src

[Mesa-dev] [v2 26/26] i965: Enable fast clears for multi-lod

From: Ben Widawsky On SKL (also fast clear is used for level 0, layer 0): Manhattan 3.0: 3.88434% +/- 0.814659% Manhattan 3.0 off: 3.25542% +/- 0.101149% Trex: 3.43501% +/- 0.31223% Trex off: 4.13781% +/- 0.0993569% ON BDW: Manhattan 3.0:

[Mesa-dev] [v2 23/26] i965: Restructure fast clear eligibility decision

From: Ben Widawsky v2 (Jason): - Use PRM citation for SKL now that it is available - Also return false for gen < 8 mipmapped/arrayed Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 51 +++ 1 file changed, 37 insertions(+),

[Mesa-dev] [v3 26/26] i965: Enable fast clears for multi-lod

: 1.37079% +/- 0.571208% Manhattan 3.0 off: 1.74029% +/- 0.267499% v2 (Ben, Matt): Fix rebase error by removing the perf warning v3 (Topi): Rebased on top of revised eligibility logic Signed-off-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand (v2) --- src/mesa/drivers/dri/i965

[Mesa-dev] [v2 22.1/26] i965: Apply non-msrt mcs array/mipmap horizontal alignment rules

Signed-off-by: Topi Pohjolainen CC: Jason Ekstrand --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 35 --- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

[Mesa-dev] [v2 22/26] i965: Apply non-msrt mcs array/mipmap vertical alignment rules

mip-levels and the latter for qpitch. Signed-off-by: Topi Pohjolainen CC: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 68 +++- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 3 +- src/me

[Mesa-dev] [PATCH 1/2] i965/miptree: Don't shrink textures when augmenting for more levels

l, and therefore such is created. Generation for level one in turn finds right base level size but only one level when two is needed. And the same goes on for all eight levels. This patch prevents the shrink maintaining the NPOT size of 293x277. Signed-off-by: Topi Pohjolainen CC: Jason Ekstr

[Mesa-dev] [PATCH 2/2] intel/blorp: Fix rectangle size for level-not-zero resolves

Needed to prevent gpu hangs when mip-mapped compression gets enabled. Signed-off-by: Topi Pohjolainen CC: Jason Ekstrand --- src/intel/blorp/blorp_clear.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c index

[Mesa-dev] [v2] i965: Fast color clear for mipmapped and arrayed

This is a rebase on top recent changes by Jason and Lionel. While things have changed quite a bit in some of the patches they have mostly become clearer. Ben Widawsky (1): i965: Enable fast clears for multi-lod Topi Pohjolainen (16): i965: Refactor lossless compression state tracking i965

[Mesa-dev] [v2 03/17] i965: Add new interface for full color resolves

Upcoming patches will introduce fast clear in level/layer granularity like the driver does already for depth/hiz. This patch introduces equivalent full resolve option. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.c| 6 +++--- src/mesa/drivers/dri/i965

[Mesa-dev] [v2 10/17] i965: Move fast clear state enumeration into resolve map

Status is still tracked per miptree. Next patch will switch to resolve map per slice/level. Signed-off-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 58 -- src/mesa/drivers/dri/i965/intel_resolve_map.c | 6 +-- src

[Mesa-dev] [v2 01/17] i965: Refactor lossless compression state tracking

setting the state in blorp_surf_for_miptree(). Signed-off-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand (v1) --- src/mesa/drivers/dri/i965/brw_blorp.c| 8 ++-- src/mesa/drivers/dri/i965/brw_draw.c | 5 + src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3

[Mesa-dev] [v2 05/17] i965: Split per miptree and per slice/level fast clear bits

own boolean. Possible follow-up work is to combine disable_aux_buffers and no_ccs into single enum. v2 (Jason): Changed no_msrt_mcs to no_ccs and updated comment Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 2 +- src/mesa/drivers/dri/i965

[Mesa-dev] [v2 11/17] i965: Track fast color clear state in level/layer granularity

v2: Added intel_resolve_map_clear() into intel_miptree_release() Signed-off-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand (v1) --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 64 +++ src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 14 +++--- 2 files changed, 53

[Mesa-dev] [v2 08/17] i965: Add plumbing for fast clear layer/level details

on when the actual functionality is enabled. v2: Rebased on top current master setting the state in blorp_surf_for_miptree(). Signed-off-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand (v1) --- src/mesa/drivers/dri/i965/brw_blorp.c| 17 src/mesa/drivers/dri/i965

[Mesa-dev] [v2 06/17] i965: Provide slice details to renderbuffer fast clear state tracker

This patch also introduces getter and setter for fast clear state preparing for tracking the state per slice. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 3 +- src/mesa/drivers/dri/i965/brw_draw.c | 10 +++--- src/mesa/drivers/dri/i965

[Mesa-dev] [v2 14/17] i965: Use ISL for CCS layouts

One can now also delete intel_get_non_msrt_mcs_alignment(). Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 138 +++--- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4 - 2 files changed, 38 insertions(+), 104 deletions(-) diff --git

[Mesa-dev] [v2 02/17] i965/blorp: Skip redundant re-fast clear for non-compressed

Originally re-clears where skipped but when lossless compression was introduced the re-clears where errorneously enabled also for non-compressed fast clears. Signed-off-by: Topi Pohjolainen CC: Ben Widawsky CC: Kenneth Graunke CC: Harri Syrja Cc: Chad Versace --- src/mesa/drivers/dri/i965

[Mesa-dev] [v2 15/17] i965/gen8: Relax asserts prohibiting arrayed/mipmapped fast clears

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 4 ++-- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 23 +-- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++- 3 files changed, 17 insertions(+), 13 deletions(-) diff --git a/src

[Mesa-dev] [v2 16/17] i965: Allow single-sampled miptree to be resolved and shared

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 1c8ce0d..d943f04 100644 --- a/src/mesa

[Mesa-dev] [v2 12/17] i965: Restrict fast color clear on first slice only

Signed-off-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_blorp.c | 8 1 file changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 44ae26e..1a4b333 100644 --- a/src/mesa/drivers

[Mesa-dev] [v2 09/17] i965: Refactor check if color resolve is needed

Signed-off-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 43 +-- 1 file changed, 27 insertions(+), 16 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965

[Mesa-dev] [v2 17/17] i965: Enable fast clears for multi-lod

: 1.37079% +/- 0.571208% Manhattan 3.0 off: 1.74029% +/- 0.267499% v2 (Ben, Matt): Fix rebase error by removing the perf warning v3 (Topi): Rebased on top of revised eligibility logic Signed-off-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand (v2) --- src/mesa/drivers/dri/i965

[Mesa-dev] [v2 07/17] i965: Add interface for checking multiple slices if any is unresolved

Signed-off-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 + 2 files changed, 13 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers

[Mesa-dev] [v2 13/17] i965: Resolve non-compressed fast clears prior layered rendering

Signed-off-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_draw.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 0e0bc27..21164f3 100644 --- a/src/mesa

[Mesa-dev] [v2 04/17] i965: Provide slice details to color resolver

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 15 +-- src/mesa/drivers/dri/i965/brw_blorp.h | 3 ++- src/mesa/drivers/dri/i965/brw_context.c | 14 +- src/mesa/drivers/dri/i965/intel_blit.c| 4 ++-- src/mesa

[Mesa-dev] [v3 08/17] i965: Add plumbing for fast clear layer/level details

on when the actual functionality is enabled. v2: Rebased on top current master setting the state in blorp_surf_for_miptree(). v3: Replace open-coded resolved check in surface state emission with intel_miptree_has_color_unresolved(). Signed-off-by: Topi Pohjolainen Reviewed-by: Jason

[Mesa-dev] [v3 11/17] i965: Track fast color clear state in level/layer granularity

unnecessary intel_miptree_set_fast_clear_state() call in brw_blorp_resolve_color() preventing intel_miptree_set_fast_clear_state() from asserting against RESOLVED. Signed-off-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand (v1) --- src/mesa/drivers

[Mesa-dev] [v3 14/17] i965: Use ISL for CCS layouts

One can now also delete intel_get_non_msrt_mcs_alignment(). v2 (Jason): Do not leak aux buf but allocate only after getting ISL surfaces. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 138 +++--- src/mesa/drivers/dri/i965

[Mesa-dev] [v3 04/17] i965: Provide slice details to color resolver

v2: Make intel_miptree_resolve_color() take start layer and layer count. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 13 ++- src/mesa/drivers/dri/i965/brw_blorp.h | 3 ++- src/mesa/drivers/dri/i965/brw_context.c | 14

[Mesa-dev] [PATCH] i965: Release aux buffer when disabling ccs

Otherwise subsequent render cycles keep on using compression and/or fast clear. Signed-off-by: Topi Pohjolainen CC: Kalyan Kondapally CC: Kenneth Graunke --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 1/9] i965: Refactor surface resolves prior to draw call

and move it to brw_draw.c where it will be eventually used. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.c | 174 +-- src/mesa/drivers/dri/i965/brw_draw.c| 178 src/mesa/drivers/dri/i965/brw_draw.h

[Mesa-dev] [PATCH 8/9] i965/gen6+: Use for tex_subimage_2d

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_tex_subimage.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c index f999a93..741637a 100644 --- a/src/mesa/drivers

[Mesa-dev] [PATCH 7/9] i965/gen6+: Use blorp for tex_image_2d

_mesa_store_teximage() as well. This, however, leads to performance regressions in few benchmarks, especially with Synmark OglDrvRes. Therefore intel_texsubimage_gpu_copy is only used to replace the meta path for now. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_tex_image.c | 21

[Mesa-dev] [PATCH 3/9] intel/blorp/dbg: Name blit shaders for easy recognition in dumps

Blorp clears already have an equivalent. Signed-off-by: Topi Pohjolainen --- src/intel/blorp/blorp_blit.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index 8abe3a8..9dcd33f 100644 --- a/src/intel/blorp/blorp_blit.c +++ b/src

[Mesa-dev] [PATCH 9/9] i965: Drop _mesa_meta_pbo_TexSubImage() even for gen < 6

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_tex_image.c| 24 +++- src/mesa/drivers/dri/i965/intel_tex_subimage.c | 19 +-- 2 files changed, 12 insertions(+), 31 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c

[Mesa-dev] [PATCH 5/9] meta: Refactor texture format translation

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/common/meta_tex_subimage.c | 9 +++-- src/mesa/main/glformats.c | 15 +++ src/mesa/main/glformats.h | 4 3 files changed, 22 insertions(+), 6 deletions(-) diff --git a/src/mesa

[Mesa-dev] [PATCH 4/9] i965: Estimate batch space per shader stage

sible with blorp tex uploads (HSW with piglit test max-samplers). One runs out of space while batch wrapping isn't allowed. Signed-off-by: Topi Pohjolainen CC: Kenneth Graunke CC: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_draw.c | 52 +--- 1 f

[Mesa-dev] [PATCH 2/9] i965: Consider surface resolves just before draw

e but only the internal driver state. Signed-off-by: Topi Pohjolainen CC: Kenneth Graunke CC: Jason Ekstrand CC: Ben Widawsky --- src/mesa/drivers/dri/i965/brw_compute.c | 1 + src/mesa/drivers/dri/i965/brw_context.c | 4 src/mesa/drivers/dri/i965/brw_draw.c| 2 ++ 3 files chang

[Mesa-dev] i965/gen6+: Yet another blorp path - tex_(sub)image2d

path but at least there aren't any jenkins regressions. Topi Pohjolainen (9): i965: Refactor surface resolves prior to draw call i965: Consider surface resolves just before draw intel/blorp/dbg: Name blit shaders for easy recognition in dumps i965: Estimate batch space per shader st

[Mesa-dev] [PATCH 6/9] i965: Add support for tex upload using gpu

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_tex.h | 8 + src/mesa/drivers/dri/i965/intel_tex_subimage.c | 194 + 2 files changed, 202 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_tex.h b/src/mesa/drivers/dri/i965

[Mesa-dev] [v2 6/18] i965/blorp: Organize pixel kill and blend/scaled inputs into vec4s

In addition, as these are never used in parallel, add a few assertions. v2 (Jason): Skip some complexity by putting them into a union but pad rectangle grid into a vec4 instead. Also keep the LOAD_UNIFORM macro. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri

[Mesa-dev] [v2 7/18] i965/blorp: Load tranformation coordinates as vec4

In preparation for loading as flat vertex input. v2: Use LOAD_INPUT() macro Signed-off-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand (v1) --- src/mesa/drivers/dri/i965/brw_blorp.h| 3 +-- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 24 ++-- 2 files changed

[Mesa-dev] [v2 6.1/18] i965/blorp: Rename LOAD_UNIFORM to LOAD_INPUT

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index 14db10b..dbf33e1 100644 --- a

[Mesa-dev] [v2 14/18] i965/blorp: Use flat inputs instead of uniforms

v2 (Jason): Use LOAD_INPUT() macro Signed-off-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand (v1) --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 24 +--- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 9 + 2 files changed, 18 insertions(+), 15 deletions

[Mesa-dev] [PATCH] i965/blorp/gen7+: Bring back push constant setup

p defaults in the beginning of each batch buffer. However, hardware doesn't seem to tolerate these packets being programmed multiple times per primitive. Bspec for IVB: "It is invalid to execute this command more than once between 3D_PRIMITIVE commands." Signed-off-by: Topi Poh

[Mesa-dev] [PATCH] i965/blorp: Cleanup leftovers from push constant disabling

Setup for pixel shader push constants is the same as for other stages. Note that on gen8+ the if-else branches were identical and the generation check for packet size redundant. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen7_blorp.c | 27 -- src/mesa/drivers

[Mesa-dev] [PATCH] main: Allow external textures to use fallback (0, 0, 0, 1)

ture has only a single plane. Luckily, that's the only type of external textures that Mesa currently supports." CC: Chad Versace Signed-off-by: Topi Pohjolainen --- src/mesa/main/texstore.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/main/texstore.c b/src/mesa/main/

[Mesa-dev] [PATCH 01/22] i965/meta: Add means for signaling meta blit surface overrides

using blorp honor the renderbuffer settings. These are no piglit tests relying on this. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.c | 10 ++ src/mesa/drivers/dri/i965/brw_context.h | 15 +++ src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 02/22] i965/gen8: Follow stencil meta blit overrides in the context

Hardware before gen8 does not have full stencil texturing support and therefore the signaling for stencil index mode cannot be done through the texture itself - but via driver specific context instead. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c | 3

[Mesa-dev] [PATCH 05/22] i965/fs: Recompile when switching to/from stencil indexing

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_program.h | 20 src/mesa/drivers/dri/i965/brw_wm.c | 14 ++ 2 files changed, 34 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_program.h b/src/mesa/drivers/dri/i965/brw_program.h

[Mesa-dev] i965/fs: Stencil texturing on gen6/7

his can be found in: git://people.freedesktop.org/~tpohjola/mesa stencil_meta_blit_gen6 Topi Pohjolainen (22): i965/meta: Add means for signaling meta blit surface overrides i965/gen8: Follow stencil meta blit overrides in the context i965/gen8: Take into account stencil meta blit layer override

[Mesa-dev] [PATCH 03/22] i965/gen8: Take into account stencil meta blit layer override

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen8_surface_state.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index cd2fb40..f5c75fe 100644 --- a/src/mesa

[Mesa-dev] [PATCH 04/22] i965/fs: Add generator support for fetching texture dimensions

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_defines.h| 2 ++ src/mesa/drivers/dri/i965/brw_fs.cpp | 1 + src/mesa/drivers/dri/i965/brw_fs.h | 3 +++ src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 33 ++ src/mesa

[Mesa-dev] [PATCH 10/22] i965/gen6: Use helper variables for texture surface parameters

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 33 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index f3efdbc

[Mesa-dev] [PATCH 07/22] i965/gen6: Surface state overrides for sampling w-tiled as y-tiled

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 21 + 1 file changed, 21 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index c9d9614..f3efdbc 100644 --- a

[Mesa-dev] [PATCH 11/22] i965/gen7: Configure msaa stencil buffers as single sampled

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 28 --- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index f12f215

[Mesa-dev] [PATCH 15/22] i965/gen6: Add tile offset support for texture surfaces

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 30db9f9..0f596e4 100644 --- a

[Mesa-dev] [PATCH 09/22] i965/gen7: Use helper variables for texture surface parameters

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 34 ++- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index b31f491

[Mesa-dev] [PATCH 06/22] i965/fs/gen6: Use stencil indexing if stencil meta blit is active

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index f9a39ad..c56688c 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b

[Mesa-dev] [PATCH 12/22] i965/gen6: Configure msaa stencil buffers as single sampled

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 5f40301..d00a65d

[Mesa-dev] [PATCH 08/22] i965: Add helper for determining if miptree represents stencil buffer

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 6a91884..80520fa 100644 --- a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 17/22] i965: Keep track of texture base dimensions

These are needed when texturing stencil buffers, otherwise they are simply ignored. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 12 src/mesa/drivers/dri/i965/intel_tex.c | 49 + 2 files changed, 61 insertions(+) diff

[Mesa-dev] [PATCH 19/22] i965/fs/gen6: Support for sampling stencil with msaa coordinates

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_fs.h | 2 +- src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 3 +- src/mesa/drivers/dri/i965/brw_fs_stencil_tex.cpp | 92 +++- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 23 -- 4

[Mesa-dev] [PATCH 20/22] i965/fs/gen6: Support for sampling stencil with noormalized coordinates

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_fs_stencil_tex.cpp | 52 src/mesa/drivers/dri/i965/brw_fs_stencil_tex.h | 1 + 2 files changed, 53 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_stencil_tex.cpp b/src/mesa/drivers/dri

[Mesa-dev] [PATCH 14/22] i965/gen6: Configure w-tiled surfaces as y-tiled

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 22 ++ 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index d00a65d

[Mesa-dev] [PATCH 18/22] i965/fs/gen6: Support for sampling stencil with non-msaa coordinates

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/Makefile.sources | 1 + src/mesa/drivers/dri/i965/brw_fs.h | 1 + src/mesa/drivers/dri/i965/brw_fs_stencil_tex.cpp | 411 +++ src/mesa/drivers/dri/i965/brw_fs_stencil_tex.h | 74 src

[Mesa-dev] [PATCH 22/22] i965/fb/gen6: Use meta path for stencil up/downsampling

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 31 --- 1 file changed, 4 insertions(+), 27 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index dd7e57a..0da23ef

[Mesa-dev] [PATCH 16/22] i965/gen6: Offset stencil texture surfaces directly to level/layer

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 27 +++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 0f596e4

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