Hi,
This extensions is the equivalent of GL_ARB_shader_draw_parameters.
This was added by Vulkan 1.0.39.
Cheers,
Lionel Landwerlin (2):
spirv: add SPV_KHR_shader_draw_parameters support
anv: enable VK_KHR_shader_draw_parameters
src/compiler/spirv/nir_spirv.h | 1 +
src/compiler/spirv
Enables 10 tests from:
dEQP-VK.draw.shader_draw_parameters.*
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_device.c | 4
src/intel/vulkan/anv_pipeline.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
rough
correctly? I'm pretty sure we have exactly zero code for that.
On Wed, Jan 25, 2017 at 10:55 AM, Lionel Landwerlin
mailto:lionel.g.landwer...@intel.com>>
wrote:
Enables 10 tests from:
dEQP-VK.draw.shader_draw_parameters.*
Signed-off-by: Lionel Landwerlin mailto:
Looks good to me :
Reviewed-by: Lionel Landwerlin
On 25/01/17 20:12, Chad Versace wrote:
Untested, but builds. I wanted to get feedback on this approach before
going through the trouble of fetching and building the newest CTS. If
the review feedback is good, then I'll test it with th
The size of the pool is slightly smaller than the size of the
structure containing the whole pool. We need to take that into account
on when setting up the internals.
Fixes a crash due to out of bound memory access in:
dEQP-VK.api.descriptor_pool.out_of_pool_memory
Signed-off-by: Lionel
(Lionel)
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_descriptor_set.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/intel/vulkan/anv_descriptor_set.c
b/src/intel/vulkan/anv_descriptor_set.c
index a4b7638a61..7853ec7dd9 100644
--- a/src/intel/vulkan
Fixes:
dEQP-VK.api.descriptor_pool.out_of_pool_memory
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_util.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/vulkan/anv_util.c b/src/intel/vulkan/anv_util.c
index 6408ac87c7..5fbc7cc113 100644
--- a/src/intel/vulkan
On 26/01/17 13:43, Eric Engestrom wrote:
On Thursday, 2017-01-26 11:27:00 +, Lionel Landwerlin wrote:
Fixes:
dEQP-VK.api.descriptor_pool.out_of_pool_memory
Signed-off-by: Lionel Landwerlin
Reviewed-by: Eric Engestrom
But is there any reason not to add support for all the other
Both patches look good to me :
Reviewed-by: Lionel Landwerlin
On 26/01/17 13:48, Eric Engestrom wrote:
Signed-off-by: Eric Engestrom
---
src/intel/vulkan/anv_util.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/intel/vulkan/anv_util.c b/src/intel/vulkan/anv_util.c
index
Reviewed-by: Lionel Landwerlin
On 26/01/17 13:18, Emil Velikov wrote:
From: Emil Velikov
MSVC warns about implicit conversion as below. Annotate the literal
appropriately to silence the warning.
nir_gather_info.c(249) : warning C4334: '<<' : result of 32-bit shift
implicitly
Reviewed-by: Lionel Landwerlin
On 26/01/17 13:18, Emil Velikov wrote:
From: Emil Velikov
MSVC warns about different const qualifiers. Add the extra const to
silence it.
nir_phi_builder.c(244) : warning C4090: 'initializing' : different 'const'
qualifiers
nir_phi_buil
Fixes:
dEQP-VK.spirv_assembly.instruction.compute.opspecconstantop.vector_related
dEQP-VK.spirv_assembly.instruction.graphics.opspecconstantop.vector_related*
Signed-off-by: Lionel Landwerlin
---
src/compiler/spirv/spirv_to_nir.c | 52 ---
1 file
compiler currently stops parsing variables & types on the OpUndef
and switches to instructions, leaving the following sc_[0-2] variables
untreated.
Signed-off-by: Lionel Landwerlin
---
src/compiler/spirv/spirv_to_nir.c | 1 +
src/compiler/spirv/vtn_variables.c | 6 ++
2 files change
On 27/01/17 08:44, Juan A. Suarez Romero wrote:
On Thu, 2017-01-26 at 17:08 +, Lionel Landwerlin wrote:
Fixes:
dEQP-VK.spirv_assembly.instruction.compute.opspecconstantop.vector_related
dEQP-VK.spirv_assembly.instruction.graphics.opspecconstantop.vector_related*
Signed-off-by
On 27/01/17 16:26, Eric Engestrom wrote:
On Friday, 2017-01-27 17:00:18 +0100, Juan A. Suarez Romero wrote:
This fixes dEQP-VK.api.descriptor_pool.out_of_pool_memory test
Signed-off-by: Juan A. Suarez Romero
Thanks, this is correct, but Lionel Landwerlin already sent [1] a more
complete
Hey Jason,
I'm wondering whether we're missing flushing some dynamic state here too.
Regardless, the flushing you're adding here is definitely required :
Reviewed-by: Lionel Landwerlin
Thanks!
On 24/03/17 23:31, Jason Ekstrand wrote:
Cc: "13.0 17.0"
Combining all the files into a single string didn't make any
difference in the size of the aubinator binary.
With this change we now also embed gen4/4.5/5 descriptions, which
increases the aubinator size by ~16Kb.
Signed-off-by: Lionel Landwerlin
---
src/intel/Makefile.genxml.am
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 68fd18cd68..322f0df523 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -1136,6
Hi Randy,
This patch looks good to me.
Reviewed-by: Lionel Landwerlin
Cc: "17.0 13.0"
Are you planning to send a follow up patch to fix the remaining
layoutCount accesses too?
Cheers,
-
Lionel
On 20/03/17 07:31, Randy Xu wrote:
From: Xu Randy
We should use anv_get_layer
anv_CmdClearColorImage crash issue
Hi Randy,
This patch looks good to me.
Reviewed-by: Lionel Landwerlin
Cc: "17.0 13.0"
Are you planning to send a follow up patch to fix the remaining layoutCount
accesses too?
I guess you means the layerCount access
I checked the code, there are two kinds of
Looks good to me :
Reviewed-by: Lionel Landwerlin
On 27/03/17 15:44, Jason Ekstrand wrote:
Cc: "13.0 17.0"
---
src/intel/vulkan/anv_blorp.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/a
Signed-off-by: Lionel Landwerlin
---
src/intel/genxml/gen6.xml | 40 +++
src/intel/genxml/gen7.xml | 40 +++
src/intel/genxml/gen75.xml | 54
src/intel/genxml/gen8.xml | 69
Signed-off-by: Lionel Landwerlin
---
src/intel/genxml/gen6.xml | 48 ++
src/intel/genxml/gen7.xml | 48 ++
src/intel/genxml/gen75.xml | 64 ++
src/intel/genxml/gen8.xml | 23
files where introduces and we have used
them successfully in aubinator to look at .aub files. With this change
we can apply the same error states reported by the kernel driver.
Cheers,
Lionel Landwerlin (7):
intel: genxml: add INSTDONE registers
intel: genxml: add GFX_ARB_ERROR_RPT register
Signed-off-by: Lionel Landwerlin
---
src/intel/genxml/gen8.xml | 16
src/intel/genxml/gen9.xml | 16
2 files changed, 32 insertions(+)
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 91573ae73a..be54748876 100644
--- a/src/intel/genxml
Signed-off-by: Lionel Landwerlin
---
src/intel/genxml/gen6.xml | 110 +
src/intel/genxml/gen7.xml | 64 ++
src/intel/genxml/gen75.xml | 71 +
src/intel/genxml/gen8.xml | 71
Signed-off-by: Lionel Landwerlin
---
src/intel/genxml/gen7.xml | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index ba9c8e8154..08307b3506 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2665,4
Signed-off-by: Lionel Landwerlin
---
src/intel/genxml/gen6.xml | 12
src/intel/genxml/gen7.xml | 12
src/intel/genxml/gen75.xml | 13 +
src/intel/genxml/gen8.xml | 18 ++
src/intel/genxml/gen9.xml | 18 ++
5 files changed
This is pretty much the same tool as what i-g-t has, only with a more
fancy decoding of the instructions/registers. It also doesn't support
anything before gen4.
Signed-off-by: Lionel Landwerlin
---
src/intel/Makefile.tools.am | 20 +-
src/intel/common/gen_deco
MI_REPORT_PERF_COUNT at the end of the performance
query.
Signed-off-by: Lionel Landwerlin
Cc: Robert Bragg
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 51 ++-
1 file changed, 32 insertions(+), 19 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
On 30/03/17 18:53, Matt Turner wrote:
On Wed, Mar 29, 2017 at 1:07 PM, Lionel Landwerlin
wrote:
Signed-off-by: Lionel Landwerlin
---
src/intel/genxml/gen7.xml | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index
On 30/03/17 19:27, Matt Turner wrote:
On Wed, Mar 29, 2017 at 1:07 PM, Lionel Landwerlin
wrote:
This is pretty much the same tool as what i-g-t has, only with a more
fancy decoding of the instructions/registers. It also doesn't support
anything before gen4.
Signed-off-by: Lionel Landw
On 30/03/17 20:09, Chris Wilson wrote:
On Thu, Mar 30, 2017 at 11:27:26AM -0700, Matt Turner wrote:
I think we should figure out how to make this not just a fork of
intel_error_decode. Should intel_error_decode do away?
There are various tools in i-g-t that I'm definitely in favor of
moving int
v2: add register to gen7.5 (Matt)
Signed-off-by: Lionel Landwerlin
---
src/intel/genxml/gen7.xml | 11 +++
src/intel/genxml/gen75.xml | 11 +++
2 files changed, 22 insertions(+)
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index ba9c8e8154..08307b3506
This is pretty much the same tool as what i-g-t has, only with a more
fancy decoding of the instructions/registers. It also doesn't support
anything before gen4.
v2 (from Matt): Drop authors
Remove undefined automake variable
Signed-off-by: Lionel Landwerlin
Acked-by:
-::gentoo'`,
* the complete build log and the output of `emerge -pqv '=med
On Thu, 30 Mar 2017 at 19:56 Jordan Justen <mailto:jordan.l.jus...@intel.com>> wrote:
Series Reviewed-by: Jordan Justen mailto:jordan.l.jus...@intel.com>>
On 2017-03-25 14:57:15, Lio
and TXL respectively, so we need to pass a valid LOD
Maybe replace with "TXS, TXS and TXL respectively"
Reviewed-by: Lionel Landwerlin
+ * argument.
*/
assert(srcs[TEX_LOGICAL_SRC_LOD].file == BAD_FILE);
srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_ud(0u);
Signed-off-by: Lionel Landwerlin
---
src/intel/Makefile.genxml.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/Makefile.genxml.am b/src/intel/Makefile.genxml.am
index 05a12f8f77..d780ca8470 100644
--- a/src/intel/Makefile.genxml.am
+++ b/src/intel
v2: use Emil's recommendation
change rule to closer to genxml/genX_bits.h
Signed-off-by: Lionel Landwerlin
---
src/intel/Makefile.genxml.am | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/Makefile.genxml.am b/src/intel/Makefile.genxml.am
index 05a12
On 31/03/17 14:23, Emil Velikov wrote:
On 31 March 2017 at 11:42, Lionel Landwerlin
wrote:
The GENXML_XML_FILES variable was missing the "srcdir" prefix, thus
the files won't be found on OOT builds.
Side note: If you want to spare yourself such fun experiences, CC me
on build
On 31/03/17 16:21, Emil Velikov wrote:
On 31 March 2017 at 14:40, Lionel Landwerlin
wrote:
v2: use Emil's recommendation
change rule to closer to genxml/genX_bits.h
Signed-off-by: Lionel Landwerlin
---
src/intel/Makefile.genxml.am | 4 ++--
1 file changed, 2 insertions(
uot;Gen Header: $(PRIVATE_MODULE) <= $(notdir $(@))"
+ $(hide) $(MESA_PYTHON2) $(MESA_TOP)/src/intel/genxml/gen_zipped_file.py
$(addprefix $(MESA_TOP)/src/intel/,$(GENXML_XML_FILES)) > $@ || (rm -f $@;
false)
+
The other files seems to use the header-gen macro, why not this one too?
Acke
This series is :
Reviewed-by: Lionel Landwerlin
On 01/04/17 06:37, Jason Ekstrand wrote:
I've had these patches lying around for a while now waiting for the extension
to go public. It went public, so here they are. This series adds all of the
core window system bits for doing a tr
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 50 +-
src/intel/common/gen_decoder.h | 1 +
2 files changed, 26 insertions(+), 25 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index
Some packets like 3DSTATE_VF_STATISTICS, 3DSTATE_DRAWING_RECTANGLE,
3DPRIMITIVE, PIPELINE_SELECT, etc... have configurable fields in
dword0, we probably want to print those.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c| 21 +
src/intel
(Jordan)
Signed-off-by: Lionel Landwerlin
Acked-by: Matt Turner
---
src/intel/Makefile.tools.am | 19 +-
src/intel/common/gen_decoder.c | 11 +
src/intel/common/gen_decoder.h | 1 +
src/intel/tools/.gitignore | 1 +
src/intel/tools/aubinator_error_
On 03/04/17 21:04, Robert Bragg wrote:
On Mar 30, 2017 16:16, "Lionel Landwerlin"
mailto:lionel.g.landwer...@intel.com>>
wrote:
While exercising reading report with moderate load, we might have to
wait for all the reports to land in the OA buffer, otherwise we mig
On 04/04/17 00:22, Jordan Justen wrote:
From BDW PRM, Volume 6: Command Stream Programming, 'Render Command
Header Format'.
Signed-off-by: Jordan Justen
---
src/intel/common/gen_decoder.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/intel/common/gen_
Sounds like a good strategy :)
Acked-by: Lionel Landwerlin
On 04/04/17 00:22, Jordan Justen wrote:
Decoding with aubinator encountered a command of 0x. With the
previous code, it caused aubinator to jump 255 + 2 dwords to start
decoding again.
Instead we can attempt to detect the
Reviewed-by: Lionel Landwerlin
On 04/04/17 00:22, Jordan Justen wrote:
Signed-off-by: Jordan Justen
---
src/intel/tools/aubinator.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index a64bce7a536
On 04/04/17 19:49, Jordan Justen wrote:
On 2017-04-04 06:21:04, Lionel Landwerlin wrote:
On 04/04/17 00:22, Jordan Justen wrote:
From BDW PRM, Volume 6: Command Stream Programming, 'Render Command
Header Format'.
Signed-off-by: Jordan Justen
---
src/intel/common/gen_deco
Reviewed-by: Lionel Landwerlin
On 04/04/17 23:38, Jason Ekstrand wrote:
We already provide a default LOD for textureQueryLevels and texture() on
non-fragment stages. However, there are more cases where one is needed
such as textureSize(gsampler2DMS*) in SPIR-V. Instead of trying to list
out
This series is :
Acked-by: Lionel Landwerlin
On 05/04/17 12:00, Juan A. Suarez Romero wrote:
Several files are missed in their proper EXTRA_DIST Makefile.am. And thus `make
distcheck` fails.
These commits fix it.
I've split them in 3 because the missing files are in different sections
On 04/04/17 18:45, Robert Bragg wrote:
On Tue, Apr 4, 2017 at 10:20 AM, Lionel Landwerlin
mailto:lionel.g.landwer...@intel.com>>
wrote:
On 03/04/17 21:04, Robert Bragg wrote:
On Mar 30, 2017 16:16, "Lionel Landwerlin"
mailto:lionel.g.landwer...@i
Thanks!
Reviewed-by: Lionel Landwerlin
On 06/04/17 06:51, Jordan Justen wrote:
The call to gen_print_group should provide a pointer to the beginning
of the the structure data, not the start of the batch data.
Cc: Lionel Landwerlin
Signed-off-by: Jordan Justen
---
src/intel/tools
This is a pretty good indicator that something's gone horribly wrong.
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator_error_decode.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/intel/tools/aubinator_error_decode.c
b/src/intel/
On 06/04/17 12:12, Chris Wilson wrote:
On Thu, Apr 06, 2017 at 12:04:40PM +0100, Lionel Landwerlin wrote:
This is a pretty good indicator that something's gone horribly wrong.
Do you run IPEHR through the decoder? That was somewhere on the todo
list for intel_error_decode.
-Chris
No
I have one suggestion at the bottom of the patch, otherwise :
Reviewed-by: Lionel Landwerlin
On 07/04/17 17:52, Rafael Antognolli wrote:
We need to emit BLEND_STATE, which size is 1 + 2 * nr_draw_buffers
dwords (on gen8+), but the BLEND_STATE struct length is always 17. By
marking it size 1
On 09/04/17 17:23, Jason Ekstrand wrote:
On April 9, 2017 8:48:31 AM Lionel Landwerlin
wrote:
I have one suggestion at the bottom of the patch, otherwise :
Reviewed-by: Lionel Landwerlin
On 07/04/17 17:52, Rafael Antognolli wrote:
We need to emit BLEND_STATE, which size is 1 + 2
On 31/03/17 16:17, Jason Ekstrand wrote:
Cc: "13.0 17.0"
---
src/intel/vulkan/anv_blorp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 72a468a..f26f5e5 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulka
On 12/04/17 12:57, Jason Ekstrand wrote:
On Wed, Apr 12, 2017 at 12:25 PM, Lionel Landwerlin
mailto:lionel.g.landwer...@intel.com>>
wrote:
On 31/03/17 16:17, Jason Ekstrand wrote:
Cc: "13.0 17.0" mailto:mesa-sta...@lists.freedesktop.org>>
---
es used in either buffer cannot
be reused before primary is destroyed/reset.
As a result the only point at which we can get stale data in the VF
cache is at the beginning of the primary buffer.
If that matches your understanding, this is :
Reviewed-by: Lionel Landwerlin
+
Reviewed-by: Lionel Landwerlin
On 12/04/17 23:33, Kenneth Graunke wrote:
Starting positions >= 32 are not part of the header, rather than >.
Caught by Coverity, which found that "bits <<= field->start" may shift
by 32, which has undefined behavior.
CID: 14049
Reviewed-by: Lionel Landwerlin
On 12/04/17 23:33, Kenneth Graunke wrote:
I introduced this when cleaning up this code. libdrm_intel was fine.
While passing NULL to free() is a common pattern...passing NULL to
unmap seems pretty bad. You really ought to know whether you have
a buffer or not
We did support single value operand equations, but not single variable
operand ones. In particular we were failing on "$Sampler0Bottleneck".
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_oa.py | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
Reviewed-by: Lionel Landwerlin
On 14/04/17 14:55, Jason Ekstrand wrote:
---
src/compiler/nir/nir.c | 2 ++
src/compiler/nir/nir_split_var_copies.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index 43fa60f..0abf9b6
Acked-by: Lionel Landwerlin
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
On 03/06/18 19:41, Mauro Rossi wrote:
Change to avoid building error:
external/mesa/src/intel/vulkan/anv_android.c:131:72:
error: too few arguments to function call, expected 5, have 4
result = anv_bo_cache_import(device, &device->bo_cache, dma_buf, &bo);
~~~
On 03/06/18 21:22, Mauro Rossi wrote:
Hi there,
2018-06-03 21:52 GMT+02:00 Lionel Landwerlin
mailto:lionel.g.landwer...@intel.com>>:
On 03/06/18 19:41, Mauro Rossi wrote:
Change to avoid building error:
external/mesa/src/intel/vulkan/anv_android.c:131:72:
y: Mauro Rossi
Thanks for the fix!
Reviewed-by: Lionel Landwerlin
---
src/intel/vulkan/anv_android.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/vulkan/anv_android.c b/src/intel/vulkan/anv_android.c
index ed5da5b537..45a21dcfc3 100644
--- a/src/intel/vulkan/
Reviewed-by: Lionel Landwerlin
On 04/06/18 01:38, Mauro Rossi wrote:
Changes to avoid building error:
external/mesa/src/intel/vulkan/anv_android.c:131:72:
error: too few arguments to function call, expected 5, have 4
result = anv_bo_cache_import(device, &device->bo_cache, dma_b
Reviewed-by: Lionel Landwerlin
On 04/06/18 01:48, Mauro Rossi wrote:
Changes to avoid building error:
external/mesa/src/intel/vulkan/anv_android.c:131:72:
error: too few arguments to function call, expected 5, have 4
result = anv_bo_cache_import(device, &device->bo_cache, dma_b
Reviewed-by: Lionel Landwerlin
On 04/06/18 11:18, Kenneth Graunke wrote:
On pre-4.13 kernels, which don't support I915_EXEC_BATCH_FIRST, we move
the validation list entry to the end...but incorrectly left the exec_bo
array alone, causing a mismatch where exec_bos[0] no longer corresponded
Looks like we forgot to update this bit of the driver for softpin.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_intel.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/vulkan/anv_intel.c b/src/intel/vulkan/anv_intel.c
index 431cef5c6ac..06db5787a9c 100644
--- a/src
On 05/06/18 11:28, Lionel Landwerlin wrote:
Looks like we forgot to update this bit of the driver for softpin.
Signed-off-by: Lionel Landwerlin
I guess :
Fixes: 4affeba1e9eb42 ("anv: Soft-pin everything else")
---
src/intel/vulkan/anv_intel.c | 2 ++
1 file changed, 2
An invalid format could be computed through the
modifier_is_supported() helper. Better verify each step.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=10664
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4
src/mesa/drivers/dri/i965
We have no corresponding ISL format for XBGR2101010.
Signed-off-by: Lionel Landwerlin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106642
---
src/mesa/drivers/dri/i965/intel_screen.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src
An invalid format could be computed through the
modifier_is_supported() helper. Better verify each step.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106642
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4
src/mesa/drivers/dri/i965
Signed-off-by: Lionel Landwerlin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106642
---
src/mesa/drivers/dri/common/dri_util.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/common/dri_util.c
b/src/mesa/drivers/dri/common/dri_util.c
index a591dfcd7d2
Found by Eero.
v2: Add G16R16 formats (Lionel)
Signed-off-by: Lionel Landwerlin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106642
---
src/mesa/drivers/dri/common/dri_util.c | 16
1 file changed, 16 insertions(+)
diff --git a/src/mesa/drivers/dri/common/dri_util.c
channels.g.bits > 0 &&
+ fmtl->channels.b.bits > 0 &&
+ fmtl->channels.a.bits > 0 &&
+ fmtl->channels.a.type == ISL_VOID;
}
enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
Do you want to use it in is
Reviewed-by: Lionel Landwerlin
On 06/06/18 18:17, Jason Ekstrand wrote:
We follow the same convention as isl_format_get_layout in having two
assertions to ensure that only valid formats are passed in. We also
check against the array size of the table because some valid formats
such as CCS
On 06/06/18 18:27, Jason Ekstrand wrote:
On Wed, Jun 6, 2018 at 7:57 AM, Lionel Landwerlin
mailto:lionel.g.landwer...@intel.com>>
wrote:
Found by Eero.
v2: Add G16R16 formats (Lionel)
Signed-off-by: Lionel Landwerlin mailto:lionel.g.landwer...@intel.com>>
Bug
Found by Eero.
v2: Add G16R16 formats (Lionel)
v3: Fix G16R16 mapping to mesa format (Jason)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Plamena Manolova (v2)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106642
---
src/mesa/drivers/dri/common/dri_util.c | 16
1
ut advertising them shouldn't hurt.
On Wed, Jun 6, 2018 at 10:36 AM, Lionel Landwerlin
mailto:lionel.g.landwer...@intel.com>>
wrote:
Found by Eero.
v2: Add G16R16 formats (Lionel)
v3: Fix G16R16 mapping to mesa format (Jason)
Signed-off-by: Lionel Landwerlin mailto
Reviewed-by: Lionel Landwerlin
On 07/06/18 01:48, Jason Ekstrand wrote:
There were some places that were calling anv_semaphore_impl_cleanup and
neither deleting the semaphore nor setting the type back to NONE. Just
set it to NONE in impl_cleanup to avoid these issues.
Bugzilla: https
You left out isl_buffer_fill_image_param() in isl_storage_image.c
Regardless, this is an improvement and with this I actually hit the
assert :)
Reviewed-by: Lionel Landwerlin
On 06/06/18 18:47, Jason Ekstrand wrote:
We add two assertions instead of one because the first assertion that
Reviewed-by: Lionel Landwerlin
On 06/06/18 18:47, Jason Ekstrand wrote:
We follow the same convention as isl_format_get_layout in having two
assertions to ensure that only valid formats are passed in. We also
check against the array size of the table because some valid formats
such as CCS
Reviewed-by: Lionel Landwerlin
On 06/06/18 18:47, Jason Ekstrand wrote:
This reworks it to work like query_dma_buf_modifiers and, in particular,
makes it more flexible so that we can disallow a non-static set of
formats.
Cc: mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965
Reviewed-by: Lionel Landwerlin
On 06/06/18 18:47, Jason Ekstrand wrote:
Cc: mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/intel_screen.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src
Reviewed-by: Lionel Landwerlin
On 06/06/18 18:47, Jason Ekstrand wrote:
Not all of the MESA_FORMAT and ISL_FORMAT helpers we use can properly
handle RGBX formats. Also, we don't want to make decisions based on
those in the first place because we can't render to RGBA and we use th
Reviewed-by: Lionel Landwerlin
On 06/06/18 18:47, Jason Ekstrand wrote:
---
src/mesa/drivers/dri/i965/intel_screen.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965
Sorry for missing that.
Fixes: e73d136a023080 ("vulkan/wsi/x11: Implement FIFO mode.")
Reviewed-by: Lionel Landwerlin
On 01/06/18 12:16, Cameron Kumar wrote:
The queue_manager thread can access the images from x11_present_to_x11,
hence this reorder prevents dereferencing of danglin
from the aub file and
fetch them on request by the batch decoder. As a result we can get rid
of the 1<<40 mmapped address space and only rely on the mmap aub file
\o/
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator.c | 116 +---
1 file changed
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_batch_decoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/common/gen_batch_decoder.c
b/src/intel/common/gen_batch_decoder.c
index a8e709358cd..963adbec271 100644
--- a/src/intel/common
On 10/06/18 13:23, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-06-10 13:15:10)
Now that we're softpinning the address of our BOs in anv & i965, the
addresses selected start at the top of the addressing space. This is a
problem for the current implementation of aubinator which
On 10/06/18 18:42, Eric Engestrom wrote:
Coverity ID: 1436909
Fixes: 3352f2d746d3959b22ca4 "i965: Create multiple miptrees for planar YUV
images"
Signed-off-by: Eric Engestrom
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-
On 11/06/18 14:22, Eric Engestrom wrote:
From: Eric Engestrom
v2: intel_miptree_release() already takes care of the planes, no need
to hand-code the loop (Lionel)
Coverity ID: 1436909
Cc: Lionel Landwerlin
Fixes: 3352f2d746d3959b22ca4 "i965: Create multiple miptrees for plana
On 13/06/18 21:26, Jason Ekstrand wrote:
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 46 ++
src/mesa/drivers/dri/i965/brw_bufmgr.h | 1 -
2 files changed, 10 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
b/src/mesa/drivers/dri/i
On 14/06/18 14:01, Lionel Landwerlin wrote:
On 13/06/18 21:26, Jason Ekstrand wrote:
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 46 ++
src/mesa/drivers/dri/i965/brw_bufmgr.h | 1 -
2 files changed, 10 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers
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