e_buf_create(struct brw_context *brw,
> struct intel_mipmap_tree *mt)
> @@ -1412,7 +1500,12 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
> struct intel_mipmap_tree *mt)
> {
> assert(mt->hiz_buf == NULL);
> - mt->hiz_b
On Tue, Nov 11, 2014 at 03:06:03PM -0800, Jordan Justen wrote:
> On 2014-11-10 10:51:17, Ben Widawsky wrote:
> > On Mon, Jul 21, 2014 at 11:00:51PM -0700, Jordan Justen wrote:
> > > We are still allocating a miptree for hiz, but we only use fields from
> > > intel_mi
these stats to implement ARB_pipeline_statistics_query.
Eric wrote it, and Ken touched it last. Do you have any opposition?
Cc: Eric Anholt
Cc: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff
On Thu, Nov 13, 2014 at 09:47:10AM -0800, Eric Anholt wrote:
> Kenneth Graunke writes:
>
> > On Wednesday, November 12, 2014 06:54:31 PM Ben Widawsky wrote:
> >> Every other unit in the geometry pipeline automatically enables
> >> statistics gathering. This part o
most basic support for GOTO simply so we don't need to remember
to change the function in the future.
Cc: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_defines.h | 1 +
src/mesa/drivers/dri/i965/brw_disasm.c | 29 ++---
src/mesa/d
On Wed, Nov 19, 2014 at 01:28:25AM -0800, Kenneth Graunke wrote:
> On Tuesday, November 18, 2014 12:35:55 PM Ben Widawsky wrote:
> > Add support for decoding the new branch control bit. I saw two things wrong
> > with
> > the existing code.
> >
> > 1. It didn&
y mostly safe after your patch to fix libdrm. Unless you
start getting into the prelocation stuff, where I'd bet there are at least a few
unsafe assumptions (unless my patches or equivalent were merged, the kernel
isn't even 48b safe). I also think we determined the 0 state base thing won&
On Wed, Nov 19, 2014 at 10:40:56PM -0800, Ben Widawsky wrote:
> On Wed, Nov 19, 2014 at 09:18:54PM -0800, Kenneth Graunke wrote:
> > On Wednesday, November 19, 2014 02:13:03 PM Ian Romanick wrote:
> > > On 11/18/2014 09:11 PM, Chad Versace wrote:
> > > > This patch
Move this to a separate function so that we can begin to add other little
caveats without making too big a mess.
NOTE: There is some desire to improve this function eventually, but we need to
fix a bug first.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 42
easy to backport.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86268
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 20 ++--
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/src
On Fri, Nov 21, 2014 at 10:50:31AM -0800, Ben Widawsky wrote:
> Fix one of the few cases where we can't reliable touch the destination hazard
> bits. I am explicitly doing this patch individually so it is easy to
> backport. I
> was tempted to do this patch before the pre
On Fri, Nov 21, 2014 at 11:04:18AM -0800, Matt Turner wrote:
> On Fri, Nov 21, 2014 at 10:50 AM, Ben Widawsky
> wrote:
> > Move this to a separate function so that we can begin to add other little
> > caveats without making too big a mess.
> >
> > NOTE: There
On Fri, Nov 21, 2014 at 11:09:44AM -0800, Matt Turner wrote:
> On Fri, Nov 21, 2014 at 10:50 AM, Ben Widawsky
> wrote:
> > Fix one of the few cases where we can't reliable touch the destination
> > hazard
> > bits. I am explicitly doing this patch individually so i
tiling coming back different, but
put a warn or something at least.
> +
> +
> static struct intel_miptree_aux_buffer *
> intel_hiz_miptree_buf_create(struct brw_context *brw,
> struct intel_mipmap_tree *mt)
> @@ -1540,6 +1638,8 @@ intel_miptree_alloc_hiz(str
Bail if we failed to create the bo (Ben)
>
> Signed-off-by: Jordan Justen
> Reviewed-by: Topi Pohjolainen
I really don't want to review this one. I think some of the same things I said
in patch 5 apply here. This patch improves the current situation, so let's move
it forward.
Ac
ter than 8 varyings we will hit this condition. CC Ken to clarify.
Cc: Kenneth Graunke
Reported-by: Ilia Mirkin (via Coverity)
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/gen8_sf_state.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/mesa/driver
ter than 8 varyings we will hit this condition. CC Ken to clarify.
v2: Forgot to git add the warning message in v1
Cc: Kenneth Graunke
Reported-by: Ilia Mirkin (via Coverity)
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/gen8_sf_state.c | 7 ++-
1 file changed, 6 insertions(+),
like a
compute_atoms[].
Sorry that I have no context on this. Forgive me if this is a stupid
interjections.
--
Ben Widawsky, Intel Open Source Technology Center
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
able to reproduce this, and therefore for now, I'll
assume it was some transient issue which has been fixed.
Signed-off-by: Ben Widawsky
---
docs/GL3.txt | 1 +
src/mapi/glapi/gen/GL4x.xml | 14
src/mesa/drivers/dri/i965/gen6_queryo
On Sun, Nov 23, 2014 at 02:12:10AM -0500, Ilia Mirkin wrote:
> On Sat, Nov 22, 2014 at 6:52 PM, Ben Widawsky
> wrote:
> > This patch implements ARB_pipeline_statistics_query. This addition to GL
> > does
> > not add a new API. Instead, it adds new tokens to the exist
I think your comments
mimic some of my questions as well, so I see no need for Jordan to respond to my
mail.
The only modification to your request that I would ask is that Jordan send a
list of where there is perceived overlap as opposed to sending the full list of
state (let him do the work :P).
On Sun, Nov 23, 2014 at 01:50:08PM -0500, Ilia Mirkin wrote:
> On Sun, Nov 23, 2014 at 1:31 PM, Ben Widawsky wrote:
> > On Sun, Nov 23, 2014 at 02:12:10AM -0500, Ilia Mirkin wrote:
> >> On Sat, Nov 22, 2014 at 6:52 PM, Ben Widawsky
> >> wrote:
&
determine that the argument
passed in is within the correct boundary, however, it was using UQ as the upper
limit instead of Q.
To my knowledge you can only hit this case with the branch I am currently
working on, so it doesn't fix any known issues.
Signed-off-by: Ben Widawsky
---
src/mesa/dr
On Tue, Mar 10, 2015 at 09:43:26PM -0700, Kenneth Graunke wrote:
> On Thursday, February 26, 2015 03:42:53 PM Ben Widawsky wrote:
> > Keep this as a separate patch for review, but I will squash it with the
> > previous
> > patch before pushing.
> >
> > We
On Tue, Mar 10, 2015 at 09:19:30PM -0700, Kenneth Graunke wrote:
> On Thursday, February 26, 2015 03:42:52 PM Ben Widawsky wrote:
> > From: Kristian Høgsberg
> >
> > v2 by Ben:
> > Rebase with conflict resolution
> > Add the SKL scaling factors
>
> I&#x
On Tue, Mar 10, 2015 at 05:39:24PM +, Neil Roberts wrote:
> Ben Widawsky writes:
>
> > This patch will use a new calculation to determine if a surface can be
> > blitted
> > from or to. Previously, the "total_height" member was used. Total_height in
> &
On Sat, Mar 14, 2015 at 09:54:27PM -0700, Jordan Justen wrote:
> Add some values for gen7 & gen8. These are the number threads in a
> subslice.
>
> Signed-off-by: Jordan Justen
> Cc: Ben Widawsky
> Cc: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/brw_con
On Mon, Feb 23, 2015 at 10:02:26AM -0800, Matt Turner wrote:
> On Sun, Feb 22, 2015 at 3:06 PM, Ben Widawsky wrote:
> > On Sun, Feb 08, 2015 at 02:48:02PM -0800, Matt Turner wrote:
> >> On Sun, Feb 8, 2015 at 1:59 PM, Ben Widawsky
> >> wrote:
> >> > + /*
On Mon, Mar 23, 2015 at 02:18:30PM +, Neil Roberts wrote:
> Ben Widawsky writes:
>
> > diff --git a/src/mesa/drivers/dri/i965/intel_blit.h
> > b/src/mesa/drivers/dri/i965/intel_blit.h
> > index f563939..531d329 100644
> > --- a/src/mesa/drivers/dri/i965/i
On Mon, Mar 23, 2015 at 02:52:50PM +, Neil Roberts wrote:
> Sorry for the delay in replying to this.
>
> Ben Widawsky writes:
>
> >> > +static inline uint32_t
> >> > +intel_miptree_blit_height(struct intel_mipmap_tree *mt)
> >> > +{
x27;t need to set it at
init. For whatever reason this improves stability on ETQW with the bug mentioned
below.
TODO: This patch still needs to be tested on a full piglit run.
References: https://bugs.freedesktop.org/show_bug.cgi?id=89039 (doesn't fix)
Cc: Anuj Phogat
Cc: Eero Tamminen
Signed-o
MD(0))
> FF(sfid,
> /* 4: */ 123, 120, /* called msg_target */
> /* 4.5 */ 123, 120,
> @@ -364,9 +379,6 @@ FF(sfid,
> FC(base_mrf, 27, 24, brw->gen < 6);
> /** @} */
>
> -/* Message descriptor bits */
> -#define MD(x) (x + 96)
> -
> /**
>
ge),
> +input->name);
The current code isn't wrong, but it made things somewhat confusing for me when
reviewing. I don't think there is ever a case where input->data.assigned is
valid. Inputs are supposed to be read only, and so they would never be assigned
ount, ctx);
> + instructions->push_tail(inst);
> + rhs_base += count;
> + row_idx += count;
> +}
Add a space here
> +if (row_idx >= rows) {
> + row_idx = 0;
> + col_idx++;
> + }
dered.
Cc: Matt Turner
Cc: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 7 +++
src/mesa/drivers/dri/i965/brw_ir_fs.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
at getting the performance data more stable.
Cc: Matt Turner
Cc: Kenneth Graunke
Cc: Jason Ekstrand
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 104 +
src/mesa/drivers/dri/i965/brw_fs.h | 3 +
src/mesa/drivers/dri/i965/brw_f
Based originally on a patch from Ken in May 2014 of the same title. Things
changed enough that I didn't feel comfortable leaving his authorship. Ken, if
you feel you should retain authorship, it's fine with me, just call it
reviewed-by me instead.
Cc: Kenneth Graunke
Signed-off-by: Be
dered.
Cc: Matt Turner
Signed-off-by: Ben Widawsky
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 7 +++
src/mesa/drivers/dri/i965/brw_ir_fs.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_f
but never emit the new instruction I see similar results.
Cc: Matt Turner
Cc: Kenneth Graunke
Cc: Jason Ekstrand
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 92 ++
src/mesa/drivers/dri/i965/brw_fs.h | 3 +
src/mesa/driver
count, ctx);
> +instructions->push_tail(inst);
> +rhs_base += count;
> +row_idx += count;
> +remaining_slots -= count;
> +
> +/* Sometimes, there is still data left in the parameters and
> +
derToTexture (because certain textures are considered complete even
when they're not??). I don't know enough to assert correctness for that though.
Would be nice if you could dumb this down for me as well.
With a valid explanation of how tObj->_MipmapComplete and tObj->_
Same as previous, but for BSW.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 11098cf..ec6c4e6 100644
--- a
This optimization is disabled by default, and it is recommended to be enabled.
The docs do not provide much info.
Cc: Ian Romanick
Cc: "Neil S. Roberts"
Signed-off-by: Ben Widawsky
---
Notes:
I am enabling this optimization separately for BSW as the recommendation was
explic
On Fri, Apr 10, 2015 at 07:50:19PM -0700, Kenneth Graunke wrote:
> On Friday, April 10, 2015 12:52:03 PM Ben Widawsky wrote:
> > Based originally on a patch from Ken in May 2014 of the same title. Things
> > changed enough that I didn't feel comfortable leaving his authorship.
On Fri, 10 Apr 2015 15:49:32 -0700
Jordan Justen wrote:
> Sounds reasonable. Assuming you build tested, series
> Reviewed-by: Jordan Justen
Same
r-b: bwidawsk...
Though I am not sure I see the utility of 4 patches instead of 1...
>
> On 2015-04-10 13:45:24, Mark Janes wrote:
> > Please pard
On Fri, Apr 10, 2015 at 07:39:51PM +0100, Neil Roberts wrote:
> Commit e93566a15c61c33faa changed the message header code needed to
> make Skylake use SIMD4x2 so that it uses a register with width 4
> instead of 8 as the source register in the send message. However it
> also changed the width for t
t; Cc: mesa-sta...@lists.freedesktop.org
> > ---
>
> Wow, yeah, that's awful.
>
> Doesn't ib/new_ib suffer from the same problem?
>
> With ib/new_ib fixed as well,
Good catch, Matt. It looks like it is needed to me as well. (The author and
reviewer o
Starting with Skylake, the display engine is capable of scanning out from
Y-tiled buffers. As such, we can and should use Y-tiling for better efficiency.
Note that the buffer allocation done for mipmaps will already never allocate an
X-tiled buffer for GEN9.
Signed-off-by: Ben Widawsky
---
src
ee similar results.
v5: Remove declaration of combine_tex_header since v4 dropped that function
(Ben)
Remove check for impossible case of an empty block (Matt)
Set dest earlier to avoid extra special-casing in generate_tex (Matt)
Cc: Kenneth Graunke
Cc: Jason Ekstrand
Signed-off-by: Ben Widawsky
R
On Mon, Apr 13, 2015 at 02:04:53PM +0100, Neil Roberts wrote:
> Ben Widawsky writes:
>
> > Can you do me a favor since I am lazy? Can you send the generated asm
> > diff with this patch? I am admittedly rusty on the matter, but I
> > thought a mov is just a mov, a
sage header on Skylake to get SIMD4x2 mode.
> - * Reserve space for the register.
> - */
> - if (brw->gen >= 9) {
> -reladdr.reg_offset++;
> -alloc.sizes[reladdr.reg] = 2;
> - }
> -
> dst
tle before it. So I think this is our bug.
>
> The workaround is to emit a non-pipelined state packet after issuing a
> CONSTANT_BUFFER packet. This is really similar to the workaround I
> developed in commit c4fd0c9052dd391d6f2e9bb8e6da209dfc7ef35b.
>
> Signed-off-by: Ke
uce the code duplication. It will also be useful in the next
> patch to expand what happens on Gen9+. This shouldn't introduce any
> functional changes.
Hopefully you agreed and didn't just do it for me :-)
Reviewed-by: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/brw_vec
ader from g0. This was accidentally lost
> during a rebase on top of 07c571a39fa1.
> Split the patch into two so that the helper function is a separate
> change.
> Fix emitting the MOV instruction on Gen7.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?i
ayouting code to pick the qpitch value in a similar way.
>
> v2: Make the commit message and comments more convincing
Yell louder next time, I think you just fixed my fast clear bugs :D !!!
Reviewed-by: Ben Widawsky
Tested-by: Ben Widawsky
___
Gen9 surface state is very similar to the previous generation. The important
changes here are aux mode, and the way clear colors work.
NOTE: There are some things intentionally left out of this decoding.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_state_dump.c | 36
---
src/mesa/drivers/dri/i965/intel_debug.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_debug.c
b/src/mesa/drivers/dri/i965/intel_debug.c
index a5b883c..b4ec59e 100644
--- a/src/mesa/drivers/dri/i965/intel_debug.c
+++ b/src/mesa/drivers/dri/
: 0x: SF_CLIP VP: Min extents: 0.00x0.00
0x7db8: 0x: SF_CLIP VP: Max extents: 299.00x349.00
While here, fix the wrong offsets for the guardband (I didn't check if it used
to be valid on GEN4).
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_defines.h| 1 +
BIND0: surface state address
0x7924: 0x7940:BIND1: surface state address
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_defines.h| 4 +-
src/mesa/drivers/dri/i965/brw_state_dump.c | 86 --
2 files changed, 85 insertions(+), 5 deletions
is makes some of
the sample output in subsequent commits slightly incorrect.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_state_dump.c | 226 -
1 file changed, 219 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c
b/
|CLAMP|WRAP
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_state_dump.c | 71 +-
1 file changed, 70 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c
b/src/mesa/drivers/dri/i965/brw_state_dump.c
index 89c1a29..21a3d8f
ere. (Also potentially we get
slightly less bad performance when using INTEL_DEBUG=batch)
I didn't intend to leave any major state changes out, so if you're aware of one
I've missed, please don't hesitate to have me add it.
Ben Widawsky (7):
i965: Add all surface types t
factor ONE,ONE,ONE,ONE (src,dst,src
alpha, dst alpha)
function ADD,ADD (color, alpha), Disables:
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_state_dump.c | 105 -
1 file changed, 103 insertions(+), 2 deletions(-)
diff --git
Gen9 is mostly the same as Gen8.
NOTE: There are some things intentionally left out of this decoding.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_state_dump.c | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers
: 0x0977: SURF007: Clear color:
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_context.h| 1 +
src/mesa/drivers/dri/i965/brw_state.h | 13 -
src/mesa/drivers/dri/i965/brw_state_batch.c| 20
src/mesa/drivers/dri/i965
Oops, ignore this one. It was from an older series.
On Thu, Apr 23, 2015 at 04:50:01PM -0700, Ben Widawsky wrote:
> Gen9 is mostly the same as Gen8.
>
> NOTE: There are some things intentionally left out of this decoding.
>
> Signed-off-by: Ben Widawsky
> ---
> src/
I think for BSW
it's actually required.
http://lists.freedesktop.org/archives/intel-gfx/2014-July/049917.html
Thread counts all look right afaict though.
>
> Signed-off-by: Jordan Justen
> Cc: Ben Widawsky
> Cc: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/brw_contex
On Sat, Apr 25, 2015 at 05:39:20PM -0700, Jordan Justen wrote:
> On 2015-04-25 13:54:41, Ben Widawsky wrote:
> > On Fri, Apr 24, 2015 at 04:33:06PM -0700, Jordan Justen wrote:
> > > Add some values for gen7 & gen8. These are the number threads in a
> > > subslice.
&g
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_device_info.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c
b/src/mesa/drivers/dri/i965/brw_device_info.c
index 7ab70fe..4904e63 100644
--- a/src
v2: Forgot to squash in the comment removal
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_device_info.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c
b/src/mesa/drivers/dri/i965
PTOR_DATA:
>
> DWORD 6, bits 20:16: With text identical to the Ivy Bridge PRM.
>
> Signed-off-by: Jordan Justen
Reviewed-by: Ben Widawsky
[snip]
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
On Sat, Feb 13, 2016 at 09:36:01AM +0200, Pohjolainen, Topi wrote:
> On Thu, Feb 11, 2016 at 01:48:18PM -0800, Ben Widawsky wrote:
> > On Thu, Feb 11, 2016 at 08:33:58PM +0200, Topi Pohjolainen wrote:
> > > Signed-off-by: Topi Pohjolainen
> > > ---
>
than it seems. Furthermore, if the existing ordering is important, it seems
a comment is sorely lacking.
Kristian you wrote this originally, would you mind looking at this one? With
Kristian's ack, this is;
Reviewed-by: Ben Widawsky
--
Ben Widawsky, Intel Open Source Techn
ed to doing this as long as you've considered my potential
objection.
> uint32_t *surf = allocate_surface_state(brw, &offset, surf_index);
>
> surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) |
> --
> 2.5.0
>
> ___
rts_non_msrt_mcs(const struct brw_context *brw,
> + unsigned tiling);
> +
> +bool
> +intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw,
> + const struct intel_mipmap_tree
> *mt);
> +
> +bool
On Thu, Feb 11, 2016 at 08:34:11PM +0200, Topi Pohjolainen wrote:
> v2: Use explicitly against base type of GL_FLOAT instead of
> using _mesa_is_format_integer_color(). Otherwise we miss
> GL_UNSIGNED_NORMALIZED.
>
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/intel
> fixing state restore mechanism in i965-meta operations.
>
> v2 (Ben): Use combination of msaa_layout and number of samples
>instead of introducing explicit type for lossless
>compression.
>
I'm skipping 19 for now until we get through the rest.
I
On Tue, Feb 16, 2016 at 10:39:23AM -0500, Rob Clark wrote:
> Try xf86-video-modesetting instead of xf86-video-intel..
Might I inquire the thought behind this? It's my impression that unless one is
using glamor, modesetting won't ever outperform xf86-video-intel (which defaults
to the hardware blit
t;
> Fixes piglit test: spec/arb_compute_shader/zero-dispatch-size
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94100
> Signed-off-by: Jordan Justen
> Cc: Kenneth Graunke
> Cc: Ben Widawsky
> Cc: Ilia Mirkin
> ---
>
lands?
Reviewed-by: Ben Widawsky
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94150
>
> Signed-off-by: Topi Pohjolainen
> CC: Ben Widawsky
> CC: Ian Romanick
> Reviewed-by: Tapani Palli
> ---
> src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 9 -
On Tue, Feb 16, 2016 at 12:21:02PM -0800, Jordan Justen wrote:
> On 2016-02-16 12:03:10, Ben Widawsky wrote:
> > On Tue, Feb 16, 2016 at 10:09:50AM -0800, Jordan Justen wrote:
> > > On gen7 (Ivy Bridge, Haswell), we will get a GPU hang if an indirect
> > > dispa
The Iris part is left unbranded because we did not have these with original SKL.
Cc: "11.0 11.1"
---
include/pci_ids/i965_pci_ids.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 5139e27..c049b78 100644
--- a/include/pc
Also adds some of the Iris/Pro parts which we previously didn't have named.
Signed-off-by: Ben Widawsky
---
include/pci_ids/i965_pci_ids.h | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
A new list yielded new devices that apparently have shipped, or will ship.
Signed-off-by: Ben Widawsky
---
intel/intel_chipset.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 35148e5..392f7ba 100644
--- a/intel
A new list yielded new devices that apparently have shipped, or will ship.
v2: I can't read. 0x192d is GT3
Signed-off-by: Ben Widawsky
---
intel/intel_chipset.h | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
Also adds some of the Iris/Pro parts which we previously didn't have named.
v2: 0x192d is gt3, not gt4
Signed-off-by: Ben Widawsky
---
include/pci_ids/i965_pci_ids.h | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/pci_ids/i965_pci_ids.h b/in
The Iris part is left unbranded because we did not have these with original SKL.
v2: 0x192d is gt3, not gt4
Cc: "11.0 11.1"
---
include/pci_ids/i965_pci_ids.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 5139e27..77d
On Wed, Feb 17, 2016 at 04:02:32AM +0200, Grazvydas Ignotas wrote:
> On Wed, Feb 17, 2016 at 1:45 AM, Ben Widawsky
> wrote:
> > The Iris part is left unbranded because we did not have these with original
> > SKL.
> >
> > v2: 0x192d is gt3, not gt4
>
> The na
On Tue, Feb 16, 2016 at 03:42:45PM -0800, Ben Widawsky wrote:
> A new list yielded new devices that apparently have shipped, or will ship.
>
> v2: I can't read. 0x192d is GT3
>
> Signed-off-by: Ben Widawsky
> ---
> intel/intel_chipset.h | 11 ---
> 1 fil
The Iris part is left unbranded because we did not have these with original SKL.
v2: 0x192d is gt3, not gt4
v3: Forgot to update the temporary brand string when I did v2.
Cc: "11.0 11.1"
Signed-off-by: Ben Widawsky
---
include/pci_ids/i965_pci_ids.h | 2 ++
1 file changed, 2
expected).
I was originally planning to use an assert, but there is no reason to be so
mean.
Cc: Jordan Justen
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_context.c | 8 ++--
src/mesa/drivers/dri/i965/brw_device_info.h | 5 +
2 files changed, 11 insertions(+), 2
to do that as well.
The interface was introduced in libdrm 2.4.60, which is already required, so it
should all be fine.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_screen.c | 21 +
src/mesa/drivers/dri/i965/intel_screen.h | 12 +++-
2 files
ould too.
Note that I did manage to find a good use for this info anyway in the computer
shader thread counts.
Cc: Kaveh Nasri
Signed-off-by: Ben Widawsky
---
include/pci_ids/i965_pci_ids.h | 4 ++--
src/mesa/drivers/dri/i965/brw_context.c | 33 +---
src/m
fused
configurations which /might/ have shipped. Fallback code is still there.
Cc: Jordan Justen
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_context.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa
We have better information now, and 28 was not a valid thing to support. 6 EUs
per sublice with 7 threads per EU is the minimum supported config.
Cc: Jordan Justen
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
On Mon, Mar 07, 2016 at 10:16:41PM -0800, Matt Turner wrote:
> On Mon, Mar 7, 2016 at 5:39 PM, Ben Widawsky
> wrote:
> > Certain products are not uniquely identifiable based on device id alone. The
> > kernel exports an interface to help deal with this. This patch merely
>
On Mon, Mar 07, 2016 at 10:11:11PM -0800, Matt Turner wrote:
> On Mon, Mar 7, 2016 at 5:39 PM, Ben Widawsky
> wrote:
> > "Braswell" is a Cherryview based *thing*. It unfortunately requires extra
> > information to determine its marketing name. Unlike all previous prod
Thank you very much for the patch. It is
>
> Reviewed-by: Matt Turner
>
> I'll commit it shortly.
Great patch.
Reviewed-by: Ben Widawsky
>
> > ---
> > src/mesa/drivers/dri/i965/gen7_urb.c | 24 +---
> > 1 file changed, 5 insertions(+),
break;
>}
>
> + if (s_type == EGL_PBUFFER_BIT) {
> + if ((tex_target == EGL_NO_TEXTURE && tex_format != EGL_NO_TEXTURE)
> ||
> + (tex_format == EGL_NO_TEXTURE && tex_target != EGL_NO_TEXTURE))
> {
> +
OPY_BLT command.
>
> Cc: Ben Widawsky
> Cc: Chad Versace
> Signed-off-by: Anuj Phogat
I verified that the docs were changed (in March actually):
Reviewed-by: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/intel_blit.c | 65
> --
> 1
601 - 700 of 1066 matches
Mail list logo
