way to make the assertion was.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 77 ++---
1 file changed, 72 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 1fc5
determine that the argument
passed in is within the correct boundary, however, it was using UQ as the upper
limit instead of Q.
To my knowledge you can only hit this case with the branch I am currently
working on, so it doesn't fix any known issues.
Signed-off-by: Ben Widawsky
Reviewed-by: Matt T
tride must exist.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
b/src/mesa/drivers/dri/i965/brw_reg.h
index a04149c..76d3248 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src
This is the analogous patch to i965/fs: Extract dword multiplies. Like that
patch, we'll do the internal users separately to aid bisection.
Because that patch was requested by Jason, this was is also indirectly requested
by him.
Cc: Jason Ekstrand
Signed-off-by: Ben Widawsky
---
src
As it turns out, we were over-thinking the cause of the hang on
Cherryview. It's simply errata for Cherryview.
commit 88fea85f09e2252035bec66ab26c375b45b000f5
Author: Ben Widawsky
Date: Fri Nov 21 10:47:41 2014 -0800
i965/vec4/gen8: Handle the MUL dest hazard exception
This
I couldn't find any other callers which have a DW operand in a mul.
Signed-off-by: Ben Widawsky
---
It would be good if someone else can take a look
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/driver
this case, we do have
some ability to fix it up, and so we try to do that. Some cases we cannot fix
things and so we must assert. Finding it at visitor time does make things a bit
easier to debug and fix.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs.cpp
This is the vec4 analogous patch to i965/fs: Add users of emit_mul_dw
Signed-off-by: Ben Widawsky
---
It would be good if someone else can take a look
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers
If we have any case where both operands can fit in 16b, a plain old mul with no
mach should be sufficient.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri
o previous patches, this actually applies to the whole MUL/MACH macro
operation, but it's easier to just catch it at MACH, since that is the only
thing we use MACH for.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp | 2 +-
src/mesa/d
for
imul_high. This fixes failing tests on IVB, and doesn't seem to hurt the same
tests on HSW.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 52
1 file changed, 30 insertions(+), 22 deletions(-)
diff --git a/src/mesa/driver
separately for easier bisection.
Cc: Jason Ekstrand
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 106 +++
src/mesa/drivers/dri/i965/brw_fs.h | 4 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 87 ++
3 files
There are currently 2 users of this functionality. I have 2 more users coming
up, and having a simple function makes the results much cleaner. The existing
interface semantics was proposed by Matt.
Cc: Matt Turner
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_eu_emit.c
other usage is for the
high results from the MUL/MACH macro
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86822
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 28 +++-
1 file changed, 19 insertions(+), 9 deletions(-)
diff -
requires the accumulator write flag, which can hinder optimization passes.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_defines.h| 2 +
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 12 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 73
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_extensions.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 76f..49d92bb 100644
--- a/src/mesa/drivers
This patch addresses the errata on GEN8+ which disallows the mul/mach macro to
have a modifier on src1. This was previously listed as a FINISHME.
Assertions for these cases will be added shortly.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 23
old.
This assertion applies to mul too as mentioned above. It is harder to detect mul
when used in the macro operation, so that is left for now.
"Accumulator is an implicit source and thus cannot be an explicit source
operand."
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i96
wrote equivalent code using the QW type.
Cc: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_defines.h | 3 ++-
src/mesa/drivers/dri/i965/brw_eu.h | 21 +
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 21
On Tue, Dec 23, 2014 at 10:38:36AM -0800, Matt Turner wrote:
> On Mon, Dec 22, 2014 at 7:29 PM, Ben Widawsky
> wrote:
> > The fancy DW * DW = QW that was enabled earlier in the series for the fs
> > does
> > not work for the vec4 paths. vec4 paths use ALIGN16 mode,
On Tue, Dec 23, 2014 at 10:45:27AM -0800, Matt Turner wrote:
> On Mon, Dec 22, 2014 at 7:29 PM, Ben Widawsky
> wrote:
> > This patch addresses the errata on GEN8+ which disallows the mul/mach macro
> > to
> > have a modifier on src1. This was previously listed as a FINIS
On Mon, Dec 22, 2014 at 07:29:30PM -0800, Ben Widawsky wrote:
> I couldn't find any other callers which have a DW operand in a mul.
>
> Signed-off-by: Ben Widawsky
>
> ---
> It would be good if someone else can take a look
> ---
> src/mesa/drivers/dri/i965/brw_f
lia Mirkin
Signed-off-by: Ben Widawsky
---
.../glapi/gen/ARB_pipeline_statistics_query.xml| 24 +++
src/mapi/glapi/gen/Makefile.am | 1 +
src/mapi/glapi/gen/gl_API.xml | 3 +
src/mesa/main/config.h | 3 +
src
static so gcc doesn't initialized it on every call (Ian)
- Use if (_mesa_has_geometry_shaders(ctx)) instead of explicit checks (Ian)
- Core mesa parts moved into a prep patch (Ilia)
Cc: Ian Romanick
Cc: Ilia Mirkin
Signed-off-by: Ben Widawsky
---
docs/relnotes/10.5.0.html
On Wed, Nov 12, 2014 at 11:17:55AM -0800, Kenneth Graunke wrote:
> According to the documentation, we need to do a CS stall on every fourth
> PIPE_CONTROL command to avoid GPU hangs. The kernel does a CS stall
> between batches, so we only need to count the PIPE_CONTROLs in our batches.
>
> v2: G
lignment=%d row_length=%d skip_pixels=%d skip_rows=%d)\n",
> + __FUNCTION__, texImage->Level, xoffset, yoffset, width, height,
> + format, type, texImage->TexFormat, image->mt->tiling,
> + packing->Alignment, packing->RowLength, packing->SkipPixels
WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
>
I think you should do this as two separate patches, 1 per platform. For the BSW
patch (given that I had the same functionality in the kernel patch I asked you
to look at ;-) and FWIW, Jordan has numbers on BSW B-step with my kernel
On Sun, Jan 11, 2015 at 04:05:25PM -0800, Kenneth Graunke wrote:
> On Sunday, January 11, 2015 01:49:41 PM Ben Widawsky wrote:
> > On Sat, Jan 10, 2015 at 06:44:49PM -0800, Kenneth Graunke wrote:
> > > This is an important optimization for avoiding read-after-write (RAW)
>
On Sun, Jan 11, 2015 at 06:53:32PM -0800, Kenneth Graunke wrote:
[snip]
>
> Jesse had suggested setting it in broadwell_init_clock_gating on January 5th,
> and Valtteri tried it on January 7th. He found "no noticeable difference".
> I tried it again, and confirmed his result: there was zero per
On Sun, Jan 11, 2015 at 07:05:21PM -0800, Kenneth Graunke wrote:
> On Sunday, January 11, 2015 05:46:09 PM Ben Widawsky wrote:
> > On Sun, Jan 11, 2015 at 04:05:25PM -0800, Kenneth Graunke wrote:
> > > On Sunday, January 11, 2015 01:49:41 PM Ben Widawsky wrote:
> > > &
On Mon, Jan 12, 2015 at 02:02:34PM +0200, Ville Syrjälä wrote:
> On Sun, Jan 11, 2015 at 07:14:57PM -0800, Ben Widawsky wrote:
> > On Sun, Jan 11, 2015 at 07:05:21PM -0800, Kenneth Graunke wrote:
> > > On Sunday, January 11, 2015 05:46:09 PM Ben Widawsky wrote:
> > > &
idths"
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_blit.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index e919528..9500bd7 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++
An upcoming patch is going to introduce some code here, and having this code
organized as the patch does makes it a bit easier to read later.
There should be no functional change here.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_blit.c | 28
1
overnor, and HI-Z raw stall optimization, the improvement
is even more stark on Braswell.
Jordan was extremely helpful in creating this patch. Consider him co-author.
References: http://patchwork.freedesktop.org/patch/38909/
Cc: Jordan Justen
Signed-off-by: Ben Widawsky
---
src/mesa/d
;ll always allocate
a linear BO for huge buffers. The next patch changes that.
v2: Fix NDEBUG warning
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_blit.c | 107 -
1 file changed, 105 insertions(+), 2 deletions(-)
diff --git a/src/mesa/driver
On Tue, Jan 13, 2015 at 11:37:50PM -0800, Ben Widawsky wrote:
> This patch will use a new calculation to determine if a surface can be blitted
> from or to. Previously, the "total_height" member was used. Total_height in
> the
> case of 2d, 3d, and cube map arrays is th
On Thu, Jan 15, 2015 at 01:41:14AM -0800, Kenneth Graunke wrote:
> There's some debate about whether we should use Meta or BLORP,
> but either should run circles around the BLT engine.
>
> Improves performance in "copypixrate -blit -back" (from Mesa demos)
> by 232.037% +/- 3.15795% (n=10) on Broa
On Thu, Jan 15, 2015 at 11:33:22AM -0800, Kenneth Graunke wrote:
> On Thursday, January 15, 2015 08:56:23 AM Ben Widawsky wrote:
> > On Thu, Jan 15, 2015 at 01:41:14AM -0800, Kenneth Graunke wrote:
> > > There's some debate about whether we should use Meta or BLORP,
>
y.
This is a respin of a patch which only [incorrectly] tried to address gen9.
Cc: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_sampler_state.c | 5 +
src/mesa/drivers/dri/i965/brw_state.h | 1 -
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 1 -
3 f
On Wed, Sep 02, 2015 at 01:03:43PM +0100, Chris Wilson wrote:
> On Wed, Aug 26, 2015 at 10:52:58AM -0700, Ben Widawsky wrote:
> > Docs suggest this is no longer required starting with Gen8.
> >
> > Perf (no regressions in n=20)
> > OglMultithread 0.67%
&g
On Fri, Sep 04, 2015 at 02:58:30PM -0700, Ben Widawsky wrote:
> On Wed, Sep 02, 2015 at 01:03:43PM +0100, Chris Wilson wrote:
> > On Wed, Aug 26, 2015 at 10:52:58AM -0700, Ben Widawsky wrote:
> > > Docs suggest this is no longer required starting with Gen8.
> > >
>
: Sarah Sharp
Cc: Jordan Justen
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_device_info.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c
b/src/mesa/drivers/dri/i965/brw_device_info.c
index 7ad3a2f..a6a3bb6 100644
-
On Sun, Sep 06, 2015 at 06:12:38PM +0200, Francisco Jerez wrote:
> This series implements dynamic partitioning of the L3 cache space
> among its clients, the purpose is multiple:
>
> - Steal a chunk of L3 space when necessary and reserve it for SLM as
>required to support compute shaders with
On Fri, Sep 11, 2015 at 10:24:29AM -0700, Ben Widawsky wrote:
> On Sun, Sep 06, 2015 at 06:12:38PM +0200, Francisco Jerez wrote:
> > This series implements dynamic partitioning of the L3 cache space
> > among its clients, the purpose is multiple:
> >
> > - Ste
On Fri, Sep 11, 2015 at 11:37:21AM -0700, Ben Widawsky wrote:
> On Fri, Sep 11, 2015 at 10:24:29AM -0700, Ben Widawsky wrote:
> > On Sun, Sep 06, 2015 at 06:12:38PM +0200, Francisco Jerez wrote:
> > > This series implements dynamic partitioning of the L3 cache space
> >
On Fri, Sep 11, 2015 at 12:12:15PM -0700, Jordan Justen wrote:
> On 2015-09-10 16:59:12, Ben Widawsky wrote:
> > All SKL SKUs except the lowest one which has half the L3 size actually have
> > 384K
>
> These commit message lines seem to wrap a bit long. This first li
On Fri, Sep 11, 2015 at 11:33:14AM +0300, Abdiel Janulgue wrote:
> Some updated figures first:
>
> Ue4 Reflections Subway demo
> x fs gather constants disabled
> + fs gather constants enabled
>
> HSW:
> N Min MaxMedian AvgStddev
> x 10 5.
On Tue, Sep 15, 2015 at 12:24:00PM +0300, Abdiel Janulgue wrote:
> Here's a more comprehensive shader-db run:
>
> total instructions in shared programs: 6394485 -> 6374865 (-0.31%)
> instructions in affected programs: 261322 -> 241702 (-7.51%)
> helped:3210
> HU
l_miptree_create_layout(struct brw_context *brw,
> width0 = ALIGN(width0, 2) * 4;
> height0 = ALIGN(height0, 2) * 2;
> break;
> + case 16:
assert(brw->gen >= 9);
Reviewed-by: Ben Widawsky
> +width0 = ALIGN
> Kenneth Graunke experimented with some other patterns that have a
> higher standard deviation but I think after some discussion it was
> decided that it would be better to pick the same pattern as the other
> graphics API in case there are games that rely on this pattern
g that these will magically pass
> on a production device.
>
> clip-and-scissor-blit 16 downsample
> unaligned-blit 16 color msaa
>
> Jenkins is reporting some unstable tests on g45 and g965 but they
> don't seem related so I'm a bit confused.
>
I can revie
On Thu, Sep 17, 2015 at 05:00:06PM +0100, Neil Roberts wrote:
> In order to support 16x MSAA, skl+ has a wider version of lcd2dms that
> takes two parameters for the MCS data. This patch makes it allocate a
> register that is twice as big for the MCS data and then always use
> the wider version.
>
On Thu, Sep 17, 2015 at 05:00:07PM +0100, Neil Roberts wrote:
> In order to support 16x MSAA, skl+ has a wider version of lcd2dms that
> takes two parameters for the MCS data. The MCS data in the response
> still fits in a single register so we just need to ensure we copy both
> values rather than
On Thu, Sep 17, 2015 at 05:00:08PM +0100, Neil Roberts wrote:
> When 16x MSAA is used for sampling with texelFetch the compiler needs
> to use a different instruction which passes more arguments for the MCS
> data. Previously on skl+ it was unconditionally using this new
> instruction. However sinc
R(t1, t1, fs_reg(5));
>
>/* This works for both SIMD8 and SIMD16 */
I'm really sketchy on the details of how this actually works. Mostly, I get what
this code is doing, and I agree that the only difference for 16x should be the
extra bit (because SSPI needs to go up to 7 for S
default:
>unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
> };
This and the previous are:
Reviewed-by: Ben Widawsky
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On Thu, Sep 17, 2015 at 05:00:12PM +0100, Neil Roberts wrote:
> The destination rectangle is now drawn at 4x4 the size and the shader
> code to calculate the sample number is adjusted accordingly.
> ---
> src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c | 22 +-
> 1 file chang
-
> +*|12 |13 |14 |15 |
> +*-
> */
> uint8_t SampleMap2x[2];
> uint8_t SampleMap4x[4];
> uint8_t SampleMap8x[8];
> + uint8_t SampleMap16x[16];
>
> /** GL_ARB_shader_atomic_counters */
> GLuint MaxAtomicBufferBindings;
btw, I noticed in this area of the code that the calculation for shader_offset
is pretty crappy. You could just do:
shader_offset = ffs(samples) - 1;
Reviewed-by: Ben Widawsky
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} else if (screen->devinfo->gen >= 7) {
>return gen7_modes;
I think you also should add a case in get_fast_clear_rect() (even though we
don't have fast clears turned on yet). It's in my fast clear branch I believe,
but it makes more sense in this series.
Reviewed-by: Ben Widawsky
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On Tue, Sep 15, 2015 at 11:37:22AM -0700, Kristian Høgsberg wrote:
> On Thu, Sep 10, 2015 at 03:35:18PM +0200, Iago Toral Quiroga wrote:
> > This is the same we do for other things like uniforms because it ensures
> > optimal performance.
> >
> > Reviewed-by: Jordan Justen
> > ---
> > src/mesa/d
On Wed, Sep 23, 2015 at 06:08:33PM +0100, Neil Roberts wrote:
> Ben Widawsky writes:
>
> > On Thu, Sep 17, 2015 at 05:00:08PM +0100, Neil Roberts wrote:
> >> When 16x MSAA is used for sampling with texelFetch the compiler needs
> >> to use a different instruction w
On Wed, Sep 23, 2015 at 06:28:42PM +0100, Neil Roberts wrote:
> Ben Widawsky writes:
>
> >> + /* On Gen9+ we'll use lcd2ms_w instead which has two registers
> >> for
> >> + * the MCS data.
> >> + */
&
On Wed, Sep 23, 2015 at 11:12:26PM +0100, Neil Roberts wrote:
> Ben Widawsky writes:
>
> > Hmm. As I read it, it sounded like you didn't have to send LOD it's
> > implied to be 0 if you don't send it. If I am wrong about that, then I
> > agree with you
On Thu, Sep 24, 2015 at 11:41:15AM +0100, Emil Velikov wrote:
> Hi guys,
>
> On 2 September 2015 at 20:10, Pohjolainen, Topi
> wrote:
> > On Thu, Aug 27, 2015 at 10:05:14AM -0700, Ben Widawsky wrote:
> >> On Thu, Aug 27, 2015 at 10:51:59AM +0300, Pohjolainen, Topi w
On Thu, Sep 24, 2015 at 11:54:57AM +0100, Emil Velikov wrote:
> Hi Ben,
>
> On 11 September 2015 at 20:15, Ben Widawsky wrote:
> > On Fri, Sep 11, 2015 at 12:12:15PM -0700, Jordan Justen wrote:
> >> On 2015-09-10 16:59:12, Ben Widawsky wrote:
> >> > All SKL
onfusion by renaming the variables to match the hardware
> enum names:
> git ls-files |
> xargs sed -i -e 's/align_w/halign/g' \
> -e 's/align_h/valign/g'
>
> Suggested-by: Kenneth Graunke
> Cc: Ben Widawsky
> Cc: Kenneth Grau
On Tue, Sep 29, 2015 at 02:16:04PM -0700, Chad Versace wrote:
> On Sun 27 Sep 2015, Ben Widawsky wrote:
> > On Fri, Sep 25, 2015 at 12:05:49PM -0700, Chad Versace wrote:
> > > The values of intel_mipmap_tree::align_w and ::align_h correspond to the
> > > hardware
On Thu, Oct 01, 2015 at 08:20:07AM -0700, Chad Versace wrote:
> There are three types of fast clears:
> a. fast depth clears
> b. fast singlesample color clears
> c. fast multisample color clears
> Function intel_miptree_is_fast_clear_capable() checks if a miptree
> supports fast clears of ty
and when not seem like an important to
have if it isn't already there (maybe not an ENV var, but an easy knob in the
code).
> On 09/15/2015 08:59 PM, Ben Widawsky wrote:
> > On Tue, Sep 15, 2015 at 12:24:00PM +0300, Abdiel Janulgue wrote:
> >> Here's a more comprehensive s
All the "features" of the hardware are similar starting with GEN8, so remove as
much of the GEN9 uniqueness as possible. This makes implementing future gen
platforms a bit easier.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_device_info.c | 13 ++---
1 file
information like we have for BXT.
This patch is just a preference of mine, so if people are opposed it doesn't
need to get merged.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_device_info.c | 25 ++---
1 file changed, 10 insertions(+), 15 deletions(-)
diff --
I spotted this while looking for what needs updating in future platforms.
I'm too lazy to go through the git logs, but it was probably missed by Jason
when all the brw refactoring happened.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_context.c | 2 +-
src/mesa/driver
On Mon, Jan 18, 2016 at 07:05:21AM -0800, Kenneth Graunke wrote:
> This writes linked shader programs to .shader_test files to
> $MESA_SHADER_CAPTURE_PATH in the format used by shader-db
> (http://cgit.freedesktop.org/mesa/shader-db).
>
> It supports both GLSL shaders and ARB programs. All stages
On Mon, Jan 18, 2016 at 12:37:18PM -0800, Francisco Jerez wrote:
> Fixes a number of GLES31 CTS failures and hangs on various hardware:
>
> ES31-CTS.texture_gather.plain-gather-depth-2d
> ES31-CTS.texture_gather.plain-gather-depth-2darray
> ES31-CTS.texture_gather.plain-gather-depth-cube
> ES3
: Kenneth Graunke
Date: Fri Aug 14 16:01:33 2015 -0700
i965/vs: Simplify fs_visitor's ATTR file.
Note that the authorship dates are out of order, but the above reflects the
order of the commit dates.
Cc: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_f
nneth Graunke
Cc: Neil Roberts
Cc: Mark Janes
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c
b/src/mesa/drivers/dri/i965/brw_device_info.c
index b8
Cc: Jordan Justen
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index aad512f..820c1d4 100644
--- a
> @@ -896,6 +896,9 @@ brw_meta_resolve_color(struct brw_context *brw,
>
> _mesa_meta_end(ctx);
>
> + /* Restore in case we were called in the middle of brw_try_draw_prims() */
> + vbo_bind_arrays(ctx);
> +
I don't claim to understand meta well enough to call this
n the “full surface clear” bit in 3DSTATE_WM_OP must be set to
1."
I'm very surprised that no regressions were spotted originally.
Signed-off-by: Jordan Justen (v1)
Reviewed-by: Topi Pohjolainen (v1)
Signed-off-by: Ben Widawsky (v2)
---
I am currently running perf data on this patch, b
On Thu, Jan 28, 2016 at 05:31:43PM -0800, Ben Widawsky wrote:
> From: Jordan Justen
>
> After modifying the hiz buffer allocation and qpitch calculation, hiz
> appears to work in all cases on gen8.
>
> v2 by Ben: add GEN8_WM_HZ_FULL_SURFACE_DEPTH_CLEAR. From docs:
> "
They were already declared as such. It was changed here:
commit 31f0967fb50101437d2568e9ab9640ffbcbf7ef9
Author: Ian Romanick
Date: Wed Sep 2 14:43:18 2015 -0700
i965: Make intel_miptree_map_raw static
Cc: Ian Romanick
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965
Chris
> Forbes)
> ---
>
> While taking a look to bug #76396, I found that the git commit message
> on arb_texture_multisample/sample-depth.c mentions that MSAA+hiz not
> working on Haswell was an already know bug. After pinging on IRC Ben
> Widawsky pointed me this around o
updating these as we add new platforms to mesa? I
foresee a problem of these getting stale. I wonder how the drm-intel devs deals
with that.
[snip]
--
Ben Widawsky, Intel Open Source Technology Center
___
mesa-dev mailing list
mesa-dev@lists.freede
e demo seems to work fine without the assert, and therefore release
builds of mesa wouldn't stumble over this. Perhaps there is some unnoticeable
corruption, but I had trouble spotting it.
Thanks to Jason for looking at my backtrace and figuring out what was going on.
Cc: Jason Ekstrand
Si
Cc: Jason Ekstrand
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93358
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_copy_image.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_copy_image.c
b/src/mesa/drivers/dri/i965/inte
rm-intel devs
> > deals with that.
>
> To update this for the new platforms should be a trivial patch. I do not see
> any issues with that.
The issue is remembering to do it. But I take it that we have no good solution
for that.
>
> > [snip]
> >
> > --
> &
over it. The change itself is
somewhat trivial, but I wanted to have the conversation about whether this will
actually be useful. I think we're of similar minds in that we hope it's useful,
and it doesn't make much new clutter (and hopeful
On Mon, Feb 08, 2016 at 09:48:54PM -0800, Jason Ekstrand wrote:
> On Sat, Feb 6, 2016 at 6:11 PM, Ben Widawsky
> wrote:
>
> > This fixes an assertion failure in [at least] one of the Unreal Engine
> > Linux
> > demo/games that uses DXT1 compression. Specifically, the
th, height, depth, 0,
> +compute_msaa_layout(brw, format, 0,
> +disable_aux_buffers),
If you roll in to layout flags, you just pass layout flags to
compute_msaa
gt;&mt->tiling, &pitch, alloc_flags);
>mt->pitch = pitch;
> }
Maybe you can just move the stencil alignment down into the if statement and
make it even better isolated. Right now I think it's a little confusing to have
the local v
On Tue, Feb 09, 2016 at 12:10:18PM -0800, Ian Romanick wrote:
> On 02/09/2016 11:58 AM, Ben Widawsky wrote:
> > On Mon, Feb 08, 2016 at 09:48:54PM -0800, Jason Ekstrand wrote:
> >> On Sat, Feb 6, 2016 at 6:11 PM, Ben Widawsky
> >> wrote:
> >>
> >>&
mt->last_level,
> + mcs_width,
> + mcs_height,
> + mt->logical_depth0,
> + 0 /* num_samples */,
> + INTEL_MSAA_LAYOUT_NONE,
> +
On Mon, Feb 08, 2016 at 06:51:23PM +0200, Topi Pohjolainen wrote:
> Currently the logic allocating and setting up miptrees is closely
> combined with decision making when to re-allocate buffers in
> X-tiled layout and when to associate colors with auxiliary buffers.
>
> These auxiliary buffers are
On Mon, Feb 08, 2016 at 06:51:26PM +0200, Topi Pohjolainen wrote:
> Skylake introduces compression support also for the single-sampled
> color buffers. Similarly to the multi-sampled case the color buffer
> will be associated with an auxiliary surface tracking the
> compression state.
>
> Signed-o
On Mon, Feb 08, 2016 at 06:51:27PM +0200, Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers
entirely instead of correcting it.
You could mention the two patches which touched this part of the code if you
wanted, or perhaps you realized you reviewed both of them :P
Reviewed-by: Ben Widawsky
The one that used type instead of format:
commit 6fa1130cd21926cdd4ae86aa12ee3f5c0bb5ba33
Author
On Mon, Feb 08, 2016 at 06:51:32PM +0200, Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/gen8_surface_state.c | 62
> --
> 1 file changed, 29 insertions(+), 33 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/gen8_surfa
On Mon, Feb 08, 2016 at 06:51:33PM +0200, Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/driver
; src/mesa/drivers/dri/i965/intel_pixel_bitmap.c | 2 +-
> src/mesa/drivers/dri/i965/intel_pixel_read.c| 2 +-
> src/mesa/drivers/dri/i965/intel_tex_image.c | 2 +-
> src/mesa/drivers/dri/i965/intel_tex_subimage.c | 2 +-
> 16 files changed, 318 insertions(+), 136 deletion
because this one also applies to HSW Mobile until B0
> (which we again don't care about), but it's not listed here. How can
> that be?
Sameer, can you address some of Matt's concerns about the accuracy of the
workarounds? I realize you don't know the mesa codebase well, but f
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