On Thu, Sep 17, 2015 at 05:00:06PM +0100, Neil Roberts wrote:
> In order to support 16x MSAA, skl+ has a wider version of lcd2dms that
> takes two parameters for the MCS data. This patch makes it allocate a
> register that is twice as big for the MCS data and then always use
> the wider version.
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 4 ++++
> src/mesa/drivers/dri/i965/brw_disasm.c | 1 +
> src/mesa/drivers/dri/i965/brw_fs.cpp | 27
> ++++++++++++++++++++++++--
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 5 +++++
> src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 9 ++++++---
> src/mesa/drivers/dri/i965/brw_shader.cpp | 5 +++++
> 6 files changed, 46 insertions(+), 5 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 8fc8ceb..2d5b67d 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -969,6 +969,8 @@ enum opcode {
> FS_OPCODE_TXB_LOGICAL,
> SHADER_OPCODE_TXF_CMS,
> SHADER_OPCODE_TXF_CMS_LOGICAL,
> + SHADER_OPCODE_TXF_CMS_W,
> + SHADER_OPCODE_TXF_CMS_W_LOGICAL,
> SHADER_OPCODE_TXF_UMS,
> SHADER_OPCODE_TXF_UMS_LOGICAL,
> SHADER_OPCODE_TXF_MCS,
> @@ -1517,10 +1519,12 @@ enum brw_message_target {
> #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
> #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
> #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
> +#define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W 28
> #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29
> #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30
> #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31
>
> +
> /* for GEN5 only */
> #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0
> #define BRW_SAMPLER_SIMD_MODE_SIMD8 1
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index db23a18..5aca728 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -622,6 +622,7 @@ static const char *const gen5_sampler_msg_type[] = {
> [GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO] = "gather4_po",
> [GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C] = "gather4_po_c",
> [HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE] = "sample_d_c",
> + [GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W] = "ld2dms_w",
> [GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS] = "ld_mcs",
> [GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS] = "ld2dms",
> [GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS] = "ld2dss",
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 32a2adf..82f49b4 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -697,6 +697,7 @@ fs_inst::components_read(unsigned i) const
> case SHADER_OPCODE_TXS_LOGICAL:
> case FS_OPCODE_TXB_LOGICAL:
> case SHADER_OPCODE_TXF_CMS_LOGICAL:
> + case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
> case SHADER_OPCODE_TXF_UMS_LOGICAL:
> case SHADER_OPCODE_TXF_MCS_LOGICAL:
> case SHADER_OPCODE_LOD_LOGICAL:
> @@ -712,6 +713,9 @@ fs_inst::components_read(unsigned i) const
> /* Texture offset. */
> else if (i == 7)
> return 2;
> + /* MCS */
> + else if (i == 5 && opcode == SHADER_OPCODE_TXF_CMS_W_LOGICAL)
> + return 2;
> else
> return 1;
>
> @@ -873,6 +877,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
> case SHADER_OPCODE_TXD:
> case SHADER_OPCODE_TXF:
> case SHADER_OPCODE_TXF_CMS:
> + case SHADER_OPCODE_TXF_CMS_W:
> case SHADER_OPCODE_TXF_MCS:
> case SHADER_OPCODE_TG4:
> case SHADER_OPCODE_TG4_OFFSET:
> @@ -3816,17 +3821,31 @@ lower_sampler_logical_send_gen7(const fs_builder
> &bld, fs_inst *inst, opcode op,
> coordinate_done = true;
> break;
> case SHADER_OPCODE_TXF_CMS:
> + case SHADER_OPCODE_TXF_CMS_W:
> case SHADER_OPCODE_TXF_UMS:
> case SHADER_OPCODE_TXF_MCS:
> - if (op == SHADER_OPCODE_TXF_UMS || op == SHADER_OPCODE_TXF_CMS) {
> + if (op == SHADER_OPCODE_TXF_UMS ||
> + op == SHADER_OPCODE_TXF_CMS ||
> + op == SHADER_OPCODE_TXF_CMS_W) {
> bld.MOV(retype(sources[length], BRW_REGISTER_TYPE_UD),
> sample_index);
> length++;
> }
>
> - if (op == SHADER_OPCODE_TXF_CMS) {
> + if (op == SHADER_OPCODE_TXF_CMS || op == SHADER_OPCODE_TXF_CMS_W) {
> /* Data from the multisample control surface. */
> bld.MOV(retype(sources[length], BRW_REGISTER_TYPE_UD), mcs);
> length++;
> +
> + /* On Gen9+ we'll use lcd2ms_w instead which has two registers for
> + * the MCS data.
> + */
> + if (op == SHADER_OPCODE_TXF_CMS_W) {
> + bld.MOV(retype(sources[length], BRW_REGISTER_TYPE_UD),
> + mcs.file == IMM ?
> + mcs :
> + offset(mcs, bld, 1));
> + length++;
> + }
This hunk is very confusing to me without more context from later patches. I
assume the upper bits of mcs are 0 for the cases where you're doing < 16x, but
there is no way to determine that. I am not a big fan of the, lay out all the
infrastructure, then use it later, when it comes to patch review. Or am I
missing something?
(Also, I think a separate case for SHADER_OPCODE_TXF_CMS_W would probably look a
bit nicer, but that's just a random thought).
> }
>
> /* There is no offsetting for this message; just copy in the integer
> @@ -4040,6 +4059,10 @@ fs_visitor::lower_logical_sends()
> lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_CMS);
> break;
>
> + case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
> + lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_CMS_W);
> + break;
> +
> case SHADER_OPCODE_TXF_UMS_LOGICAL:
> lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_UMS);
> break;
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index 90805e4..d3e3e05 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -612,6 +612,10 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg
> dst, struct brw_reg src
> case SHADER_OPCODE_TXF:
> msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
> break;
> + case SHADER_OPCODE_TXF_CMS_W:
> + assert(devinfo->gen >= 9);
> + msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
> + break;
> case SHADER_OPCODE_TXF_CMS:
> if (devinfo->gen >= 7)
> msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
> @@ -1916,6 +1920,7 @@ fs_generator::generate_code(const cfg_t *cfg, int
> dispatch_width)
> case SHADER_OPCODE_TXD:
> case SHADER_OPCODE_TXF:
> case SHADER_OPCODE_TXF_CMS:
> + case SHADER_OPCODE_TXF_CMS_W:
> case SHADER_OPCODE_TXF_UMS:
> case SHADER_OPCODE_TXF_MCS:
> case SHADER_OPCODE_TXL:
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> index b85b52b..ea7b3eb 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> @@ -200,8 +200,8 @@ fs_visitor::emit_mcs_fetch(const fs_reg &coordinate,
> unsigned components,
> fs_inst *inst = bld.emit(SHADER_OPCODE_TXF_MCS_LOGICAL, dest, srcs,
> ARRAY_SIZE(srcs));
>
> - /* We only care about one reg of response, but the sampler always writes
> - * 4/8.
> + /* We only care about one or two regs of response, but the sampler always
> + * writes 4/8.
> */
> inst->regs_written = 4 * dispatch_width / 8;
>
> @@ -287,7 +287,10 @@ fs_visitor::emit_texture(ir_texture_opcode op,
> opcode = SHADER_OPCODE_TXF_LOGICAL;
> break;
> case ir_txf_ms:
> - opcode = SHADER_OPCODE_TXF_CMS_LOGICAL;
> + if (devinfo->gen >= 9)
> + opcode = SHADER_OPCODE_TXF_CMS_W_LOGICAL;
> + else
> + opcode = SHADER_OPCODE_TXF_CMS_LOGICAL;
> break;
> case ir_txs:
> case ir_query_levels:
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
> b/src/mesa/drivers/dri/i965/brw_shader.cpp
> index eed73fb..1e1ea9f 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
> @@ -607,6 +607,10 @@ brw_instruction_name(enum opcode op)
> return "txf_cms";
> case SHADER_OPCODE_TXF_CMS_LOGICAL:
> return "txf_cms_logical";
> + case SHADER_OPCODE_TXF_CMS_W:
> + return "txf_cms_w";
> + case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
> + return "txf_cms_w_logical";
> case SHADER_OPCODE_TXF_UMS:
> return "txf_ums";
> case SHADER_OPCODE_TXF_UMS_LOGICAL:
> @@ -1034,6 +1038,7 @@ backend_instruction::is_tex() const
> opcode == SHADER_OPCODE_TXD ||
> opcode == SHADER_OPCODE_TXF ||
> opcode == SHADER_OPCODE_TXF_CMS ||
> + opcode == SHADER_OPCODE_TXF_CMS_W ||
> opcode == SHADER_OPCODE_TXF_UMS ||
> opcode == SHADER_OPCODE_TXF_MCS ||
> opcode == SHADER_OPCODE_TXL ||
> --
> 1.9.3
>
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