On 20.03.2018 23:11, Lionel Landwerlin wrote:
This is the equivalent of commit 5770e1d89e0eb49eb3c9547e8657d636b6e7e5d7 for
android.
Signed-off-by: Lionel Landwerlin
Fixes: 2d2b15fbcab ("i965: fix autotools/android build")
---
src/mesa/drivers/dri/i965/Android.mk | 5 -
1 file changed,
From: Lionel Landwerlin
This is the equivalent of commit 5770e1d89e0eb49eb3c9547e8657d636b6e7e5d7 for
android.
v2: fix xml files path and file given to --header
Signed-off-by: Lionel Landwerlin
Signed-off-by: Tapani Pälli
Fixes: 2d2b15fbcab ("i965: fix autotools/android build")
---
src/mesa/
On Tuesday, March 20, 2018 11:10:11 AM PDT Lionel Landwerlin wrote:
> On 20/03/18 00:08, Kenneth Graunke wrote:
> > On Wednesday, March 14, 2018 10:19:11 AM PDT Lionel Landwerlin wrote:
> >> + devinfo->num_slices = __builtin_popcount(devinfo->slice_masks);
> > _mesa_bitcount() here and elsewhere.
When sending this I did not realize there are also other patches in list
... hopefully this makes sense. Anyway, this fixes issues for me and
build is fine on Android.
On 21.03.2018 09:15, Tapani Pälli wrote:
From: Lionel Landwerlin
This is the equivalent of commit 5770e1d89e0eb49eb3c9547e86
On Tuesday, 2018-03-20 13:39:25 -0700, Scott D Phillips wrote:
> When building intel_tiled_memcpy for i686, the stack will only be
> 4-byte aligned. This isn't sufficient for SSE temporaries which
> require 16-byte alignment. Use the force_align_arg_pointer
> function attribute in that case to ens
On 21.03.2018 08:52, Alejandro Piñeiro wrote:
On 21/03/18 06:57, Lin Johnson wrote:
Ext_color_buffer_half_float is using type GL_HALF_FLOAT
and data_type GL_FLOAT. This fix Android CTS test android.view.cts.PixelCopyTest
#TestWindowProducerCopyToRGBA16F
Signed-off-by: Lin Johnson
---
src/m
On 21.03.2018 12:45, Tapani Pälli wrote:
On 21.03.2018 08:52, Alejandro Piñeiro wrote:
On 21/03/18 06:57, Lin Johnson wrote:
Ext_color_buffer_half_float is using type GL_HALF_FLOAT
and data_type GL_FLOAT. This fix Android CTS test
android.view.cts.PixelCopyTest
#TestWindowProducerCopyToRG
Oops, sorry.
Reviewed-by: Pierre Moreau
Thanks again for the series!
Pierre
On 2018-03-20 — 20:23, Aaron Watry wrote:
> ping.
>
> This is the last of the series that still needs review.
>
> --Aaron
>
> On Thu, Mar 1, 2018 at 1:39 PM, Aaron Watry wrote:
> > Use get_language_version to calcul
If it works for you & the CI, go for it.
I only tested my patch on the CI.
Thanks!
-
Lionel
On 21/03/18 07:32, Tapani Pälli wrote:
When sending this I did not realize there are also other patches in
list ... hopefully this makes sense. Anyway, this fixes issues for me
and build is fine on And
On 21 March 2018 at 02:07, Rob Clark wrote:
> On Tue, Mar 20, 2018 at 2:45 PM, Emil Velikov
> wrote:
>> On 20 March 2018 at 18:02, Christian Gmeiner
>> wrote:
>>> Fixes rendering issues with mode rgba on etnaviv. I have applied
>>> the same change for nv12 variants but they are not supported on
On 19/03/18 23:34, Kenneth Graunke wrote:
On Wednesday, March 14, 2018 10:19:07 AM PDT Lionel Landwerlin wrote:
This will be reused to store values reported by the kernel. The main
use case will be for use as the input values of the metric sets
equations for the INTEL_performance_queries extensi
Eric, can I get this R-b by you?
J.A.
On Tue, 2018-03-20 at 15:53 +0100, Juan A. Suarez Romero wrote:
> Build vulkan/wsi/wayland if Wayland platform is enabled.
>
> v2: fix comparison with default fallback (Eric)
>
> CC: Daniel Stone
> Fixes: bfa22266cd4d ("vulkan/wsi/wayland: Add sup
On Wednesday, 2018-03-21 14:10:57 +0100, Juan A. Suarez Romero wrote:
> Eric, can I get this R-b by you?
This looks sensible, but I don't know enough about how/when the wayland
bits are built, especially under autotools
Acked-by: Eric Engestrom
>
>
> J.A.
>
> On Tue, 2018-03-20 at 15:5
Hi Juan,
On 19 March 2018 at 17:49, Juan A. Suarez Romero wrote:
> The first two patches in the series is a new fix for issue
> https://bugs.freedesktop.org/show_bug.cgi?id=105211, as the current version
> breaks when running the above command, due "make dist/distcheck" tries to
> generate the th
On 21 March 2018 at 07:15, Tapani Pälli wrote:
> From: Lionel Landwerlin
>
> This is the equivalent of commit 5770e1d89e0eb49eb3c9547e8657d636b6e7e5d7 for
> android.
>
> v2: fix xml files path and file given to --header
>
> Signed-off-by: Lionel Landwerlin
> Signed-off-by: Tapani Pälli
> Fixes:
Hi,
Here are a few more changes after Ken's review. It's mostly all
reviewed except patches : 2, 3 & 5.
Thanks a lot,
Lionel Landwerlin (8):
intel: devinfo: store number of EUs per subslice
intel: devinfo: store slice/subslice/eu masks
drm-uapi: bump headers
intel: devinfo: meson: includ
This will be reused to store values reported by the kernel. The main
use case will be for use as the input values of the metric sets
equations for the INTEL_performance_queries extension. By storing this
information in the gen_device_info we make this non GL specific so
this can be reused by Vulkan
We want to store values coming from the kernel but as a first step, we
can generate mask values out the numbers already stored in the
gen_device_info masks.
v2: Add a helper to set EU masks (Lionel/Ken)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Kenneth Graunke
---
src/intel/dev/gen_device_
Required updates from drm-next for changes in i965.
Signed-off-by: Lionel Landwerlin
---
include/drm-uapi/README | 8 +--
include/drm-uapi/drm_mode.h | 43 +---
include/drm-uapi/i915_drm.h | 152 +--
include/drm-uapi/tegra_drm.h | 22 +--
There are a couple of ways we can get the fusing information from the
kernel :
- Through DRM_I915_GETPARAM with the SLICE_MASK/SUBSLICE_MASK
parameters
- Through the new DRM_IOCTL_I915_QUERY by requesting the
DRM_I915_QUERY_TOPOLOGY_INFO
The second method is more accurate and also gi
Some equations of the CNL metrics started to use operators we haven't
defined yet, just add those.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_oa.py | 15 +++
1 file changed, 15 insertions(+)
diff --git a/src/mesa/drivers/dri/i965
With the introduction of asymmetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available.
We introduce a new uAPI in the kernel driver to report exactly what
part of the GPU are fused and require this to be available on Gen10+.
Prior
Already available with the autotools build.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Kenneth Graunke
---
src/intel/dev/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/dev/meson.build b/src/intel/dev/meson.build
index 3346fe60c07..9369fd3c0da 100644
Ping.
On 03/19/2018 01:11 PM, Leo Liu wrote:
On the CI family, firmware requires the destory command have to be the
last command in the IB, moving feedback command after destroy is causing
issues on CI cards, so we have to keep the previous logic that moves
destroy back to the last command.
Bu
Can't 100% judge if that is correct, but on first glance it seems to
make sense.
Patch is Acked-by: Christian König .
Regards,
Christian.
Am 21.03.2018 um 15:22 schrieb Leo Liu:
Ping.
On 03/19/2018 01:11 PM, Leo Liu wrote:
On the CI family, firmware requires the destory command have to be
On 03/21/2018 10:25 AM, Christian König wrote:
Can't 100% judge if that is correct, but on first glance it seems to
make sense.
It all depends on how firmware handle it. The only thing we could do is
to verify on different generation of HW as much as possible.
Thanks,
Leo
Patch is Acked-
From: Khem Raj
endianness check is OS wide and not specific to libc.
Fixes build with musl libc
Signed-off-by: Khem Raj
Signed-off-by: Maxin B. John
---
src/util/u_endian.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/util/u_endian.h b/src/util/u_endian.h
index 22d0
The fifth and final release candidate for Mesa 18.0.0 is now available.
Modulo serious regressions, it is anticipated that it will become
Mesa 18.0.0 this Friday around 16:00GMT
Alex Smith (1):
radv: Fix CmdCopyImage between uncompressed and compressed images
Andres Gomez (2):
travi
Hi Maxin,
Welcome back ;-)
On 21 March 2018 at 14:52, wrote:
> From: Khem Raj
>
> endianness check is OS wide and not specific to libc.
> Fixes build with musl libc
>
> Signed-off-by: Khem Raj
> Signed-off-by: Maxin B. John
> ---
> src/util/u_endian.h | 2 +-
> 1 file changed, 1 insertion(+
Hey,
I've started looking into removing the gralloc method
GRALLOC_MODULE_PERFORM_GET_DRM_FD.
The issues around this seems to be two parts:
1) Finding the right device to open
2) Sharing the device between components
Finding the right device to open
Using a
Chris Wilson writes:
> Quoting Scott D Phillips (2018-03-20 20:39:25)
>> When building intel_tiled_memcpy for i686, the stack will only be
>> 4-byte aligned. This isn't sufficient for SSE temporaries which
>> require 16-byte alignment. Use the force_align_arg_pointer
>> function attribute in tha
Let's handle 16-bit while we're at it.
On Thu, Mar 8, 2018 at 8:07 AM, Neil Roberts wrote:
> The only change neccessary is to change the type of the constant used
> to compare against.
>
> This has been tested against the arb_gpu_shader_fp64/execution/
> fs-isinf-dvec tests using the ARB_gl_spir
On Wed, Mar 21, 2018 at 8:18 AM, Jason Ekstrand
wrote:
> Let's handle 16-bit while we're at it.
>
In particular, why not just create a nir_imm_floatN_t helper similar to the
nir_imm_intN_t helper I added not too long ago. It would take a double and
automatically convert to float or float16 (via
Mesa 17.3.7 is now available.
In this release we have:
The i965 receives quite a few of fixes. We have fixes for hangs on GFXBench 5's
Aztec Ruins benchmark, a fix for OpenGL CTS test in Haswell, another fix for the
number of input components, a fix for KHR_blend_equation_advanced, another fix
in
Title is about 17.3.5, when it must be about 17.3.6.
CC: Emil Velikov
---
docs/relnotes/17.3.6.html | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/relnotes/17.3.6.html b/docs/relnotes/17.3.6.html
index 0dd1097975..de8518aacd 100644
--- a/docs/relnotes/17.3.6.html
+++ b/
On 21 March 2018 at 16:33, Juan A. Suarez Romero wrote:
> Title is about 17.3.5, when it must be about 17.3.6.
>
Reviewed-by: Emil Velikov
Thanks
Emil
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listi
On Wednesday, 2018-03-21 17:33:36 +0100, Juan A. Suarez Romero wrote:
> Title is about 17.3.5, when it must be about 17.3.6.
>
> CC: Emil Velikov
Reviewed-by: Eric Engestrom
> ---
> docs/relnotes/17.3.6.html | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/docs/relnot
On 21/03/2018 15:09, Emil Velikov wrote:
Hi Maxin,
Welcome back ;-)
On 21 March 2018 at 14:52, wrote:
From: Khem Raj
endianness check is OS wide and not specific to libc.
Fixes build with musl libc
Signed-off-by: Khem Raj
Signed-off-by: Maxin B. John
---
src/util/u_endian.h | 2 +-
1
Hi Emil,
On Wed, Mar 21, 2018 at 5:09 PM, Emil Velikov wrote:
> Hi Maxin,
>
> Welcome back ;-)
Thanks :)
>
> On 21 March 2018 at 14:52, wrote:
>> From: Khem Raj
>>
>> endianness check is OS wide and not specific to libc.
>> Fixes build with musl libc
>>
>> Signed-off-by: Khem Raj
>> Signed-o
On Tue, 2018-03-20 at 20:23 -0500, Aaron Watry wrote:
> ping.
>
> This is the last of the series that still needs review.
Hi,
sorry for the delay. I once again really dislike the approach of
implement and enable in separate patches, because it breaks bisection
(I think 4 and 5 should be squashed
On Thu, Mar 8, 2018 at 8:07 AM, Neil Roberts wrote:
> The implementation is inspired by
> lower_instructions_visitor::dfrexp_sig_to_arith.
>
> This has been tested against the arb_gpu_shader_fp64/fs-frexp-dvec4
> test using the ARB_gl_spirv branch.
> ---
>
> Please also see this related patch whi
GTF-GLES3.gtf.GL3Tests.instanced_arrays.instanced_arrays_divisor uses -1
as a divisor, so we would overflow to count=0 and upload no data,
triggering the assert below. We want to upload 1 element in this case,
fixing the test on VC5.
---
src/gallium/auxiliary/util/u_vbuf.c | 7 ++-
1 file cha
Cc: Maxin B. John
Cc: Khem Raj
Suggested-by: Jon Turney
Signed-off-by: Eric Engestrom
---
configure.ac| 1 +
meson.build | 2 +-
src/util/u_endian.h | 2 +-
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/configure.ac b/configure.ac
index 29d3c3457a7cdaefc36a..36
On Wed, Mar 21, 2018 at 2:39 AM, Eric Engestrom
wrote:
> On Tuesday, 2018-03-20 13:39:25 -0700, Scott D Phillips wrote:
>> When building intel_tiled_memcpy for i686, the stack will only be
>> 4-byte aligned. This isn't sufficient for SSE temporaries which
>> require 16-byte alignment. Use the for
Quoting Jon Turney (2018-03-21 09:47:23)
> On 21/03/2018 15:09, Emil Velikov wrote:
> > Hi Maxin,
> >
> > Welcome back ;-)
> >
> > On 21 March 2018 at 14:52, wrote:
> >> From: Khem Raj
> >>
> >> endianness check is OS wide and not specific to libc.
> >> Fixes build with musl libc
> >>
> >> Sig
On Wednesday, 2018-03-21 10:11:55 -0700, Dylan Baker wrote:
> Quoting Jon Turney (2018-03-21 09:47:23)
> > On 21/03/2018 15:09, Emil Velikov wrote:
> > > Hi Maxin,
> > >
> > > Welcome back ;-)
> > >
> > > On 21 March 2018 at 14:52, wrote:
> > >> From: Khem Raj
> > >>
> > >> endianness check is
From: Marek Olšák
---
src/mesa/state_tracker/st_draw.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/state_tracker/st_draw.c b/src/mesa/state_tracker/st_draw.c
index b95a2522b2e..73f936bb4a9 100644
--- a/src/mesa/state_tracker/st_draw.c
+++ b/src/mesa/state_tracker/st_draw.
Quoting Eric Engestrom (2018-03-21 10:09:17)
> Cc: Maxin B. John
> Cc: Khem Raj
> Suggested-by: Jon Turney
> Signed-off-by: Eric Engestrom
> ---
> configure.ac| 1 +
> meson.build | 2 +-
> src/util/u_endian.h | 2 +-
> 3 files changed, 3 insertions(+), 2 deletions(-)
>
> diff
On 21 March 2018 at 17:09, Eric Engestrom wrote:
> Cc: Maxin B. John
> Cc: Khem Raj
> Suggested-by: Jon Turney
> Signed-off-by: Eric Engestrom
> ---
> configure.ac| 1 +
> meson.build | 2 +-
> src/util/u_endian.h | 2 +-
> 3 files changed, 3 insertions(+), 2 deletions(-)
>
>
On Wednesday, 2018-03-21 10:45:35 -0700, Dylan Baker wrote:
> Quoting Eric Engestrom (2018-03-21 10:09:17)
> > Cc: Maxin B. John
> > Cc: Khem Raj
> > Suggested-by: Jon Turney
> > Signed-off-by: Eric Engestrom
> > ---
> > configure.ac| 1 +
> > meson.build | 2 +-
> > src/util/u
On Wednesday, 2018-03-21 17:54:02 +, Eric Engestrom wrote:
> On Wednesday, 2018-03-21 10:45:35 -0700, Dylan Baker wrote:
> > Quoting Eric Engestrom (2018-03-21 10:09:17)
> > > Cc: Maxin B. John
> > > Cc: Khem Raj
> > > Suggested-by: Jon Turney
> > > Signed-off-by: Eric Engestrom
> > > ---
>
On 21 March 2018 at 17:54, Eric Engestrom wrote:
> On Wednesday, 2018-03-21 10:45:35 -0700, Dylan Baker wrote:
>> Quoting Eric Engestrom (2018-03-21 10:09:17)
>> > Cc: Maxin B. John
>> > Cc: Khem Raj
>> > Suggested-by: Jon Turney
>> > Signed-off-by: Eric Engestrom
>> > ---
>> > configure.ac
On Tue, Mar 20, 2018 at 9:26 AM, Tomasz Figa wrote:
> On Wed, Mar 21, 2018 at 12:58 AM, Emil Velikov
> wrote:
>> On 20 March 2018 at 14:24, Tomasz Figa wrote:
>>> On Tue, Mar 20, 2018 at 10:44 PM, Emil Velikov
>>> wrote:
On 20 March 2018 at 04:40, Tomasz Figa wrote:
> On Tue, Mar 20
On Wednesday, 2018-03-21 17:53:08 +, Emil Velikov wrote:
> On 21 March 2018 at 17:09, Eric Engestrom wrote:
> > Cc: Maxin B. John
> > Cc: Khem Raj
> > Suggested-by: Jon Turney
> > Signed-off-by: Eric Engestrom
> > ---
> > configure.ac| 1 +
> > meson.build | 2 +-
> > src/
On Wednesday, 2018-03-21 10:11:45 -0700, Matt Turner wrote:
> On Wed, Mar 21, 2018 at 2:39 AM, Eric Engestrom
> wrote:
> > On Tuesday, 2018-03-20 13:39:25 -0700, Scott D Phillips wrote:
> >> When building intel_tiled_memcpy for i686, the stack will only be
> >> 4-byte aligned. This isn't sufficien
https://bugs.freedesktop.org/show_bug.cgi?id=105240
Hleb Valoshka <375...@gmail.com> changed:
What|Removed |Added
Assignee|dri-devel@lists.freedesktop |mesa-dev@lists.freedes
https://bugs.freedesktop.org/show_bug.cgi?id=105240
--- Comment #1 from Hleb Valoshka <375...@gmail.com> ---
Works on Devuan 2 (Debian 9) with Linux 4.9 and 4.15 and Mesa 13.0.6, so I
assume that the problem is in Mesa.
--
You are receiving this mail because:
You are the assignee for the bug.___
---
src/intel/genxml/gen10.xml | 18 ++
src/intel/genxml/gen11.xml | 18 ++
src/intel/genxml/gen7.xml | 20
src/intel/genxml/gen75.xml | 22 ++
src/intel/genxml/gen8.xml | 18 ++
src/intel/genxml/gen9.xml |
Decode SC_INSTDONE, ROW_INSTDONE and SAMPLER_INSTDONE.
---
src/intel/tools/aubinator_error_decode.c | 12
1 file changed, 12 insertions(+)
diff --git a/src/intel/tools/aubinator_error_decode.c
b/src/intel/tools/aubinator_error_decode.c
index db880d74a9e..9abd05fd75a 100644
--- a/src
---
src/intel/genxml/gen10.xml | 23 +++
src/intel/genxml/gen11.xml | 23 +++
src/intel/genxml/gen7.xml | 22 ++
src/intel/genxml/gen75.xml | 25 +
src/intel/genxml/gen8.xml | 23 +++
src/inte
---
src/intel/genxml/gen10.xml | 27 +++
src/intel/genxml/gen11.xml | 27 +++
src/intel/genxml/gen7.xml | 19 +++
src/intel/genxml/gen75.xml | 17 +
src/intel/genxml/gen8.xml | 24
src/intel/
Quoting Emil Velikov (2018-03-21 10:57:09)
> On 21 March 2018 at 17:54, Eric Engestrom wrote:
> > On Wednesday, 2018-03-21 10:45:35 -0700, Dylan Baker wrote:
> >> Quoting Eric Engestrom (2018-03-21 10:09:17)
> >> > Cc: Maxin B. John
> >> > Cc: Khem Raj
> >> > Suggested-by: Jon Turney
> >> > Sig
Quoting Emil Velikov (2018-03-21 10:53:08)
> On 21 March 2018 at 17:09, Eric Engestrom wrote:
> > Cc: Maxin B. John
> > Cc: Khem Raj
> > Suggested-by: Jon Turney
> > Signed-off-by: Eric Engestrom
> > ---
> > configure.ac| 1 +
> > meson.build | 2 +-
> > src/util/u_endian.h |
On March 21, 2018 6:47:48 PM UTC, Dylan Baker wrote:
> Quoting Emil Velikov (2018-03-21 10:53:08)
> > On 21 March 2018 at 17:09, Eric Engestrom
> wrote:
> > > Cc: Maxin B. John
> > > Cc: Khem Raj
> > > Suggested-by: Jon Turney
> > > Signed-off-by: Eric Engestrom
> > > ---
> > > configure.a
This adds support for doubles in some of the builtin functions. The
last two patches have been posted already and are a v2 based on
Jason’s feedback.
These patches come out of testing using the ARB_gl_spirv branch of
Mesa and Piglit. However they also affect Vulkan and can be tested
with VkRunner
This lets you easily build float immediates just given the bit size.
If we have this single place here to handle this then it will be
easier to add support for 16-bit floats later.
---
src/compiler/nir/nir_builder.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/compiler/ni
There is an existing macro that is used to choose between either a
float or a double immediate constant based on the bit size of the
first operand to the builtin. This is now changed to use the new
nir_imm_floatN_t helper function to reduce the number of places that
make this decision.
---
src/com
The only change neccessary is to change the type of the constant used
to compare against.
This has been tested against the arb_gpu_shader_fp64/execution/
fs-isinf-dvec tests using the ARB_gl_spirv branch.
v2: Use nir_imm_floatN_t for the constant.
---
src/compiler/spirv/vtn_alu.c | 7 ---
1
The SPIR-V spec doesn’t specify a size requirement for these and the
equivalent functions in the GLSL spec have explicit alternatives for
doubles. Refract is a little bit more complicated due to the fact that
the final argument is always supposed to be a scalar 32- or 16- bit
float regardless of th
Aaron, this patch breaks the meson build-test in our CI:
../src/gallium/state_trackers/clover/llvm/invocation.cpp:88:36: error:
‘lang_opencl10’ is not a member of ‘clang::LangStandard’
{ 100, clang::LangStandard::lang_opencl10},
configured with:
meson -Dbuild-tests=true
-Dgallium-dri
On Wed, Mar 21, 2018 at 2:37 PM, Mark Janes wrote:
> Aaron, this patch breaks the meson build-test in our CI:
>
> ../src/gallium/state_trackers/clover/llvm/invocation.cpp:88:36: error:
> ‘lang_opencl10’ is not a member of ‘clang::LangStandard’
> { 100, clang::LangStandard::lang_opencl10
The hardware only supports 32-bit depth surfaces, but we can
enable TC-compat HTILE for 16-bit depth surfaces if no Z planes
are compressed.
The main benefit is to reduce the number of depth decompression
passes. Also, we don't need to implement DB->CB copies which is
fine.
This improves Serious
Instead of that huge conditional that's going to be crazy.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_image.c | 56 -
1 file changed, 45 insertions(+), 11 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 51
1 file changed, 37 insertions(+), 14 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 36ba0c3833..22500bfc13 100644
--- a/src/amd/vulkan/r
On 14 March 2018 at 20:13, Andres Gomez wrote:
> On Wed, 2018-03-14 at 16:02 +, Emil Velikov wrote:
>
> [...]
>>
>> Just double-checking:
>> I would suspect you're not suggesting removing the existing email/poke
>> scheme?
>
> Partially. The "announce" mail for the pre-branching period will s
On Wed, Mar 21, 2018 at 2:52 PM, Aaron Watry wrote:
> On Wed, Mar 21, 2018 at 2:37 PM, Mark Janes wrote:
>> Aaron, this patch breaks the meson build-test in our CI:
>>
>> ../src/gallium/state_trackers/clover/llvm/invocation.cpp:88:36: error:
>> ‘lang_opencl10’ is not a member of ‘clang::LangSta
There's nothing to worry about here -- the A channel just gets dropped by
the blit. This avoids a segfault in the fallback path when copying from a
RGBA16_SINT renderbuffer to a RGB16_SINT destination represented by an
RGBA16_SINT texture (the fallback path tries to get/fetch to float
buffers, but
We all know the platform names, and I don't want to update this list
continually.
---
src/intel/tools/aubinator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 8029dc12155..2a72efa8a2c 100644
--- a/src/intel/tool
From: Anuj Phogat
Disabling fast color clear makes fbo-clearmipmap test render correct
texture in base miplevel. Fast color clear is anyways disabled for
non-base miplevels.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i96
From: Anuj Phogat
When source or destination datatype is 64b or operation is integer
DWord multiply, DepCtrl must not be used.
We had this restriction on few previous intel platforms. It has been
brought back on Gen11+.
---
src/intel/compiler/brw_vec4.cpp | 8 ++--
1 file changed, 6 insertio
From: Jason Ekstrand
Otherwise all our render target writes go no where.
---
src/intel/compiler/brw_eu_emit.c | 3 +++
src/intel/compiler/brw_inst.h| 3 +++
2 files changed, 6 insertions(+)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index fe7fa8723e1..9
---
src/intel/compiler/test_eu_validate.cpp | 39 +
1 file changed, 39 insertions(+)
diff --git a/src/intel/compiler/test_eu_validate.cpp
b/src/intel/compiler/test_eu_validate.cpp
index 8169f951b2d..e36f50a2d7e 100644
--- a/src/intel/compiler/test_eu_validate.cpp
From: Anuj Phogat
On gen11+ AUX_HIZ is not a supported value for surfaces being
sampled by the 3D sampler.
---
src/intel/dev/gen_device_info.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index 3365bdd4dd6..9e684b78a09 1006
From: Anuj Phogat
ICL uses the same L3 configs as CNL, just leaving the SLM configs out.
---
src/intel/common/gen_l3_config.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index 7d58ad8d7c8..b977c6ab136
From: Anuj Phogat
---
include/pci_ids/i965_pci_ids.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index feb9c582b19..925655e9908 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -19
From Message Descriptor section in gfxspecs:
"Memory fence messages without Commit Enable set do not return
anything to the thread (response length is 0 and destination
register is null)."
This fixes a GPU hang in simulation in the piglit test
arb_shader_image_load_store-shader-mem-barrie
Now that the PCI IDs are upstream, this can be readded.
---
src/intel/compiler/test_eu_validate.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/compiler/test_eu_validate.cpp
b/src/intel/compiler/test_eu_validate.cpp
index e36f50a2d7e..79401222d78 100644
--- a/src/intel/compiler/
From: Anuj Phogat
Rafael ran piglit with the test code enabled and saw no additional GPU
hangs.
---
src/intel/compiler/brw_compiler.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_compiler.h
b/src/intel/compiler/brw_compiler.h
index 0e27c898203..d3ae
The opencl 1.0 langstandard was renamed in 5.0+
Cc: Mark Janes
---
src/gallium/state_trackers/clover/llvm/invocation.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/state_trackers/clover/llvm/invocation.cpp
b/src/gallium/state_trackers/clover/llvm/invocation.cpp
index af
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Wed, Mar 21, 2018 at 9:30 PM, Samuel Pitoiset
wrote:
> The hardware only supports 32-bit depth surfaces, but we can
> enable TC-compat HTILE for 16-bit depth surfaces if no Z planes
> are compressed.
>
> The main benefit is to reduce the number
On Wed, Mar 21, 2018 at 02:06:12PM -0700, Matt Turner wrote:
> We all know the platform names, and I don't want to update this list
> continually.
Reviewed-by: Rafael Antognolli
> ---
> src/intel/tools/aubinator.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/int
On Wed, Mar 21, 2018 at 02:06:14PM -0700, Matt Turner wrote:
> From: Anuj Phogat
>
> On gen11+ AUX_HIZ is not a supported value for surfaces being
> sampled by the 3D sampler.
Reviewed-by: Rafael Antognolli
> ---
> src/intel/dev/gen_device_info.c | 1 +
> 1 file changed, 1 insertion(+)
>
> d
Matches the bspec.
Reviewed-by: Rafael Antognolli
On Wed, Mar 21, 2018 at 02:06:20PM -0700, Matt Turner wrote:
> From: Anuj Phogat
>
> ---
> include/pci_ids/i965_pci_ids.h | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_
This patch fixes the clover build for Clang 4.0, which is what the Intel
CI uses.
Tested-by: Mark Janes
Aaron Watry writes:
> The opencl 1.0 langstandard was renamed in 5.0+
>
> Cc: Mark Janes
> ---
> src/gallium/state_trackers/clover/llvm/invocation.cpp | 4
> 1 file changed, 4 inserti
Aaron Watry writes:
> The opencl 1.0 langstandard was renamed in 5.0+
>
> Cc: Mark Janes
> ---
> src/gallium/state_trackers/clover/llvm/invocation.cpp | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/src/gallium/state_trackers/clover/llvm/invocation.cpp
> b/src/gallium/state_tracke
On Wednesday, March 21, 2018 2:06:12 PM PDT Matt Turner wrote:
> We all know the platform names, and I don't want to update this list
> continually.
> ---
> src/intel/tools/aubinator.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/intel/tools/aubinator.c b/src/intel
On Wednesday, March 21, 2018 2:06:18 PM PDT Matt Turner wrote:
> From: Anuj Phogat
>
> When source or destination datatype is 64b or operation is integer
> DWord multiply, DepCtrl must not be used.
> We had this restriction on few previous intel platforms. It has been
> brought back on Gen11+.
>
On Wednesday, March 21, 2018 2:06:19 PM PDT Matt Turner wrote:
> From: Anuj Phogat
>
> Disabling fast color clear makes fbo-clearmipmap test render correct
> texture in base miplevel. Fast color clear is anyways disabled for
> non-base miplevels.
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c | 4
On Wed, Mar 21, 2018 at 2:51 PM, Kenneth Graunke wrote:
> On Wednesday, March 21, 2018 2:06:18 PM PDT Matt Turner wrote:
>> From: Anuj Phogat
>>
>> When source or destination datatype is 64b or operation is integer
>> DWord multiply, DepCtrl must not be used.
>> We had this restriction on few pre
On Wednesday, March 21, 2018 2:06:17 PM PDT Matt Turner wrote:
> From: Jason Ekstrand
>
> Otherwise all our render target writes go no where.
> ---
> src/intel/compiler/brw_eu_emit.c | 3 +++
> src/intel/compiler/brw_inst.h| 3 +++
> 2 files changed, 6 insertions(+)
>
> diff --git a/src/int
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