[Mesa-dev] [PATCH 10/11] intel/compiler: Skip 64-bit type tests when types not available

[Matt Turner]

---
 src/intel/compiler/test_eu_validate.cpp | 39 +++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/src/intel/compiler/test_eu_validate.cpp 
b/src/intel/compiler/test_eu_validate.cpp
index 8169f951b2d..e36f50a2d7e 100644
--- a/src/intel/compiler/test_eu_validate.cpp
+++ b/src/intel/compiler/test_eu_validate.cpp
@@ -1075,6 +1075,15 @@ TEST_P(validation_test, 
qword_low_power_align1_regioning_restrictions)
       return;
 
    for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
+      if (!devinfo.has_64bit_types &&
+          (inst[i].dst_type == BRW_REGISTER_TYPE_DF ||
+           inst[i].dst_type == BRW_REGISTER_TYPE_UQ ||
+           inst[i].dst_type == BRW_REGISTER_TYPE_Q  ||
+           inst[i].src_type == BRW_REGISTER_TYPE_DF ||
+           inst[i].src_type == BRW_REGISTER_TYPE_UQ ||
+           inst[i].src_type == BRW_REGISTER_TYPE_Q))
+         continue;
+
       if (inst[i].opcode == BRW_OPCODE_MOV) {
          brw_MOV(p, retype(g0, inst[i].dst_type),
                     retype(g0, inst[i].src_type));
@@ -1195,6 +1204,15 @@ TEST_P(validation_test, 
qword_low_power_no_indirect_addressing)
       return;
 
    for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
+      if (!devinfo.has_64bit_types &&
+          (inst[i].dst_type == BRW_REGISTER_TYPE_DF ||
+           inst[i].dst_type == BRW_REGISTER_TYPE_UQ ||
+           inst[i].dst_type == BRW_REGISTER_TYPE_Q  ||
+           inst[i].src_type == BRW_REGISTER_TYPE_DF ||
+           inst[i].src_type == BRW_REGISTER_TYPE_UQ ||
+           inst[i].src_type == BRW_REGISTER_TYPE_Q))
+         continue;
+
       if (inst[i].opcode == BRW_OPCODE_MOV) {
          brw_MOV(p, retype(g0, inst[i].dst_type),
                     retype(g0, inst[i].src_type));
@@ -1331,6 +1349,15 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf)
       return;
 
    for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
+      if (!devinfo.has_64bit_types &&
+          (inst[i].dst_type == BRW_REGISTER_TYPE_DF ||
+           inst[i].dst_type == BRW_REGISTER_TYPE_UQ ||
+           inst[i].dst_type == BRW_REGISTER_TYPE_Q  ||
+           inst[i].src_type == BRW_REGISTER_TYPE_DF ||
+           inst[i].src_type == BRW_REGISTER_TYPE_UQ ||
+           inst[i].src_type == BRW_REGISTER_TYPE_Q))
+         continue;
+
       if (inst[i].opcode == BRW_OPCODE_MOV) {
          brw_MOV(p, retype(inst[i].dst, inst[i].dst_type),
                     retype(inst[i].src, inst[i].src_type));
@@ -1359,6 +1386,9 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf)
       clear_instructions(p);
    }
 
+   if (!devinfo.has_64bit_types)
+      return;
+
    /* MAC implicitly reads the accumulator */
    brw_MAC(p, retype(g0, BRW_REGISTER_TYPE_DF),
               retype(stride(g0, 4, 4, 1), BRW_REGISTER_TYPE_DF),
@@ -1529,6 +1559,15 @@ TEST_P(validation_test, qword_low_power_no_depctrl)
       return;
 
    for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
+      if (!devinfo.has_64bit_types &&
+          (inst[i].dst_type == BRW_REGISTER_TYPE_DF ||
+           inst[i].dst_type == BRW_REGISTER_TYPE_UQ ||
+           inst[i].dst_type == BRW_REGISTER_TYPE_Q  ||
+           inst[i].src_type == BRW_REGISTER_TYPE_DF ||
+           inst[i].src_type == BRW_REGISTER_TYPE_UQ ||
+           inst[i].src_type == BRW_REGISTER_TYPE_Q))
+         continue;
+
       if (inst[i].opcode == BRW_OPCODE_MOV) {
          brw_MOV(p, retype(g0, inst[i].dst_type),
                     retype(g0, inst[i].src_type));
-- 
2.16.1

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