On Mon, Jun 22, 2015 at 5:36 AM, Ilia Mirkin wrote:
> On Sun, Jun 21, 2015 at 11:33 PM, Michel Dänzer wrote:
>> On 22.06.2015 00:31, Ilia Mirkin wrote:
>>> On Sun, Jun 21, 2015 at 12:22 PM, Emil Velikov
>>> wrote:
On 20/06/15 10:01, Eirik Byrkjeflot Anonsen wrote:
> Ilia Mirkin writes
On Thu, Jun 04, 2015 at 05:35:11PM -0700, Ben Widawsky wrote:
> On Wed, Jun 03, 2015 at 09:32:55PM +0300, Pohjolainen, Topi wrote:
> > On Wed, Jun 03, 2015 at 09:21:11PM +0300, Topi Pohjolainen wrote:
> > > Shader programs are cached per stage (FS, VS, GS) using the
> > > corresponding shader sourc
On Mon, Jun 22, 2015 at 01:28:12PM +0300, Pohjolainen, Topi wrote:
> On Thu, Jun 04, 2015 at 05:35:11PM -0700, Ben Widawsky wrote:
> > On Wed, Jun 03, 2015 at 09:32:55PM +0300, Pohjolainen, Topi wrote:
> > > On Wed, Jun 03, 2015 at 09:21:11PM +0300, Topi Pohjolainen wrote:
> > > > Shader programs a
Should there be some clamping somewhere to prevent crashes due to
out-of-bound unit index?
In any case,
Reviewed-by: Roland Scheidegger
Am 22.06.2015 um 05:18 schrieb Dave Airlie:
> This is required for ARB_gpu_shader5 support in softpipe.
>
> v2: add support to txd/txf/txq paths.
>
> Signed-of
Ran multiple test cases multiple times that were introducing GPU hangs.
Applying this patch fixed the GPU hang issues on SKL.
Tested-by: Valtteri Rantala
> -Original Message-
> From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On Behalf
> Of Anuj Phogat
> Sent: Friday, June
On Mon, Jun 22, 2015 at 12:23:54PM +0200, Marek Olšák wrote:
> On Mon, Jun 22, 2015 at 5:36 AM, Ilia Mirkin wrote:
> > On Sun, Jun 21, 2015 at 11:33 PM, Michel Dänzer wrote:
> >> On 22.06.2015 00:31, Ilia Mirkin wrote:
> >>> On Sun, Jun 21, 2015 at 12:22 PM, Emil Velikov
> >>> wrote:
> On
On Mon, Jun 22, 2015 at 9:39 AM, Tom Stellard wrote:
> On Mon, Jun 22, 2015 at 12:23:54PM +0200, Marek Olšák wrote:
>> On Mon, Jun 22, 2015 at 5:36 AM, Ilia Mirkin wrote:
>> > On Sun, Jun 21, 2015 at 11:33 PM, Michel Dänzer wrote:
>> >> On 22.06.2015 00:31, Ilia Mirkin wrote:
>> >>> On Sun, Jun
On 19/06/15 23:09, Emil Velikov wrote:
On 19 June 2015 at 21:26, Jose Fonseca wrote:
On 19/06/15 20:56, Emil Velikov wrote:
Hi all,
A lovely series inspired (more like 'was awaken to send these out') by
Pal Rohár, who was having issues when building xlib-libgl (plus the now
enabled gles*)
S
Print GL_FLOAT, etc. instead of hex value.
---
src/mesa/main/varray.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
index 7389037..ebdd9ea 100644
--- a/src/mesa/main/varray.c
+++ b/src/mesa/main/varray.c
@@ -2309,10 +230
Hi,
On 06/18/2015 03:17 PM, Emil Velikov wrote:
Strange I was under the impression that there are apps that make use
of GS, albeit not too many.
So far I haven't seen any e.g. Steam game using GS, but Unreal Engine 4
demos:
https://wiki.unrealengine.com/Linux_Demos
use them. Of the
Reviewed-by: Ilia Mirkin
On Mon, Jun 22, 2015 at 10:33 AM, Brian Paul wrote:
> Print GL_FLOAT, etc. instead of hex value.
> ---
> src/mesa/main/varray.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
> index 73890
On 22.06.2015 15:41, Ilia Mirkin wrote:
On Mon, Jun 22, 2015 at 9:39 AM, Tom Stellard wrote:
On Mon, Jun 22, 2015 at 12:23:54PM +0200, Marek Olšák wrote:
On Mon, Jun 22, 2015 at 5:36 AM, Ilia Mirkin wrote:
On Sun, Jun 21, 2015 at 11:33 PM, Michel Dänzer wrote:
On 22.06.2015 00:31, Ilia Mir
This patch is
Reviewed-by: Ian Romanick
On 06/19/2015 06:08 AM, Jose Fonseca wrote:
> ---
> src/glsl/link_varyings.cpp | 12
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/src/glsl/link_varyings.cpp b/src/glsl/link_varyings.cpp
> index 7b2d4bd..278a778 100644
>
This seems believable... is there a piglit test?
On 06/17/2015 12:15 PM, Ilia Mirkin wrote:
> This allows mod(int, int) to become selected as float mod when doubles
> are supported.
>
> Signed-off-by: Ilia Mirkin
> Cc: "10.6"
> ---
> src/glsl/ir_function.cpp | 8 +---
> 1 file changed, 5 i
First, sorry for the late answer, I somehow missed your replies (I was
not in CC).
On mar, 2015-06-09 at 10:59 -0700, Ian Romanick wrote:
> On 06/09/2015 10:40 AM, Carl Worth wrote:
> > On Tue, Jun 09 2015, Ian Romanick wrote:
> >>> From section 3.4 ("Preprocessor") of the GLSL ES 3.00 specificati
On Mon, Jun 22, 2015 at 11:30 AM, Christian König
wrote:
> On 22.06.2015 15:41, Ilia Mirkin wrote:
>>
>> On Mon, Jun 22, 2015 at 9:39 AM, Tom Stellard wrote:
>>>
>>> On Mon, Jun 22, 2015 at 12:23:54PM +0200, Marek Olšák wrote:
On Mon, Jun 22, 2015 at 5:36 AM, Ilia Mirkin
wrote:
>>
http://patchwork.freedesktop.org/patch/52138/
I've already pushed this patch btw, Chris gave me a r-b over IRC. But
it seems I neglected to push the piglit patch, my bad.
On Mon, Jun 22, 2015 at 11:35 AM, Ian Romanick wrote:
> This seems believable... is there a piglit test?
>
> On 06/17/2015 12
Hi,
On 06/20/2015 03:32 PM, Timothy Arceri wrote:
The restrictions in ES make the extension easier to implement so
I thought I'd try get this stuff reviewed an committed before finishing
up the full extension.
The bits that I'm still working on for the desktop version are AoA inputs
outputs, and
On 06/19/2015 06:08 AM, Jose Fonseca wrote:
> When input and output varyings started to be counted separately (commit
> 42305fb5) the is_varying_var function wasn't updated to return true for
> output varyings or input varyings for stages other than the fragment
> shader), effectively making the va
https://bugs.freedesktop.org/show_bug.cgi?id=91044
--- Comment #1 from Emil Velikov ---
Based of the patch date (17 July 2012) and the extension revision history I'd
say that things were changed/nuked in Version 12 or later. With Version 15
being the prime suspect.
As Intel is a Khronos member,
I will happily remove the branch after the kernel driver lands.
I also wonder why all Mesa developers can force-push branches in Mesa
but not libdrm.
Marek
On Mon, Jun 22, 2015 at 5:39 PM, Ilia Mirkin wrote:
> On Mon, Jun 22, 2015 at 11:30 AM, Christian König
> wrote:
>> On 22.06.2015 15:41, I
On 06/22/2015 10:40 AM, Marek Olšák wrote:
> I will happily remove the branch after the kernel driver lands.
>
> I also wonder why all Mesa developers can force-push branches in Mesa
> but not libdrm.
That's probably just historical. We probably ought to restrict that on
Mesa as well.
It sounds
Niiice, thank you. For most drivers - gallium, i965 this is
implemented, leaving nouveau_vieux, radeon, r200 and i915. From these
i915 does work with EGL, while nouveau_vieux dies miserably (missing
__DRI_IMAGE v7 iirc). How well does radeon/r200 fair ?
So as a nice starter task one can, modify EG
We were not emitting the LOD, which led to message lengths of 1 instead
of 3. Setting has_lod makes us emit the LOD, but I had to make changes
to avoid emitting the non-existent coordinate as well.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91022
Cc: mesa-sta...@lists.freedesktop.org
It's not so important now that the amdgpu driver is about to be merged.
Speaking of other branches, I think removing the old feature branches
is a good idea.
Marek
On Mon, Jun 22, 2015 at 8:02 PM, Ian Romanick wrote:
> On 06/22/2015 10:40 AM, Marek Olšák wrote:
>> I will happily remove the bran
On 06/22/2015 07:01 AM, Jose Fonseca wrote:
> On 19/06/15 23:09, Emil Velikov wrote:
>> On 19 June 2015 at 21:26, Jose Fonseca wrote:
>>> On 19/06/15 20:56, Emil Velikov wrote:
Hi all,
A lovely series inspired (more like 'was awaken to send these out') by
Pal Rohár, who wa
Hi all,
As kindly hinted by Marek, currently we do have a wide selection of
supported dri <> loader combinations.
Although we like to think that things never break, we have to admit
that not many of us test every possible combinations of dri modules
and loaders. With the chances getting smaller a
Hi everyone,
I spent some time building Mesa/llvmpipe on Windows and created a Python
script
that implements all the required steps (downloading/extracting all
prerequisites and sources,
configuring and building LLVM and Mesa).
The script is available at:
https://github.com/florianlink/MesaOnWin
From: Ian Romanick
Commit b765119c changed the default value of all the counter bits to
64. However, older hardware only has 32 counter bits.
This has only been build-tested. We don't have any tests that verify
the advertised value against implementation behavior, so I don't know
what addition
Yes, I think we need to support every loader/driver combination, but
I'm not sure.
Ian, please how much do we care about compatibility between loaders
(libGL, libEGL) and DRI drivers?
Thanks,
Marek
On Mon, Jun 22, 2015 at 8:04 PM, Emil Velikov wrote:
> Niiice, thank you. For most drivers - gal
On 22 June 2015 at 15:01, Jose Fonseca wrote:
> On 19/06/15 23:09, Emil Velikov wrote:
>>
>> On 19 June 2015 at 21:26, Jose Fonseca wrote:
>>>
>>> On 19/06/15 20:56, Emil Velikov wrote:
Hi all,
A lovely series inspired (more like 'was awaken to send these out') by
Pa
>
> As kindly hinted by Marek, currently we do have a wide selection of
> supported dri <> loader combinations.
>
> Although we like to think that things never break, we have to admit
> that not many of us test every possible combinations of dri modules
> and loaders. With the chances getting small
On 22/06/15 19:40, Florian Link wrote:
Hi everyone,
I spent some time building Mesa/llvmpipe on Windows and created a Python
script
that implements all the required steps (downloading/extracting all
prerequisites and sources,
configuring and building LLVM and Mesa).
The script is available at:
On Sun, Jun 21, 2015 at 11:25 PM, Iago Toral wrote:
> On Fri, 2015-06-19 at 13:32 -0700, Anuj Phogat wrote:
>> On Thu, Jun 18, 2015 at 11:41 PM, Iago Toral wrote:
>> > On Thu, 2015-06-18 at 09:19 -0700, Anuj Phogat wrote:
>> >> On Thu, Jun 18, 2015 at 7:09 AM, Iago Toral wrote:
>> >> > On Tue, 2
Reviewed-by: Marek Olšák
For Gallium, a new PIPE_CAP or new get_xxx_param function will be needed.
Marek
On Mon, Jun 22, 2015 at 8:41 PM, Ian Romanick wrote:
> From: Ian Romanick
>
> Commit b765119c changed the default value of all the counter bits to
> 64. However, older hardware only has
On Thu 18 Jun 2015, Emil Velikov wrote:
> Hi Boyan,
>
> On 13 June 2015 at 08:33, Boyan Ding wrote:
> > The call to dri2_x11_add_configs_for_visuals (previously
> > dri2_add_configs_for_visuals) was moved downwards in commit f8c5b8a1,
> > but appeared again in its original position after its rena
This exposes a group of global performance counters that enables
GL_AMD_performance_monitor. All piglit tests are okay.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nv50/nv50_query.c | 35 ++
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 1 +
src/ga
This may happen when nv50_query_create() fails to create a new query.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nv50/nv50_query.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_query.c
b/src/gallium/
This will allow to monitor global performance counters through the
command stream of the GPU instead of using ioctls.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 11 +++
src/gallium/drivers/nouveau/nv50/nv50_screen.h | 1 +
src/gallium/drivers/nou
This notifier buffer object will be used to read back global performance
counters results written by the kernel.
For each domain, we will store the handle of the perfdom object, an
array of 4 counters and the number of cycles. Like the Gallium's HUD,
we keep a list of busy queries in a ring in ord
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nv50/nv50_query.c | 41 ++
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 1 +
src/gallium/drivers/nouveau/nv50/nv50_screen.h | 3 ++
3 files changed, 45 insertions(+)
diff --git a/src/gallium/drivers/nou
This commit adds support for both compute and graphics global
performance counters which have been reverse engineered with
CUPTI (Linux) and PerfKit (Windows).
Currently, only one query type can be monitored at the same time because
the Gallium's HUD doesn't fit pretty well. This will be improved
Hello there,
This series exposes NVIDIA's global performance counters for Tesla through the
Gallium's HUD and the GL_AMD_performance_monitor extension.
This adds support for 24 hardware events which have been reverse engineered
with PerfKit (Windows) and CUPTI (Linux). These hardware events will
To write data at the right offset, the kernel has to know some
parameters of this ring buffer, like the number of domains and the
maximum number of queries.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
This commit implements the base interface for hardware performance
counters that will be shared between nv50 and nvc0 drivers.
TODO: Bump libdrm version of mesa when nvif will be merged.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/Makefile.sources | 2 +
src/gallium/driver
If query_create fails, why would any of these functions get called?
On Mon, Jun 22, 2015 at 4:53 PM, Samuel Pitoiset
wrote:
> This may happen when nv50_query_create() fails to create a new query.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/gallium/drivers/nouveau/nv50/nv50_query.c | 15 +
On 06/22/2015 10:52 PM, Ilia Mirkin wrote:
If query_create fails, why would any of these functions get called?
Because the HUD doesn't check if query_create() fails and it calls other
pipe_query functions with NULL pointer instead of a valid query object.
On Mon, Jun 22, 2015 at 4:53 PM,
Matt, Jason, and I haven't found this useful in a long time.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_nir.c | 31 ---
1 file changed, 31 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
b/src/mesa/drivers/dri/i965/brw_nir.c
ind
Reviewed-by: Matt Turner
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
24-26 once again makes me wonder if these optimization *can* be used
with SSBOs based on the same ext spec wording I referenced before:
"The ability to write to buffer objects creates the potential for
multiple independent shader invocations to read and write the same
underlying memory. The same
For the series:
Reviewed-by: Roland Scheidegger
Am 22.06.2015 um 06:01 schrieb Dave Airlie:
> From: Dave Airlie
>
> This extends the draw code to add support for invocations.
>
> Signed-off-by: Dave Airlie
> ---
> src/gallium/auxiliary/draw/draw_gs.c| 3 ++-
> src/gallium/auxili
Reviewed-by: Jordan Justen
On 2015-06-03 00:01:17, Iago Toral Quiroga wrote:
> Shader storage buffer objects (SSBO) require special handling: when we
> detect writes to any channel of a shader buffer variable we need to
> emit the corresponding write to memory. We will later add a lowering pass
>
On Wed, Jun 10, 2015 at 03:30:47PM -0700, Anuj Phogat wrote:
> Buffers with Yf/Ys tiling end up using meta upload / download
> paths or the blitter for cases where they used tiled_memcpy paths
> in case of Y tiling. This has exposed some bugs in meta path. To
> avoid any piglit regressions on SKL t
We were initializing it in each subclasses' constructors for some
reason.
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 +---
src/mesa/drivers/dri/i965/brw_shader.cpp | 2 ++
src/mesa/drivers/dri/i965/brw_shader.h | 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 3 +--
Coverity sees that the functions immediately below the new assertions
dereference these pointers, but is unaware that an ENDIF always follows
an IF, etc.
---
src/mesa/drivers/dri/i965/brw_cfg.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_cfg.cpp
b/src/mes
Coverity sees the if (mode >= BRW_PRIM_OFFSET (128)) test and assumes
that the else-branch might execute for mode to up 127, which out be out
of bounds.
---
src/mesa/drivers/dri/i965/brw_draw.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_dra
I am shocked this is the only place we do this...
On Wed, Jun 10, 2015 at 03:30:48PM -0700, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> Cc: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/brw_tex_layout.c | 17 -
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff
1-4 (with/without changes) are:
Reviewed-by: Ben Widawsky
On Wed, Jun 10, 2015 at 03:30:49PM -0700, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> Cc: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/brw_tex_layout.c | 30
> +++---
> 1 file changed, 19 insertions(+),
If the stride is 0, the source is a uniform and we should not modify the
stride.
Cc: "10.6"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91047
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/src/mesa/dri
Can't find any uses of it in git history.
---
Strangely, when it was moved to its current location in commit 27558a1,
it was moved from mmath.h... which seems to have been lost from git's
history. Searching further git log --grep mmath.h shows that various
commit messages mention modifying mmath.h
Reviewed-by: Jordan Justen
On 2015-06-22 14:58:27, Matt Turner wrote:
> Can't find any uses of it in git history.
> ---
> Strangely, when it was moved to its current location in commit 27558a1,
> it was moved from mmath.h... which seems to have been lost from git's
> history. Searching further gi
On 06/22/2015 11:54 AM, Dave Airlie wrote:
>>
>> As kindly hinted by Marek, currently we do have a wide selection of
>> supported dri <> loader combinations.
>>
>> Although we like to think that things never break, we have to admit
>> that not many of us test every possible combinations of dri modu
On 23 June 2015 at 08:16, Ian Romanick wrote:
> On 06/22/2015 11:54 AM, Dave Airlie wrote:
>>>
>>> As kindly hinted by Marek, currently we do have a wide selection of
>>> supported dri <> loader combinations.
>>>
>>> Although we like to think that things never break, we have to admit
>>> that not
On Monday, June 22, 2015 02:58:36 PM Matt Turner wrote:
> If the stride is 0, the source is a uniform and we should not modify the
> stride.
>
> Cc: "10.6"
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91047
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 20
> 1 f
Series Reviewed-by: Jordan Justen
On 2015-06-22 14:56:06, Matt Turner wrote:
> Coverity sees that the functions immediately below the new assertions
> dereference these pointers, but is unaware that an ENDIF always follows
> an IF, etc.
> ---
> src/mesa/drivers/dri/i965/brw_cfg.cpp | 2 ++
> 1 f
From: Nanley Chery
Reviewed-by: Anuj Phogat
Signed-off-by: Nanley Chery
---
src/mesa/main/glformats.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index ac69fab..e7363b5 100644
--- a/src/mesa/main/glfor
From: Nanley Chery
Reviewed-by: Anuj Phogat
Signed-off-by: Nanley Chery
---
src/mesa/main/texcompress.c | 22 ++
src/mesa/main/teximage.c| 28
2 files changed, 50 insertions(+)
diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcom
From: Nanley Chery
v2: correct the spelling of the sRGB variants.
remove spaces around "=" when setting the enum value.
Reviewed-by: Anuj Phogat
Signed-off-by: Nanley Chery
---
.../glapi/gen/KHR_texture_compression_astc.xml | 40 ++
src/mapi/glapi/gen/Makefile.am
From: Nanley Chery
In agreement with the coding style, functions that aren't directly visible
to the GL API should prefer the use of bool over GLboolean.
Suggested-by: Ian Romanick
Signed-off-by: Nanley Chery
---
src/mesa/main/teximage.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletion
From: Nanley Chery
Reviewed-by: Anuj Phogat
Signed-off-by: Nanley Chery
---
src/mesa/main/texcompress.c | 114
1 file changed, 114 insertions(+)
diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 1654fc6..203a065 100644
--
From: Nanley Chery
v2: alphabetize the extensions.
remove OES ASTC extension.
Reviewed-by: Anuj Phogat
Signed-off-by: Nanley Chery
---
src/mesa/main/extensions.c | 2 ++
src/mesa/main/mtypes.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/src/mesa/main/extensions.c b/src/mesa
From: Nanley Chery
v2: remove extra newline.
v3: use bool instead of GLboolean.
Reviewed-by: Anuj Phogat
Signed-off-by: Nanley Chery
---
src/mesa/main/format_info.py | 2 ++
src/mesa/main/formats.c | 28
2 files changed, 6 insertions(+), 24 deletions(-)
dif
From: Nanley Chery
This patch series enables support for the KHR_texture_compression_astc_{ldr,hdr}
extensions on Skylake machines. This revision includes developer suggestions and
fixes rendering issues on previously untested systems. The sRGB issues were
fixed and determined to be unrelated to
From: Nanley Chery
Includes definition of the formats, updates to functions likely to be used, as
well as changes necessary for compilation.
Reviewed-by: Anuj Phogat
Signed-off-by: Nanley Chery
---
src/mesa/main/format_info.py | 3 +
src/mesa/main/formats.c | 130 ++
From: Nanley Chery
In agreement with commit 4ab8d59a23, vertical alignment values are equal to
four times the block height on Gen9+.
v2: add newlines to separate declarations, statments, and comments.
Reviewed-by: Anuj Phogat
Reviewed-by: Neil Roberts
Signed-off-by: Nanley Chery
---
src/mes
From: Nanley Chery
Remove redundant checks and comments by grouping our calculations for
align_w and align_h wherever possible.
v2: reintroduce brw.
don't include functional changes.
don't adjust function parameters or create a new function.
Signed-off-by: Nanley Chery
---
src/mesa/dr
From: Nanley Chery
ALIGN and ROUND_DOWN_TO both require that the alignment value passed
into the macro be a power of two in the comments. Using software assertions
verifies this to be the case.
v2: use static inline functions instead of gcc-specific statement expressions.
Signed-off-by: Nanley
From: Nanley Chery
This is necesary to initialize the gl_texture_image struct.
From the KHR_texture_compression_astc_ldr spec:
"Added to Section 3.8.6, Compressed Texture Images
Add the tokens specified above to Table 3.16, Compressed Internal Formats.
In all cases, the base internal fo
From: Nanley Chery
v2: remove OES ASTC extension reference.
Signed-off-by: Nanley Chery
---
src/mesa/drivers/dri/i965/intel_extensions.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 3
From: Nanley Chery
Aligning with a non-power-of-two number is a general task that can be used in
various places. This commit is required for the next one.
Signed-off-by: Nanley Chery
---
src/mesa/drivers/dri/i965/intel_upload.c | 6 --
src/mesa/main/macros.h | 6 ++
2
From: Nanley Chery
This patch creates a new macro, FETCH_COMPRESSED - similar in nature
to the other FETCH_* macros. This reduces repetition in the code that
deals with compressed textures.
Reviewed-by: Anuj Phogat
Signed-off-by: Nanley Chery
---
src/mesa/swrast/s_texfetch.c | 239 ---
From: Nanley Chery
ALIGN is changed to ALIGN_NPOT because alignment values are sometimes not
powers of two when working with ASTC.
Signed-off-by: Nanley Chery
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 12 ++--
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++--
2 files c
From: Nanley Chery
Intel surface formats default to LDR unless there is hardware
support for HDR and the texture is able to be processed in HDR mode.
v2: remove extra newlines.
v3: follow existing coding style in translate_tex_format().
Signed-off-by: Nanley Chery
---
src/mesa/drivers/dri/i96
From: Nanley Chery
An ASTC block takes up 16 bytes for all block width and height configurations.
This size is not integrally divisible by all ASTC block widths. Therefore cpp
is changed to mean bytes per block if the texture is compressed.
Because the original definition was bytes per block div
On 06/22/2015 05:02 PM, Nanley Chery wrote:
From: Nanley Chery
ALIGN and ROUND_DOWN_TO both require that the alignment value passed
into the macro be a power of two in the comments. Using software assertions
verifies this to be the case.
v2: use static inline functions instead of gcc-specific
On Wednesday, June 17, 2015 01:01:24 AM Marek Olšák wrote:
> From: Marek Olšák
>
> There is no way to lower them, because the array sizes are unknown
> at compile time.
>
> Based on a patch from: Fabian Bieler
I'm a bit confused by the justification given for this patch.
TCS/TES per-vertex in
On Wed, Jun 10, 2015 at 03:30:50PM -0700, Anuj Phogat wrote:
> In case of I915_TILING_{X,Y} we need to pass tiling format to libdrm
> using drm_intel_bo_alloc_tiled(). But, In case of YF/YS tiled buffers
> libdrm need not know about the tiling format because these buffers
> don't have hardware supp
On Mon, Jun 22, 2015 at 2:53 PM, Ben Widawsky wrote:
> On Wed, Jun 10, 2015 at 03:30:47PM -0700, Anuj Phogat wrote:
>> Buffers with Yf/Ys tiling end up using meta upload / download
>> paths or the blitter for cases where they used tiled_memcpy paths
>> in case of Y tiling. This has exposed some bu
On Thu, Jun 18, 2015 at 03:41:50PM -0700, Kenneth Graunke wrote:
> On Wednesday, June 17, 2015 03:50:13 PM Ben Widawsky wrote:
> > On gen9+ MOCS is an index into a table. It is 7 bits, and AFAICT, bit 0 is
> > for
> > doing encrypted reads.
> >
> > I don't recall how I decided to do this for BXT.
I started working on this project some time ago to remove brw_context from
the backend compiler. I got a bunch of refactoring done but eventualy got
stuck up on shader_time and some debug logging stuff. I've finally gotten
around to finishing it and here it is.
Jason Ekstrand (15):
i965: Repla
From: Kenneth Graunke
This will be useful for wrapper functions.
Signed-off-by: Kenneth Graunke
---
src/mesa/main/errors.c | 29 +
src/mesa/main/errors.h | 9 +
2 files changed, 30 insertions(+), 8 deletions(-)
diff --git a/src/mesa/main/errors.c b/src/mes
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_cs.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs.h| 4 +++-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp| 5 +++--
On Fri, Jun 19, 2015 at 02:41:50PM -0700, Anuj Phogat wrote:
> On Wed, Jun 10, 2015 at 3:34 PM, Anuj Phogat wrote:
> > This patch enables using XY_FAST_COPY_BLT only for Yf/Ys tiled buffers.
> > It can be later turned on for other tiling patterns (X,Y) too.
> >
> > V3: Flush in between sequential
Previously, each shader took 3 shader time indices which were potentially
at arbirary points in the shader time buffer. Now, each shader gets a
single index which refers to 3 consecutive locations in the buffer. This
simplifies some of the logic at the cost of having a magic 3 a few places.
---
---
src/mesa/drivers/dri/i965/brw_vec4_vp.cpp | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
index 92d1085..dcbd240 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
+++ b/src/
---
src/mesa/drivers/dri/i965/brw_cs.cpp | 8 +++-
src/mesa/drivers/dri/i965/brw_fs.cpp | 55 ---
src/mesa/drivers/dri/i965/brw_fs.h| 7 ++-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 7 ++-
src/mesa/drivers/dri/i965/brw_vec
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 8
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 5563c5a..ac65202 100644
--- a/src/
Previously, these were pulled out of the GL context conditionally based on
whether we were running ff/ARB or a GLSL program. Now, we just pass them
in so that the visitor doesn't have to grab them itself.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++--
src/mesa/drivers/dri/i965/b
This creates the options at screen cration time and then we just copy them
into the context at context creation time. We also move is_scalar to the
brw_compiler structure.
We also end up manually setting some values that the core would have set by
default for us. Fortunately, there are only two
While we're at it, we'll drop the note about 10-20% performance loss.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index a9d9f37..40e2c44 1006
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