Re: [Mesa-dev] [PATCH v2 12/28] glsl/ir: Add builtin constant function support for doubles

On 02/06/2015 06:56 AM, Ilia Mirkin wrote: > From: Dave Airlie > > Signed-off-by: Dave Airlie > --- > src/glsl/ir_constant_expression.cpp | 242 > +++- > 1 file changed, 210 insertions(+), 32 deletions(-) > > diff --git a/src/glsl/ir_constant_expression.cpp >

Re: [Mesa-dev] [PATCH v2 13/28] glsl/ir: Add builder support for functions with double floats

This patch is Reviewed-by: Ian Romanick On 02/06/2015 06:56 AM, Ilia Mirkin wrote: > From: Dave Airlie > > Signed-off-by: Dave Airlie > Reviewed-by: Matt Turner > --- > src/glsl/ir_builder.cpp | 23 +++ > src/glsl/ir_builder.h | 5 + > 2 files changed, 28 insertio

Re: [Mesa-dev] [PATCH v2 06/28] glsl: Add double builtin type

On Thu, Feb 05, 2015 at 11:56:28PM -0500, Ilia Mirkin wrote: > From: Dave Airlie > > This causes a lot of warnings about unchecked type in > switch statements - fix them later. The rest of the series fixes things in the compiler frontend but leaves a lot unchecked in the compiler backend (at lea

Re: [Mesa-dev] [PATCH v2 14/28] glsl: Add support doubles in optimization passes

Does opt_algebraic also need updates? On 02/06/2015 06:56 AM, Ilia Mirkin wrote: > From: Dave Airlie > > Signed-off-by: Dave Airlie > Reviewed-by: Matt Turner > --- > src/glsl/opt_constant_propagation.cpp | 3 +++ > src/glsl/opt_minmax.cpp | 13 + > 2 files changed,

Re: [Mesa-dev] [PATCH v2 15/28] glsl: Add ubo lowering support for doubles

On 02/06/2015 06:56 AM, Ilia Mirkin wrote: > From: Dave Airlie > > Signed-off-by: Dave Airlie > Reviewed-by: Matt Turner > --- > src/glsl/lower_ubo_reference.cpp | 12 +--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/src/glsl/lower_ubo_reference.cpp > b/src/gls

Re: [Mesa-dev] [PATCH v2 06/28] glsl: Add double builtin type

On Fri, Feb 06, 2015 at 10:04:13AM +0200, Pohjolainen, Topi wrote: > On Thu, Feb 05, 2015 at 11:56:28PM -0500, Ilia Mirkin wrote: > > From: Dave Airlie > > > > This causes a lot of warnings about unchecked type in > > switch statements - fix them later. > > The rest of the series fixes things in

Re: [Mesa-dev] [PATCH v2 16/28] glsl/ast: Support double floats

Three comments near the middle / bottom... On 02/06/2015 06:56 AM, Ilia Mirkin wrote: > From: Dave Airlie > > Signed-off-by: Dave Airlie > --- > src/glsl/ast.h | 2 ++ > src/glsl/ast_function.cpp | 67 > + > src/glsl/ast_to_hir.c

[Mesa-dev] [PATCH] i965: Add a function to disassemble an instruction from the 4 dwords.

I used this a while back when debugging GPU hangs, and it seems like it could be useful, so I figured I'd add it so people can use it in the debugger. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_disasm.c | 12 1 file changed, 12 insertions(+) From the clearing

Re: [Mesa-dev] [PATCH v2 17/28] glsl/parser: Support double floats

This patch is Reviewed-by: Ian Romanick On 02/06/2015 06:56 AM, Ilia Mirkin wrote: > From: Dave Airlie > > Signed-off-by: Dave Airlie > Reviewed-by: Matt Turner > --- > src/glsl/glsl_parser.yy | 33 + > 1 file changed, 29 insertions(+), 4 deletions(-) > > di

Re: [Mesa-dev] [PATCH v2 18/28] glsl/lexer: Support double floats

On 02/06/2015 06:56 AM, Ilia Mirkin wrote: > From: Dave Airlie > > Signed-off-by: Dave Airlie > --- > src/glsl/glsl_lexer.ll | 29 + > 1 file changed, 25 insertions(+), 4 deletions(-) > > diff --git a/src/glsl/glsl_lexer.ll b/src/glsl/glsl_lexer.ll > index 57c46be..

Re: [Mesa-dev] [PATCH v2 09/28] glsl/ir: Add builtin function support for doubles

On Thu, Feb 5, 2015 at 11:47 PM, Ian Romanick wrote: >> diff --git a/src/glsl/ir.h b/src/glsl/ir.h >> index a0f48b2..6e7c654 100644 >> --- a/src/glsl/ir.h >> +++ b/src/glsl/ir.h >> @@ -1275,6 +1275,13 @@ enum ir_expression_operation { >> ir_unop_bitcast_f2u, /**< Bit-identical float-to-uint "c

Re: [Mesa-dev] [PATCH v2] glsl: GLSL ES identifiers cannot exceed 1024 characters

Sorry for the delay... Reviewed-by: Ian Romanick On 01/20/2015 06:07 PM, Iago Toral Quiroga wrote: > v2 (Ian Romanick) > - Move the check to the lexer before rallocing a copy of the large string. > > Fixes the following 2 dEQP tests: > dEQP-GLES3.functional.shaders.keywords.invalid_identifiers.

Re: [Mesa-dev] [PATCH 02/11] glsl: Add link time checks for GLSL precision qualifiers

On 01/26/2015 10:09 AM, Iago Toral wrote: > On Tue, 2015-01-20 at 12:34 +0100, Iago Toral wrote: >> On Mon, 2015-01-19 at 19:39 -0800, Ian Romanick wrote: >>> On 01/19/2015 03:32 AM, Eduardo Lima Mitev wrote: From: Iago Toral Quiroga Currently, we only consider precision qualifiers

Re: [Mesa-dev] [PATCH v2 19/28] glsl: Support double inouts

On 02/06/2015 06:56 AM, Ilia Mirkin wrote: > From: Dave Airlie > > Signed-off-by: Dave Airlie > --- > src/glsl/ir_set_program_inouts.cpp | 28 +--- > 1 file changed, 25 insertions(+), 3 deletions(-) > > diff --git a/src/glsl/ir_set_program_inouts.cpp > b/src/glsl/ir_se

Re: [Mesa-dev] [PATCH v2 20/28] glsl: Support double loop control

On 02/06/2015 06:56 AM, Ilia Mirkin wrote: > From: Dave Airlie > > Signed-off-by: Dave Airlie > --- > src/glsl/loop_controls.cpp | 16 > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/src/glsl/loop_controls.cpp b/src/glsl/loop_controls.cpp > index 1c1d34f..4

Re: [Mesa-dev] [PATCH v2 21/28] glsl: Linking support for doubles

On 02/06/2015 06:56 AM, Ilia Mirkin wrote: > From: Dave Airlie > > Signed-off-by: Dave Airlie > --- > src/glsl/link_uniform_initializers.cpp | 8 +++- > src/glsl/link_varyings.cpp | 3 ++- > 2 files changed, 9 insertions(+), 2 deletions(-) > > diff --git a/src/glsl/link_uniform

Re: [Mesa-dev] [PATCH v2 22/28] glsl: add double support to lower_mat_op_to_vec

This patch is Reviewed-by: Ian Romanick On 02/06/2015 06:56 AM, Ilia Mirkin wrote: > From: Dave Airlie > > Signed-off-by: Dave Airlie > --- > src/glsl/lower_mat_op_to_vec.cpp | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/src/glsl/lower_mat_op_to_vec.cpp > b/src/glsl/lower_mat_

Re: [Mesa-dev] [PATCH v2 09/28] glsl/ir: Add builtin function support for doubles

On 02/06/2015 10:44 AM, Matt Turner wrote: > On Thu, Feb 5, 2015 at 11:47 PM, Ian Romanick wrote: >>> diff --git a/src/glsl/ir.h b/src/glsl/ir.h >>> index a0f48b2..6e7c654 100644 >>> --- a/src/glsl/ir.h >>> +++ b/src/glsl/ir.h >>> @@ -1275,6 +1275,13 @@ enum ir_expression_operation { >>> ir_un

Re: [Mesa-dev] [PATCH v2 23/28] glsl: validate output types for shader stages

On 02/06/2015 06:56 AM, Ilia Mirkin wrote: > From: Tapani Pälli > > Patch fixes Piglit test: >arb_gpu_shader_fp64/preprocessor/fs-output-double.frag > > and adds additional validation for shader outputs. > > Signed-off-by: Tapani Pälli > Signed-off-by: Dave Airlie > --- > src/glsl/ast_to

Re: [Mesa-dev] [PATCH v2 25/28] glsl/lower_instructions: add double lowering passes

On 02/06/2015 06:56 AM, Ilia Mirkin wrote: > From: Dave Airlie > > This lowers double dot product and lrp to fma. > > Signed-off-by: Dave Airlie > --- > src/glsl/lower_instructions.cpp | 83 > + > 1 file changed, 83 insertions(+) > > diff --git a/src/g

Re: [Mesa-dev] [PATCH v2 27/28] glsl: lower double optional passes (v2)

On 02/06/2015 06:56 AM, Ilia Mirkin wrote: > From: Dave Airlie > > These lowering passes are optional for the backend to request, currently > the TGSI softpipe backend most likely the r600g backend would want to use > these passes as is. They aim to hit the gallium opcodes from the standard > rou

Re: [Mesa-dev] [PATCH 2/4] mesa: introduce the equivalent of MESA_EXTENSION_OVERRIDE in drirc v2

On 03/02/15 18:27, Ilia Mirkin wrote: On Tue, Feb 3, 2015 at 10:41 AM, Martin Peres wrote: When both MESA_EXTENSION_OVERRIDE and drirc's mesa_extension_override are set, the environment variable takes precedence. Just a thought -- combine them instead of having one override the other? (With th

Re: [Mesa-dev] [PATCH 1/4] main: make the intel driver obey drirc's force_glsl_version

On 03/02/15 22:01, Kenneth Graunke wrote: It technically does support GLSL 1.10 and 1.20. Will the compiler backend complain about unknown instructions? I believe it supports everything needed for GLSL 1.20. It often falls back to swrast when exceeding limits. ack. Thanks! I'm more than O

Re: [Mesa-dev] [PATCH 02/11] glsl: Add link time checks for GLSL precision qualifiers

On Fri, 2015-02-06 at 10:47 +0200, Ian Romanick wrote: > On 01/26/2015 10:09 AM, Iago Toral wrote: > > On Tue, 2015-01-20 at 12:34 +0100, Iago Toral wrote: > >> On Mon, 2015-01-19 at 19:39 -0800, Ian Romanick wrote: > >>> On 01/19/2015 03:32 AM, Eduardo Lima Mitev wrote: > From: Iago Toral Qui

[Mesa-dev] [PATCH] gallium/util: Define ffsll on OpenBSD.

OpenBSD has ffs in libc but does not have ffsll so use the compiler builtin. PIPE_OS_BSD isn't suitable here as FreeBSD has ffsll in libc. Signed-off-by: Jonathan Gray --- src/gallium/auxiliary/util/u_math.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/auxiliary/util/u_math

[Mesa-dev] Expected wide line rendering with clipping

Hi, Eduardo and I have been looking into a few dEQP test failures that deal with wide line rendering. There are a few of them that fail because of how clipping is implemented for this case. The problem in these cases seems to be that the hw renders the wide line as a parallelogram so that if an e

Re: [Mesa-dev] [PATCH 01/11 v2] mesa: Returns a GL_INVALID_VALUE error on several APIs when buffer size is negative

Sorry for the delay... Reviewed-by: Ian Romanick On 01/21/2015 04:32 PM, Eduardo Lima Mitev wrote: > Section 2.3.1 (Errors) of the OpenGL 4.5 spec says: > > "If a negative number is provided where an argument of type sizei or > sizeiptr is specified, an INVALID_VALUE error is generated.

Re: [Mesa-dev] [PATCH 1/4] intel: make the i830/i915/i965 drivers obey drirc's force_glsl_version v2

This patch is Reviewed-by: Ian Romanick On 02/03/2015 05:41 PM, Martin Peres wrote: > v2: > - change the commit name as per Marek's comment > - make the i830/i915 drivers actually use the force_glsl_version > > Reviewed-by: Kenneth Graunke v1 > Signed-off-by: Martin Peres > --- > src/mesa/dr

Re: [Mesa-dev] [PATCH 3/4] drirc: add workarounds for Unigine Tropics v2

This patch is Reviewed-by: Ian Romanick On 02/03/2015 05:41 PM, Martin Peres wrote: > v2: > - rename mesa_extension-override to extension_override > - improve the comment by telling we disable GL_ARB_gpu_shader5 > - fix the name ARB_GL_gpu_shader5 to GL_ARB_gpu_shader5 (Ilia) > > Bugzilla: http

Re: [Mesa-dev] [PATCH 4/4] drirc: add workarounds for Unigine Sanctuary v2

On 02/04/2015 02:18 AM, Matt Turner wrote: > On Tue, Feb 3, 2015 at 7:41 AM, Martin Peres > wrote: >> v2: >> - rename mesa_extension-override to extension_override >> - improve the comment by telling we disable GL_ARB_gpu_shader5 (Ilia) >> - fix the name ARB_GL_gpu_shader5 to GL_ARB_gpu_shader5 (I

[Mesa-dev] [PATCH 3/3] i965: Fix integer border color on Haswell.

+82 Piglits - 100% of border color tests now pass on Haswell. Signed-off-by: Kenneth Graunke Cc: Chris Forbes Cc: mesa-sta...@lists.freedesktop.org --- src/mesa/drivers/dri/i965/brw_defines.h | 1 + src/mesa/drivers/dri/i965/brw_sampler_state.c | 62 +++ src/m

[Mesa-dev] [PATCH 1/3] i965: Override swizzles for integer luminance formats.

The hardware's integer luminance formats are completely unusable; currently we fall back to RGBA. This means we need to override the texture swizzle to obtain the XXX1 values expected for luminance formats. Fixes spec/EXT_texture_integer/texwrap formats bordercolor [swizzled] on Broadwell - 100%

[Mesa-dev] [PATCH 2/3] i965: Use a gl_color_union for sampler border color.

This should have no effect, but will make it easier to implement other bug fixes. Signed-off-by: Kenneth Graunke Cc: Chris Forbes Cc: mesa-sta...@lists.freedesktop.org --- src/mesa/drivers/dri/i965/brw_sampler_state.c | 107 +- 1 file changed, 54 insertions(+), 53 deleti

Re: [Mesa-dev] [PATCH 2/4] mesa: introduce the equivalent of MESA_EXTENSION_OVERRIDE in drirc v2

On 02/06/2015 12:20 PM, Martin Peres wrote: > On 03/02/15 18:27, Ilia Mirkin wrote: >> On Tue, Feb 3, 2015 at 10:41 AM, Martin Peres >> wrote: >>> When both MESA_EXTENSION_OVERRIDE and drirc's mesa_extension_override >>> are >>> set, the environment variable takes precedence. >> Just a thought --

Re: [Mesa-dev] [PATCH 1/3] i965: Override swizzles for integer luminance formats.

FWIW, this patch is Reviewed-by: Ian Romanick On 02/06/2015 02:32 PM, Kenneth Graunke wrote: > The hardware's integer luminance formats are completely unusable; > currently we fall back to RGBA. This means we need to override > the texture swizzle to obtain the XXX1 values expected for luminanc

Re: [Mesa-dev] [PATCH 2/3] i965: Use a gl_color_union for sampler border color.

On 02/06/2015 02:32 PM, Kenneth Graunke wrote: > This should have no effect, but will make it easier to implement other > bug fixes. > > Signed-off-by: Kenneth Graunke > Cc: Chris Forbes > Cc: mesa-sta...@lists.freedesktop.org > --- > src/mesa/drivers/dri/i965/brw_sampler_state.c | 107 > +

[Mesa-dev] [PATCH v2] glsl: Add link time checks for GLSL precision qualifiers

Currently, we only consider precision qualifiers at compile-time. This patch adds precision information to ir_variable so we can also do link time checks. Specifically, from the GLSL ES3 spec, 4.5.3 Precision Qualifiers: "The same uniform declared in different shaders that are linked together mus

[Mesa-dev] [PATCH 02/32] i965: Move IR object definitions to separate header files.

One should be able to manipulate i965 IR without pulling the whole FS/VEC4 visitor classes -- Optimization passes and other transformations would ideally be visitor-agnostic. Among other issues this avoids a circular dependency between the header file where such visitor-agnostic code will be defin

[Mesa-dev] [PATCH 05/32] i965: Move up fs_inst::regs_written to backend_instruction.

It will also be useful in the VEC4 back-end. --- src/mesa/drivers/dri/i965/brw_ir_fs.h | 1 - src/mesa/drivers/dri/i965/brw_shader.h | 1 + src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 1 + 3 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 19/32] i965/vec4: Pass dst register to the vec4_instruction constructor.

So regs_written gets initialized with a sensible value. --- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index babddee.

[Mesa-dev] [PATCH 23/32] i965/vec4: Init mlen for several send from GRF instructions.

--- src/mesa/drivers/dri/i965/brw_vec4.cpp | 4 +++- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 11 +++ src/mesa/drivers/dri/i965/brw_vec4_vp.cpp | 1 + 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/d

[Mesa-dev] [PATCH 15/32] i965/vec4: Implement equals() method for dst_reg too.

--- src/mesa/drivers/dri/i965/brw_ir_vec4.h | 2 ++ src/mesa/drivers/dri/i965/brw_vec4.cpp | 16 2 files changed, 18 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h index ae024b3..f11a2d2 100644 --- a/src/mesa/driver

[Mesa-dev] [PATCH 04/32] i965/vec4: Remove dependency of vec4_instruction on the visitor class.

The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. --- src/mesa/drivers/dri/i965/brw_ir_vec4.h| 3 +- src/mesa/drivers/dri/i965/brw_vec4_

[Mesa-dev] [PATCH 13/32] i965/fs: Fix lower_load_payload() not to use an incorrect half for immediates and uniforms.

--- src/mesa/drivers/dri/i965/brw_fs.cpp | 8 1 file changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 8da1f47..e2ebf7e 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -

[Mesa-dev] [PATCH 30/32] i965: Handle F16TO32/F32TO16 with dword src/dst consistently on both back-ends.

Due to the way it's implemented in hardware, the F16TO32/F32TO16 instructions require the source/destination register to be of some 16-bit type in Align1 mode, while they require it to be some 32-bit type in Align16 mode (and as an undocumented feature the high 16 bits of the destination register a

[Mesa-dev] [PATCH 24/32] i965/vec4: Add register classes up to MAX_VGRF_SIZE.

In preparation for some send from GRF instructions that will require larger payloads. --- src/mesa/drivers/dri/i965/brw_fs.h | 3 --- src/mesa/drivers/dri/i965/brw_shader.h | 3 +++ src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 10 ++ 3 files changed

[Mesa-dev] [PATCH 03/32] i965/fs: Remove dependency of fs_inst on the visitor class.

The fs_visitor argument of fs_inst::regs_read() wasn't used at all. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++-- src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp| 4 ++-- src/mesa/drivers/dri/i965/brw_fs_dead_code_eliminate.cpp | 2 +- src/mesa/drivers/dri/i965/b

[Mesa-dev] [PATCH 01/32] i965: Factor out virtual GRF allocation to a separate object.

Right now virtual GRF book-keeping and allocation is performed in each visitor class separately (among other hundred different things), leading to duplicated logic in each visitor and preventing layering as it forces any code that manipulates i965 IR and needs to allocate virtual registers to depen

[Mesa-dev] [PATCH 16/32] i965/vec4: Initialize vec4_instruction::predicate and ::predicate_inverse.

--- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 2cd185b..babddee 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mes

[Mesa-dev] [PATCH 21/32] i965/vec4: Fix the scheduler to take into account reads and writes of multiple registers.

--- src/mesa/drivers/dri/i965/brw_ir_vec4.h | 1 + src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 15 ++- src/mesa/drivers/dri/i965/brw_vec4.cpp | 17 + 3 files changed, 28 insertions(+), 5 deletions(-) diff --git a/src/mesa

[Mesa-dev] [PATCH 18/32] i965/vec4: Don't attempt to reduce swizzles of send from GRF instructions.

--- src/mesa/drivers/dri/i965/brw_vec4.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index c3f68e6..aaa4873 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i9

[Mesa-dev] [PATCH 25/32] i965/vec4: Take into account non-zero reg_offset during register allocation.

--- src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp index 80735c3..46f0bfd 100644 --- a/src/mesa/drivers/dri/i965/br

[Mesa-dev] [PATCH 22/32] i965/vec4: Don't infer MRF dependencies for send from GRF instructions.

--- .../drivers/dri/i965/brw_schedule_instructions.cpp | 32 -- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp index 2b22b2c..24075bd 100644 --- a

[Mesa-dev] [PATCH 31/32] i965/vec4: Don't set any dependency control bits for F32TO16 on Gen8.

It's expanded to several instructions. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index ed35c4b..85b9162f 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++

[Mesa-dev] [PATCH 27/32] i965: Handle negated unsigned immediate values in constant propagation.

Negation of UD/UW sources behaves the same as for D/W sources, taking the two's complement of the source, except for bitwise logical operations on Gen8 and up which take the one's complement. Fixes crash in a GLSL shader with subtraction of two unsigned values. --- .../drivers/dri/i965/brw_fs_cop

[Mesa-dev] [PATCH 17/32] i965/vec4: Fix constant propagation across different types.

If the source type differs from the original type of the constant we need to bit-cast it before propagating, otherwise the original type information will be lost. If the constant was a vector float there isn't much we can do, because the result of bit-casting the component values of a vector float

[Mesa-dev] [PATCH 32/32] i965: Don't compact instructions with unmapped bits.

Some instruction bits don't have a mapping defined to any compacted instruction field. If they're ever set and we end up compacting the instruction they will be forced to zero. Avoid using compaction in such cases. --- src/mesa/drivers/dri/i965/brw_eu_compact.c | 48 +

[Mesa-dev] [PATCH 09/32] i965/fs: Fix fs_inst::regs_written calculation for instructions with scalar dst.

Scalar registers are required to have zero stride, fix the regs_written calculation not to assume that the instruction writes zero registers in that case. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs

[Mesa-dev] [PATCH 08/32] i965/fs: Fix stack allocation of fs_inst and stop stealing src array provided on construction.

Using 'ralloc*(this, ...)' is wrong if the object has automatic storage or was allocated through any other means. Use normal dynamic memory instead. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 68 +-- src/mesa/drivers/dri/i965/brw_ir_fs.h | 8 +++-- 2 files change

[Mesa-dev] [PATCH 07/32] i965/fs: Remove duplicate include of brw_shader.h

The second one was inside an extern "C" block, luckily it was being discarded by the preprocessor. --- src/mesa/drivers/dri/i965/brw_fs.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index e789d25..ccd3da7 100644 --- a/

[Mesa-dev] [PATCH 12/32] i965/fs: Fix lower_load_payload() to take into account stride in the metadata guess.

--- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 163aa41..8da1f47 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.

[Mesa-dev] [PATCH 11/32] i965/fs: Fix lower_load_payload() to take into account non-zero reg_offset.

Fixes metadata guess when instructions in the program specify a destination register with non-zero reg_offset and when the payload of a LOAD_PAYLOAD spans several registers. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/dr

[Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().

MRFs cannot be read from anyway so they cannot possibly be a valid source of LOAD_PAYLOAD. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 39 1 file changed, 13 insertions(+), 26 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dr

[Mesa-dev] [PATCH 29/32] i965/gen8: Fix F32TO16 in vec4 mode if the source and destination registers alias.

We cannot zero out the destination register if it overlaps with the source. Use an Align1 instruction instead to zero out the high 16 bits after the conversion to half float. --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 36 - 1 file changed, 27 insertions(+), 9 de

[Mesa-dev] [PATCH 26/32] i965/vec4: Don't assume a value is dead when its VGRF is only partially overwritten.

--- src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp index 9604e60..5df0d31 100644 --- a/src/mesa

[Mesa-dev] [PATCH 28/32] i965/fs: Replace ud_reg_to_w() with a more general helper function.

--- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 27 +++--- src/mesa/drivers/dri/i965/brw_reg.h| 22 + 2 files changed, 25 insertions(+), 24 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i96

[Mesa-dev] [PATCH 14/32] i965/fs: Fix register coalesce not to lose track of the second half of 16-wide moves.

Fixes rewrite by the register coalesce pass of references to individual halves of 16-wide coalesced registers. --- src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.c

[Mesa-dev] [PATCH 20/32] i965/vec4: Make vec4_visitor::implied_mrf_writes() return zero for sends from GRF.

--- src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index aaa4873..a4fd136 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 06/32] i965: Move up fs_inst::flag_subreg to backend_instruction.

--- src/mesa/drivers/dri/i965/brw_ir_fs.h| 5 - src/mesa/drivers/dri/i965/brw_shader.h | 5 + src/mesa/drivers/dri/i965/brw_vec4.cpp | 11 +-- src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 1 + src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp

Re: [Mesa-dev] [PATCH 2/2] gallium/hud: also try R8_UNORM format for font texture

For the series: Reviewed-by: Marek Olšák Marek On Wed, Feb 4, 2015 at 9:46 PM, Brian Paul wrote: > Convert the code to try formats from an array rather than a bunch > of if/else cases. > --- > src/gallium/auxiliary/hud/font.c | 24 +++- > 1 file changed, 15 insertions(+),

[Mesa-dev] [Bug 88536] AMD graphics hardware hangs with an homogeneous coloured screen or blank screen, and with chirp coming from the graphics card

https://bugs.freedesktop.org/show_bug.cgi?id=88536 --- Comment #21 from Alberto Salvia Novella --- Other symptom is sound hangs too. And sometimes, when graphics hang, what appear in screen is a pattern of stripes of near the same colour. -- You are receiving this mail because: You are the QA

[Mesa-dev] [Bug 88536] AMD graphics hardware hangs with an homogeneous coloured screen or blank screen, and with chirp coming from the graphics card

https://bugs.freedesktop.org/show_bug.cgi?id=88536 --- Comment #22 from Alberto Salvia Novella --- Looks like -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. _

Re: [Mesa-dev] [PATCH] gallium/util: Define ffsll on OpenBSD.

On 02/06/2015 04:38 AM, Jonathan Gray wrote: OpenBSD has ffs in libc but does not have ffsll so use the compiler builtin. PIPE_OS_BSD isn't suitable here as FreeBSD has ffsll in libc. Signed-off-by: Jonathan Gray --- src/gallium/auxiliary/util/u_math.h | 2 ++ 1 file changed, 2 insertions(+

Re: [Mesa-dev] [PATCH 05/13] mesa: add double uniform support. (v4)

On 02/05/2015 08:38 PM, Ilia Mirkin wrote: On Thu, Feb 5, 2015 at 11:17 AM, Brian Paul wrote: On 02/05/2015 12:27 AM, Ilia Mirkin wrote: From: Dave Airlie This adds support for the new uniform interfaces from ARB_gpu_shader_fp64. v2: support ARB_separate_shader_objects ProgramUniform*d* (I

Re: [Mesa-dev] [PATCH 2/2] r300g: small code cleanup

This looks good with one exception: MAX_PREDS should be 0 for all shader stages. It has never been supported and never will be. With that done, this patch is: Reviewed-by: Marek Olšák Marek On Thu, Feb 5, 2015 at 11:56 PM, David Heidelberg wrote: > Signed-off-by: David Heidelberg > --- > src

[Mesa-dev] [Bug 88962] [osmesa] Crash on postprocessing if z buffer is NULL

https://bugs.freedesktop.org/show_bug.cgi?id=88962 --- Comment #6 from Brian Paul --- (In reply to Park, Jeongmin from comment #5) > Sorry about the first patch. I didn't see that. > > In dri_sw.c, it checks for z/s buffer: > > if (ctx->pp && drawable->textures[ST_ATTACHMENT_DEPTH_STENCIL])

[Mesa-dev] [PATCH] nv50, nvc0: Mark PIPE_QUERY_TIMESTAMP_DISJOINT as ready immediately on end because it is not issued on the gpu

Signed-off-by: Tiziano Bacocco --- src/gallium/drivers/nouveau/nv50/nv50_query.c | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_query.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/gallium/drivers/nouveau/nv50/nv50_query.c b/src/gallium/drivers/nouveau/nv50/nv50_query.c index e0671c

Re: [Mesa-dev] [PATCH 1/2] r300g: handle unsupported blend factor gracefully

Michel is right. Nine shouldn't use the blend factors if the driver doesn't support them. The removal of the "XXX" comment is okay and can be moved to patch 2. Marek On Fri, Feb 6, 2015 at 3:46 AM, Michel Dänzer wrote: > On 06.02.2015 09:14, David Heidelberg wrote: >> these days all (r600+,nv50

Re: [Mesa-dev] [PATCH v3] r600g: Implement GL_ARB_draw_indirect for EG/CM

Please bump the size of vgt_state for the SQ_VTX_BASE_VTX_LOC register. It's set by r600_init_atom in r600_state.c and evergreen_state.c Please bump R600_MAX_DRAW_CS_DWORDS. It's an upper bound of how many dwords draw_vbo can emit. I don't understand what get_vfetch_type is good for. Could you pl

Re: [Mesa-dev] [PATCH 2/2] r300g: small code cleanup

Should I incorporate PIPE_SHADER_CAP_MAX_PREDS change in this patch or send another with idea of dropping PIPE_SHADER_CAP_MAX_PREDS completly from gallium, if there is no use? David On 02/06/2015 04:41 PM, Marek Olšák wrote: This looks good with one exception: MAX_PREDS should be 0 for all sh

Re: [Mesa-dev] [PATCH] nv50, nvc0: Mark PIPE_QUERY_TIMESTAMP_DISJOINT as ready immediately on end because it is not issued on the gpu

On Fri, Feb 6, 2015 at 10:46 AM, Tiziano Bacocco wrote: > Please provide a commit log. Subject lines should be limited to 72 chars (as should commit log bodies). > Signed-off-by: Tiziano Bacocco > --- > src/gallium/drivers/nouveau/nv50/nv50_query.c | 1 + > src/gallium/drivers/nouveau/nvc0/nvc

[Mesa-dev] [Bug 88967] Black textures Radeon m HD 5650

https://bugs.freedesktop.org/show_bug.cgi?id=88967 --- Comment #23 from Sven Arvidsson --- So, a few things you could try: The bug could be in Wine (different drivers can lead to different behaviour), the game (Mesa sometimes follows the OpenGL spec better than other drivers and exposes bugs in

Re: [Mesa-dev] [PATCH 2/2] r300g: small code cleanup

You can update MAX_PREDS in this patch. I proposed removing predicates a long time ago, but some people disagreed. Marek On Fri, Feb 6, 2015 at 5:19 PM, David Heidelberg wrote: > Should I incorporate PIPE_SHADER_CAP_MAX_PREDS change in this patch or send > another with idea of dropping PIPE_SHA

[Mesa-dev] [PATCH 01/14] i965: Don't tile 1D miptrees.

It doesn't really improve locality of texture fetches, quite the opposite it's a waste of memory bandwidth and space due to tile alignment. --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src

[Mesa-dev] [PATCH 11/14] i965/gen7: Enable fragment shader dispatch if the program has image uniforms.

Shaders with image uniforms may have side effects. Make sure that fragment shader threads are dispatched if the shader has any image uniforms. --- src/mesa/drivers/dri/i965/gen7_wm_state.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/gen7_wm_s

Re: [Mesa-dev] [PATCH 2/2] r300g: small code cleanup

Ok, I'll do. About MAX_PREDS, maybe it's time to bring it out again :) On 02/06/2015 06:16 PM, Marek Olšák wrote: You can update MAX_PREDS in this patch. I proposed removing predicates a long time ago, but some people disagreed. Marek On Fri, Feb 6, 2015 at 5:19 PM, David Heidelberg wrote:

[Mesa-dev] [Bug 88967] Black textures Radeon m HD 5650

https://bugs.freedesktop.org/show_bug.cgi?id=88967 --- Comment #24 from Grimdoll --- 1) This game works with option d3dx9 libs setted as native, with builtin it would not work at all; 2) I don't know how to use stable mesa, I tried to revert to standard Ubuntu drivers by: $ sudo apt-get install p

[Mesa-dev] [PATCH 14/14] i965/gen7-8: Implement glMemoryBarrier().

--- src/mesa/drivers/dri/i965/brw_program.c | 40 + src/mesa/drivers/dri/i965/intel_reg.h | 1 + 2 files changed, 41 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index d9a3f05..793d963 100644 --- a

[Mesa-dev] [PATCH 02/14] i965: Allocate binding table space for shader images.

Reviewed-by: Paul Berry --- src/mesa/drivers/dri/i965/brw_context.h | 5 + src/mesa/drivers/dri/i965/brw_shader.cpp | 7 +++ 2 files changed, 12 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index bebb0be..e28c65d 100644 --

[Mesa-dev] [PATCH 08/14] i965: Define and initialize image parameter structure.

This will be used to pass image meta-data to the shader when we cannot use typed surface reads and writes. All entries except surface_idx and size are otherwise unused and will get eliminated by the uniform packing pass. size will be used for bounds checking with some image formats and will be us

[Mesa-dev] [PATCH 10/14] i965: Hook up image state upload.

--- src/mesa/drivers/dri/i965/brw_context.h | 8 +++- src/mesa/drivers/dri/i965/brw_gs_surface_state.c | 25 src/mesa/drivers/dri/i965/brw_state.h| 3 ++ src/mesa/drivers/dri/i965/brw_state_upload.c | 10 + src/mesa/drivers/dri/i965/brw_vs_surface_state.

[Mesa-dev] [PATCH 09/14] i965: Reserve enough parameter entries for all image uniforms used in the program.

--- src/mesa/drivers/dri/i965/brw_gs.c | 1 + src/mesa/drivers/dri/i965/brw_vs.c | 4 ++-- src/mesa/drivers/dri/i965/brw_wm.c | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c index ce3cba4..bfb64f3 1006

[Mesa-dev] [PATCH 04/14] i965/gen7: Factor out texture surface state set-up from gen7_update_texture_surface().

This moves most of the surface state set-up logic that can be shared between textures and shader images to a separate function. --- src/mesa/drivers/dri/i965/brw_context.h | 11 ++ src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 124 +- 2 files changed, 83 insert

[Mesa-dev] [PATCH 03/14] i965: Add helper functions to calculate the slice pitch of an array or 3D miptree.

--- src/mesa/drivers/dri/i965/brw_tex_layout.c| 45 +-- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 18 +++ 2 files changed, 53 insertions(+), 10 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layou

[Mesa-dev] [PATCH 06/14] i965: Generalize the update_null_renderbuffer_surface vtbl hook to non-renderbuffers.

Null surfaces are going to be useful to have something to point unbound image units to, as the ARB_shader_image_load_store extension requires us to behave deterministically in cases where some shader tries to access an unbound image unit: Invalid stores and atomics are supposed to be discarded and

[Mesa-dev] [PATCH 07/14] i965: Implement surface state set-up for shader images.

--- src/mesa/drivers/dri/i965/brw_context.h | 2 + src/mesa/drivers/dri/i965/brw_surface_formats.c | 111 +++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 77 3 files changed, 190 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_cont

[Mesa-dev] [PATCH 13/14] i965/gen7-8: Set up early depth/stencil control appropriately for image load/store.

--- src/mesa/drivers/dri/i965/brw_defines.h | 3 +++ src/mesa/drivers/dri/i965/gen7_wm_state.c| 7 +++ src/mesa/drivers/dri/i965/gen8_depth_state.c | 12 src/mesa/drivers/dri/i965/gen8_ps_state.c| 13 + 4 files changed, 31 insertions(+), 4 deletions(-)

[Mesa-dev] [PATCH 05/14] i965/gen8: Factor out texture surface state set-up from gen8_update_texture_surface().

This moves most of the surface state set-up logic that can be shared between textures and shader images to a separate function. --- src/mesa/drivers/dri/i965/gen8_surface_state.c | 136 ++--- 1 file changed, 77 insertions(+), 59 deletions(-) diff --git a/src/mesa/drivers/dri/i

[Mesa-dev] [PATCH 12/14] i965/gen7-8: Poke the 3DSTATE UAV access enable bits.

--- src/mesa/drivers/dri/i965/brw_defines.h | 3 +++ src/mesa/drivers/dri/i965/gen7_gs_state.c | 4 +++- src/mesa/drivers/dri/i965/gen7_vs_state.c | 13 - src/mesa/drivers/dri/i965/gen7_wm_state.c | 3 +++ src/mesa/drivers/dri/i965/gen8_gs_state.c | 4 +++- src/mesa/drivers/dri/i

[Mesa-dev] [PATCH v2] nv50, nvc0: Mark PIPE_QUERY_TIMESTAMP_DISJOINT as ready immediately

Without this when an application issues that query, it would try to wait the result from the gpu, and since no query has been actually issued, it will wait for ever Signed-off-by: Tiziano Bacocco --- src/gallium/drivers/nouveau/nv50/nv50_query.c | 2 ++ src/gallium/drivers/nouveau/nvc0/nvc0_quer

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