Re: [Mesa-dev] Submitting more shaders to shader-db?

On Sunday 04 January 2015 09:36:40 Aras Pranckevicius wrote: > Hi, > > I noticed some GLSL related discussions talk "My shader-db is dominated by > TF2, DOTA2, Portal, Brutal Legend and Dungeon Defenders. Maybe > non-Source-engine > games show some benefit from this series?" > > Now, shader-db th

Re: [Mesa-dev] [PATCH 11/22] glsl: Add ir_binop_mul to get_range

On Sat, 2015-01-03 at 20:18 +0100, Thomas Helland wrote: > V2: Add some air for readability > Use the new IS_CONSTANT macro > Combine if-blocks for reduced code-duplication > Split out into separate function for reuse later > --- > src/glsl/opt_minmax.cpp | 33 +

[Mesa-dev] [PATCH] glsl: Add ir_binop_mul to get_range

V2: Add some air for readability Use the new IS_CONSTANT macro Combine if-blocks for reduced code-duplication Split out into separate function for reuse later V3: Fix flawed logic (Spotted by Bruno) --- src/glsl/opt_minmax.cpp | 45 + 1 file

[Mesa-dev] [PATCH] tgsi: keep track of read vs written indirects

From: Rob Clark At least temporarily, I need to fallback to old compiler still for relative dest (for freedreno), but I can do relative src temp. Only a temporary situation, but seems easy/reasonable for tgsi-scan to track this. Signed-off-by: Rob Clark --- I could always keep temp indirect su

[Mesa-dev] [RFC PATCH 09/40] i965/gen7.5: Upload binding tables as hw-generated binding table format.

When hardware-generated binding tables are enabled, use the hw-generated binding table format when uploading binding table state. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_binding_tables.c | 18 +- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git

[Mesa-dev] [RFC PATCH 08/40] i965/gen7.5: Implement opcodes for the hw-generated binding table EDIT commands

Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_binding_tables.c | 40 ++ src/mesa/drivers/dri/i965/brw_defines.h| 5 src/mesa/drivers/dri/i965/brw_state.h | 9 ++ 3 files changed, 54 insertions(+) diff --git a/src/mesa/drivers

[Mesa-dev] [RFC PATCH 06/40] i965/gen7.5: Enable hardware-generated binding tables in blorp path

Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 206a6ff..3d5c7df 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b

[Mesa-dev] [RFC PATCH 10/40] i965/blorp: Update hw-binding table entries for blorp.

Update the hw-generated binding table for blorp SURFACE_STATE entries. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 35 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src

[Mesa-dev] [RFC PATCH 13/40] i965: Enable gather push constants

The 3DSTATE_GATHER_POOL_ALLOC is used to enable or disable the gather push constants feature within a context. This patch provides the toggle functionality of using gather push constants to program constant data within a batch. In addition, using gather push constants require that a gather pool be

[Mesa-dev] [RFC PATCH 07/40] i965/gen7.5: Reset resource streamer pool offsets on batch flush

Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 1150e3d..df4a0f2 100644 --- a/src/mesa/drivers/dri/i965/int

[Mesa-dev] [RFC PATCH 12/40] i965: Add gather push constants opcodes

Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_defines.h | 8 1 file changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 3f31a6f..d0b1eab 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++

[Mesa-dev] [RFC PATCH 02/40] i965/gen7.5: Introduce INTEL_RESOURCE_STREAMER to toggle resource streamer

export INTEL_RESOURCE_STREAMER={0,1} To switch on/off resource streamer. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_context.c | 6 ++ src/mesa/drivers/dri/i965/brw_context.h | 1 + 2 files changed, 7 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b

[Mesa-dev] [RFC PATCH 15/40] i965: Upload uniforms to the constant buffer

When uploading uniform constants to the uniform constant buffer, this patch aligns each entry to a 4k-sized boundary so that the gather table is able to refer to the individual bank using the hw-binding table index and the constant buffer offset to fetch to the constant entry. Signed-off-by: Abdie

[Mesa-dev] [RFC PATCH 19/40] mesa: Change internal state flag to a 64-bits

Existing state flag cannot publish additional values. Signed-off-by: Abdiel Janulgue --- src/mesa/main/dd.h | 2 +- src/mesa/main/mtypes.h | 3 ++- src/mesa/main/state.c | 6 +++--- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h index

[Mesa-dev] [RFC PATCH 05/40] i965/gen7.5: Enable hardware-generated binding tables on render path.

This patch implements the binding table enable command which is also used to allocate a binding table pool where where hardware-generated binding table entries are flushed into. Each binding table offset in the binding table pool is unique per each shader stage that are enabled within a batch. In

[Mesa-dev] [RFC PATCH 21/40] i965: Make sure that we receive 64-bit state flags

Match core Mesa state flags to receive correct notifications. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_context.c | 2 +- src/mesa/drivers/dri/i965/brw_context.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.

[Mesa-dev] [RFC PATCH 01/40] i965/gen7.5: Implement resource streamer control opcodes

Used to toggle the resource streamer within a batchbuffer Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/intel_reg.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h index 5ac0180..d41adaa 100644 -

[Mesa-dev] [RFC PATCH 04/40] i965/gen7.5: Implement MI_RS_STORE_DATA_IMM workaround for 3DPRIMITIVE commands

Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_draw.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index c581cc0..d48128d 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/s

[Mesa-dev] [RFC PATCH 03/40] i965/gen7.5: Pass resource streamer enable flags on batchbuffer start

This is passed on the kernel to enable the resource streamer enable bit on MI_BATCHBUFFER_START v3: Use I915_EXEC_RESOURCE_STREAMER. Kernel folks want the batchbuffer flags to be more concise. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 7 ++- 1 fi

[Mesa-dev] [RFC PATCH 18/40] i965: Don't use gather push constants in BLORP

Switch off gather push constants in the blorp. Blorp requires only a a set of simple constants that there is no need for the extra complexity to program a gather table entry into the pipeline. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 1 + 1 file changed, 1 in

[Mesa-dev] [RFC PATCH 20/40] mesa: Publish uniform update state flags

Trigger it when uniforms are updated Signed-off-by: Abdiel Janulgue --- src/mesa/main/dd.h | 2 ++ src/mesa/main/mtypes.h | 3 +++ src/mesa/main/state.c | 10 +- src/mesa/main/uniform_query.cpp | 6 ++ 4 files changed, 16 insertions(+), 5 deletions(

[Mesa-dev] [RFC PATCH 17/40] i965: Program the push constants state using the gather table

Use the gather table generated from the uniform uploads to gather and pack the constants to the gather pool. This changes the 3DSTATE_CONSTANT_* bits to refer to the gather pool instead of the constant buffer pointed to by an offset of the dynamic state base address. Signed-off-by: Abdiel Janulgue

[Mesa-dev] [RFC PATCH 26/40] i965: Allocate space on the gather pool for UBO entries

In addition, append the UBO entries to stage_state->push_const_size Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/gen6_vs_state.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965

[Mesa-dev] [RFC PATCH 16/40] i965: Allocate space on the gather pool for every push constant state

Reserve space in the gather pool where the resource streamer will flush its gather constant data. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/gen6_vs_state.c | 8 1 file changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers

[Mesa-dev] [RFC PATCH 11/40] i965/gen7.5: Flush on-chip binding table to pool

Normally, the CS will will just consume the binding table pointer commands as pipelined state. When the RS is enabled however, the RS flushes whatever edited surface state entries of our on-chip binding table to the binding table pool before passing the command on to the CS. Note that the the bind

[Mesa-dev] [RFC PATCH 14/40] i965: Initialize and partition a 32k constant buffer for uniforms.

Uniforms are uploaded to this buffer instead of the space allocated from the dynamic state base address. This buffer is sliced into eight 4k-sized banks; each accessible by SURFACE_STATE entries. These banks are layouted in such a way that all shader stages can upload to whatever next free bank is

[Mesa-dev] [RFC PATCH 25/40] i965: Disable gather push constants for null constants

Programming null constants with gather constant tables seems to be unsupported and results in a GPU lockup even with the prescribed GPU workarounds in the bspec. I found out by trial and error that disabling the gather constant feature for null constants is the only way to go around the issue. Thi

[Mesa-dev] [RFC PATCH 23/40] i965/fs: Associate the uniform location for the fragment shader

Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_fs.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 3639ed2..0f2c2c4 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/

[Mesa-dev] Resource streamer redux: Enable gather push constants

I sent previous patches enabling hardware-generated binding tables. By itself, hw-binding tables gave no performance improvements, it is just a means to an end. However, the real meat of the RS hardware is the optimized ability to map constants to the GRF. Gather push constants is basically an op

[Mesa-dev] [RFC PATCH 30/40] i965/fs: Append ir_binop_ubo_load entries to the gather table

At the moment, this is only possible if the const block and offset are immediate values (constants). Otherwise just fall-back to the previous method of uploading the UBO constant data to GRF using pull constants. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_context.h |

[Mesa-dev] [RFC PATCH 22/40] i965: Implement fine-grained uniform uploads

Determine which shader stage changed their uniforms and only upload uniforms which belong to it. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_context.h | 2 ++ src/mesa/drivers/dri/i965/brw_program.c | 9 + src/mesa/drivers/dri/i965/gen7_vs_state.c | 4 3 fil

[Mesa-dev] [RFC PATCH 27/40] i965: Build a dynamic gather table for UBO push constant entries

The resource streamer is able to gather and pack sparsely-located constant data from any buffer object representing a UBO block. This patch adds support for keeping track of these constant data fetches into a gather table. We only allocate a maximum of 128 entries. This limitation is taken from a

[Mesa-dev] [RFC PATCH 40/40] i965: Enable push constants for UBOs

Switches on push constants whenever we have UBO entries. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index 9

[Mesa-dev] [RFC PATCH 24/40] i965/vec4: Associate the uniform location with either geometry or vertex stage

Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 09d79c8..0f22829 100644 --- a/src/mesa/drivers/dri/i965/br

[Mesa-dev] [RFC PATCH 37/40] i965: Assign hw-binding table entries for each ubo block.

Blanket the ubo blocks with a binding table. Note that the resource streamer is able to fetch the constant buffers referred to by the gather table only if it is referenced by the hw-binding table generator. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_context.h | 3 +

[Mesa-dev] [RFC PATCH 36/40] i965/fs: Make SIMD16 work for UBO gather push constants

Gather table entries were generated previously in the SIMD8 pass. Just reuse those entries for SIMD16 so we don't generate a duplicate set of registers. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 13 + 1 file changed, 13 insertions(+) diff --gi

[Mesa-dev] [RFC PATCH 39/40] i965: Generate separate gather entries for UBOs

Now that we are able to use a gather table for fetching UBOs, make a gather entry based on the table generated by the ir_binop_ubo_load and uniform loads combined. At the moment, we separate this entry from the previous uniform-only gather table because the current approach to pack the uniform and

[Mesa-dev] [RFC PATCH 28/40] i965/fs: Append uniform variables to the gather table

Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index bd9345e..2f592c9 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_vis

[Mesa-dev] [RFC PATCH 38/40] i965/fs: Update curb_read_length to include ubo uniforms

Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_fs.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 8a03581..904c51b 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b

[Mesa-dev] [RFC PATCH 33/40] i965/fs: Include ubo registers when assigning push_constant locations

When assigning a block of register to normal uniforms, pack the ubo uniform registers next to it. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_fs.cpp | 22 +- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.c

[Mesa-dev] [RFC PATCH 32/40] i965/fs: Pack a uniform register next to UBO uniforms

And vice versa. This allows us to combine UBOs and uniform registers as push constants. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_fs.cpp | 1 + src/mesa/drivers/dri/i965/brw_fs.h | 3 +++ src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 3 ++- 3 files chang

[Mesa-dev] [RFC PATCH 34/40] i965/fs: Specify which channels are enabled per gather constant entry

A gather push constant table entry is able to fetch in 128-bit increments from the constant buffer. A channel mask is provided to narrow down which channels are loaded in that entry. This patch generates the mask for enabled entries only. The ir_swizzle visitor which is run prior this function det

[Mesa-dev] [RFC PATCH 35/40] i965: Upload UBO surfaces before emitting constant state packet

Now that UBOs are uploaded as push constants. We need to obtain and append the amount of push constant entries generated by the UBO entry fetches to the 3DSTATE_CONSTANT_* packets. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_state_upload.c | 7 --- 1 file changed, 4 inse

[Mesa-dev] [RFC PATCH 29/40] i965/vec4: Append uniform variables to the gather table

Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 0f22829..8dee915 100644 --- a/src/mesa/drivers/dri/i965/brw_

[Mesa-dev] [RFC PATCH 31/40] i965/fs: Set limitation for amount of UBO push constant entries

We set the same 16-register limitation used in assign_constant_locations() when assigning UBOs as push constants. Otherwise, just fall-back to using pull constant loads. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 de

Re: [Mesa-dev] [Nouveau] [PATCH 2/2] nvc0: regenerate rnndb headers

On 31/12/14 03:42, Ilia Mirkin wrote: > The headers hadn't been regenerated in a long time and had seen a number > of manual modifications. A few changes: > - remove nvc0_2d entirely, use the nv50 header which has the nvc0 >values too > - remove 3ddefs, it's identical to the nv50 file > - mo

[Mesa-dev] [Bug 86837] kodi segfault since auxiliary/vl: rework the build of the VL code

https://bugs.freedesktop.org/show_bug.cgi?id=86837 --- Comment #16 from bgunte...@gmail.com --- I can also confirm that this patch works. Running OpenGL version:2.1 Mesa 10.4.0(git-fb3f7c0) great work! -- You are receiving this mail because: You are the assignee for the bug. __

Re: [Mesa-dev] [PATCH:mesa] Bracket arguments to tr so they work with Solaris tr

Hi Alan, On 03/01/15 22:28, Alan Coopersmith wrote: > https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.69/html_node/Limitations-of-Usual-Tools.html#index-g_t_0040command_007btr_007d-1842 > > Without this fix, egl fails to build on Solaris, with the error: > > :0:22: error: '_

Re: [Mesa-dev] [PATCH] i965: Implement WaCsStallAtEveryFourthPipecontrol on IVB/BYT.

On Wed, Nov 12, 2014 at 11:17:55AM -0800, Kenneth Graunke wrote: > According to the documentation, we need to do a CS stall on every fourth > PIPE_CONTROL command to avoid GPU hangs. The kernel does a CS stall > between batches, so we only need to count the PIPE_CONTROLs in our batches. > > v2: G

[Mesa-dev] [Bug 86837] kodi segfault since auxiliary/vl: rework the build of the VL code

https://bugs.freedesktop.org/show_bug.cgi?id=86837 --- Comment #17 from bgunte...@gmail.com --- (In reply to Andy Furniss from comment #13) > (In reply to Emil Velikov from comment #12) > > Seems like Christian dropped the link with the tentative fix. > > http://patchwork.freedesktop.org/patch/394

Re: [Mesa-dev] [PATCH:mesa] Bracket arguments to tr so they work with Solaris tr

On 01/ 4/15 11:34 AM, Emil Velikov wrote: Hi Alan, On 03/01/15 22:28, Alan Coopersmith wrote: https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.69/html_node/Limitations-of-Usual-Tools.html#index-g_t_0040command_007btr_007d-1842 Without this fix, egl fails to build on Solaris

Re: [Mesa-dev] [PATCH 3/3] glx/dri3: Request non-vsynced Present for swapinterval zero.

On 17/12/14 05:20, Mario Kleiner wrote: > On 12/17/2014 05:49 AM, Keith Packard wrote: >> Mario Kleiner writes: >> >>> It's just that i need access to both, the old behaviour i described, and >>> the new "drop frame" behaviour, and i need a way to select what i want >>> at runtime via api without

Re: [Mesa-dev] Submitting more shaders to shader-db?

On Sun, Jan 4, 2015 at 10:20 AM, Kenneth Graunke wrote: > On Sunday 04 January 2015 09:36:40 Aras Pranckevicius wrote: > > Is it possible to submit more shaders into whatever shader-db is typically > > used by Mesa developers to test compiler optimizations on? I could package > > up some built-in

Re: [Mesa-dev] [PATCH 4/4] i965: Implemente a tiled fast-path for glReadPixels and glGetTexImage

I just did a very cursory review. I assume someone smarter than me will do a real review, but if not, feel free to ping me. I think all the comments apply to both functions. On Sat, Jan 03, 2015 at 11:54:15AM -0800, Jason Ekstrand wrote: > From: Sisinty Sasmita Patra > > Added intel_readpixels_

[Mesa-dev] [PATCH 1/4] vbo: ignore primitive restart if FixedIndex is enabled in DrawArrays

From: Marek Olšák From GL 4.4 Core profile: If both PRIMITIVE_RESTART and PRIMITIVE_RESTART_FIXED_INDEX are enabled, the index value determined by PRIMITIVE_RESTART_FIXED_INDEX is used. If PRIMITIVE_RESTART_FIXED_INDEX is enabled, primitive restart is not performed for array elements tra

[Mesa-dev] [PATCH 4/4] tgsi: add uses_centroid into tgsi_shader_info

From: Marek Olšák --- src/gallium/auxiliary/tgsi/tgsi_scan.c | 3 +++ src/gallium/auxiliary/tgsi/tgsi_scan.h | 1 + 2 files changed, 4 insertions(+) diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c b/src/gallium/auxiliary/tgsi/tgsi_scan.c index eb313e4..6210ebd 100644 --- a/src/gallium/auxi

[Mesa-dev] [PATCH 3/4] st/mesa: ignore primitive restart if FixedIndex is enabled in DrawArraysIndirect

From: Marek Olšák From GL 4.4 Core profile: If both PRIMITIVE_RESTART and PRIMITIVE_RESTART_FIXED_INDEX are enabled, the index value determined by PRIMITIVE_RESTART_FIXED_INDEX is used. If PRIMITIVE_RESTART_FIXED_INDEX is enabled, primitive restart is not performed for array elements tra

[Mesa-dev] [PATCH 2/4] st/mesa: fix GL_PRIMITIVE_RESTART_FIXED_INDEX

From: Marek Olšák Cc: 10.2 10.3 10.4 --- src/mesa/state_tracker/st_draw.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/state_tracker/st_draw.c b/src/mesa/state_tracker/st_draw.c index 64d6ef5..b6ccdd7 100644 --- a/src/mesa/state_tracker/st_draw.c +++ b/src/mesa

Re: [Mesa-dev] [PATCH 3/4] st/mesa: ignore primitive restart if FixedIndex is enabled in DrawArraysIndirect

FWIW the piglit you posted recently (arb_draw_indirect-draw-arrays-prim-restart) works with nvc0 with upstream mesa as-is. (But fails on llvmpipe/softpipe.) On Sun, Jan 4, 2015 at 4:44 PM, Marek Olšák wrote: > From: Marek Olšák > > From GL 4.4 Core profile: > > If both PRIMITIVE_RESTART and PR

Re: [Mesa-dev] [PATCH 3/4] st/mesa: ignore primitive restart if FixedIndex is enabled in DrawArraysIndirect

Nice. BTW this patch is unrelated to the test. This patch tries to fix the fixed index case, while the test only validates normal primitive restart. Marek On Sun, Jan 4, 2015 at 10:54 PM, Ilia Mirkin wrote: > FWIW the piglit you posted recently > (arb_draw_indirect-draw-arrays-prim-restart) work

[Mesa-dev] [PATCH] nv50/ir: fix texture offsets in release builds

assert's get compiled out in release builds, so they can't be relied upon to perform logic. Reported-by: Pierre Moreau Signed-off-by: Ilia Mirkin Cc: "10.2 10.3 10.4" --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp | 3 ++- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering

[Mesa-dev] [PATCH 11/13] radeonsi: do not define FACE as an ordinary PS input

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_state_shaders.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index de12b4e..437dd95 100644 --- a/src/gallium/drivers/r

[Mesa-dev] [PATCH 01/13] radeonsi: reduce the size of si_pm4_state

From: Marek Olšák - the relocs array is unused, remove it - ndw is at most 115 (init), set 140 as the maximum - compute needs 4 buffers per state, graphics only needs 1; set 4 as the maximum --- src/gallium/drivers/radeonsi/si_pm4.c | 6 +- src/gallium/drivers/radeonsi/si_pm4.h | 9 ++---

[Mesa-dev] [PATCH 02/13] radeonsi: remove init config from states

From: Marek Olšák It really doesn't do anything there. --- src/gallium/drivers/radeonsi/si_hw_context.c | 3 +-- src/gallium/drivers/radeonsi/si_pipe.c | 1 + src/gallium/drivers/radeonsi/si_pipe.h | 1 + src/gallium/drivers/radeonsi/si_pm4.c| 1 - src/gallium/drivers/radeons

[Mesa-dev] [PATCH 08/13] radeonsi: implement VERTEXID_NOBASE and BASEVERTEX system values

From: Marek Olšák Only done for completeness. Not used by anything yet. Tested by advertising PIPE_CAP_VERTEXID_NOBASE. --- src/gallium/drivers/radeonsi/si_shader.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/ra

[Mesa-dev] [PATCH 05/13] radeonsi: use ordered compares for SSG and face selection

From: Marek Olšák Ordered compares are what you have in C. Unordered compares are the result of negating ordered compares (they return true if either argument is NaN). That special NaN behavior is completely useless here, and unordered compares produce horrible code with all stable LLVM versions

[Mesa-dev] [PATCH 13/13] radeonsi: only set BC_OPTIMIZE_DISABLE when necessary

From: Marek Olšák SPI_PS_IN_CONTROL is moved into the SPI mapping state. --- src/gallium/drivers/radeonsi/si_pipe.h | 1 + src/gallium/drivers/radeonsi/si_state_shaders.c | 20 ++-- 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/rade

[Mesa-dev] [PATCH 04/13] radeonsi: enable LLVM optimizations that assume no NaNs for non-compute shaders

From: Marek Olšák --- src/gallium/drivers/radeon/radeon_llvm_emit.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/radeon/radeon_llvm_emit.c b/src/gallium/drivers/radeon/radeon_llvm_emit.c index dc871d7..e3be72c 100644 --- a/src/gallium/drivers/radeon/radeon_llvm_emit.c

[Mesa-dev] [PATCH 12/13] radeonsi: remove color_two_side from the shader key

From: Marek Olšák This can be done using the SPI mapping only. If two_side is disabled, VS COLOR is loaded to both PS COLOR and PS BCOLOR inputs. The disadvantage is that the PS always chooses the color according to FACE even though two_side is disabled. Since PS color inputs can only be used i

[Mesa-dev] [PATCH 06/13] radeonsi: clarify a hw bug in shader exports

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_shader.c | 15 ++- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index eb762c0..aa051cb 100644 --- a/src/gallium/drivers/radeons

[Mesa-dev] [PATCH 10/13] radeonsi: remove flatshade from the shader key

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_pipe.h | 1 + src/gallium/drivers/radeonsi/si_shader.h| 1 - src/gallium/drivers/radeonsi/si_state_shaders.c | 12 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_

[Mesa-dev] [PATCH 03/13] radeonsi: remove unused and not useful variables

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_pipe.h | 2 -- src/gallium/drivers/radeonsi/si_state.c | 3 +-- src/gallium/drivers/radeonsi/si_state.h | 2 -- 3 files changed, 1 insertion(+), 6 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeo

[Mesa-dev] [PATCH 09/13] radeonsi: remove special handling of TGSI_INTERPOLATE_COLOR in shader codegen

From: Marek Olšák It doesn't do anything useful. And colors are floating-point, so we can use fs.interp, remove "flatshade" from the shader key, and rely on the FLAT_SHADE state only (in the next patch). --- src/gallium/drivers/radeonsi/si_shader.c | 17 +++-- 1 file changed, 11 inse

[Mesa-dev] [PATCH 07/13] radeonsi: fix VertexID for OpenGL

From: Marek Olšák This fixes all failing piglit VertexID tests. Cc: 10.4 --- src/gallium/drivers/radeonsi/si_shader.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index aa051cb..f

[Mesa-dev] [PATCH 3/3] vc4: Skip storing the Z/S contents when it's invalidated.

Improves framerate of 5 seconds of es2gears by 1.57473% +/- 0.669409% (n=67). --- src/gallium/drivers/vc4/vc4_context.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/gallium/drivers/vc4/vc4_context.c b/src/gallium/drivers/vc4/vc4_context.c index 62f77b3..4c84bd3 100644 ---

[Mesa-dev] [PATCH 1/3] egl: Inform the client API when ancillary buffers may become undefined.

This is part of the EGL spec, and is useful for a tiled renderer to avoid the memory bandwidth cost of storing the depth/stencil buffers. --- include/GL/internal/dri_interface.h | 1 + src/egl/drivers/dri2/egl_dri2.c | 36 + src/egl/drivers/dri2/egl_dri

[Mesa-dev] [PATCH 2/3] gallium: Plumb the swap INVALIDATE_ANCILLARY flag through more layers.

v2: Instead of telling the driver that the window system ancillaries have been invalidated (when the driver doesn't know which of its buffers are the window system's!), introduce a method for invalidating specific surfaces. --- src/gallium/include/pipe/p_context.h | 11 +++

Re: [Mesa-dev] [PATCH] i965: Implement WaCsStallAtEveryFourthPipecontrol on IVB/BYT.

On Sunday, January 04, 2015 12:03:01 PM Ben Widawsky wrote: > On Wed, Nov 12, 2014 at 11:17:55AM -0800, Kenneth Graunke wrote: > > According to the documentation, we need to do a CS stall on every fourth > > PIPE_CONTROL command to avoid GPU hangs. The kernel does a CS stall > > between batches, s

[Mesa-dev] [Bug 86837] kodi segfault since auxiliary/vl: rework the build of the VL code

https://bugs.freedesktop.org/show_bug.cgi?id=86837 --- Comment #18 from bgunte...@gmail.com --- (In reply to bgunteriv from comment #17) > (In reply to Andy Furniss from comment #13) > > (In reply to Emil Velikov from comment #12) > > > Seems like Christian dropped the link with the tentative fix.

Re: [Mesa-dev] [PATCH 3/3] glx/dri3: Request non-vsynced Present for swapinterval zero.

On 12/16/2014 11:22 PM, Mathias Fröhlich wrote: Hi, On Tuesday, December 16, 2014 19:30:04 Mario Kleiner wrote: Hmm. For benchmarking i think i'd consider that a mild form of cheating. You get higher fps because you skip processing like the whole gpu blit overhead and host processing overhead

Re: [Mesa-dev] [PATCH 1/2] gallium/st: Clean up Haiku depth mapping, fix colorspace errors

On 2014-12-29 16:55, Roland Scheidegger wrote: Am 27.12.2014 um 18:41 schrieb Ilia Mirkin: On Sat, Dec 27, 2014 at 1:13 AM, Alexander von Gluck IV wrote: --- src/gallium/state_trackers/hgl/hgl.c | 48 + 1 files changed, 19 insertions(+), 29 deletions(-) @@

Re: [Mesa-dev] [PATCH 091/133] nir: Add a pass to lower local variable accesses to SSA values

Ok, I'm going to try reviewing this again. I'm pasting the latest version of the file from review/nir-v1 and replying to that so that I won't get confused between all the various changes and reorganizing things. Here we go! > /* > * Copyright © 2014 Intel Corporation > * > * Permission is hereb

Re: [Mesa-dev] [PATCH 1/2] gallium/st: Clean up Haiku depth mapping, fix colorspace errors

On 2014-12-27 11:41, Ilia Mirkin wrote: On Sat, Dec 27, 2014 at 1:13 AM, Alexander von Gluck IV wrote: --- src/gallium/state_trackers/hgl/hgl.c | 48 + 1 files changed, 19 insertions(+), 29 deletions(-) diff --git a/src/gallium/state_trackers/hgl/hgl.c b/s

Re: [Mesa-dev] [PATCH] swrast: Build fix for darwin

On 2015-01-03 10:00, Emil Velikov wrote: On 02/01/15 04:14, Jeremy Huddleston Sequoia wrote: This is certainly not the best solution to the problem, so I'm just sending this patch to the list to get the discussion started on the best way to solve this problem. Currently, any platform that does

Re: [Mesa-dev] [PATCH 094/133] nir: Add a pass to lower global variables to local variables

On Tue, Dec 16, 2014 at 1:11 AM, Jason Ekstrand wrote: > --- > src/glsl/Makefile.sources | 1 + > src/glsl/nir/nir.h| 2 + > src/glsl/nir/nir_lower_global_vars_to_local.c | 107 > ++ > 3 files changed, 110 insertions(+)

Re: [Mesa-dev] [PATCH 1/4] vbo: ignore primitive restart if FixedIndex is enabled in DrawArrays

On Sunday, January 04, 2015 10:44:17 PM Marek Olšák wrote: > From: Marek Olšák > > From GL 4.4 Core profile: > > If both PRIMITIVE_RESTART and PRIMITIVE_RESTART_FIXED_INDEX are > enabled, the index value determined by PRIMITIVE_RESTART_FIXED_INDEX is > used. If PRIMITIVE_RESTART_FIXED_INDE

Re: [Mesa-dev] [RFC PATCH 05/40] i965/gen7.5: Enable hardware-generated binding tables on render path.

On Sunday, January 04, 2015 04:04:19 PM Abdiel Janulgue wrote: > This patch implements the binding table enable command which is also > used to allocate a binding table pool where where hardware-generated > binding table entries are flushed into. > > Each binding table offset in the binding table

Re: [Mesa-dev] [RFC PATCH 06/40] i965/gen7.5: Enable hardware-generated binding tables in blorp path

On Sunday, January 04, 2015 04:04:20 PM Abdiel Janulgue wrote: > Signed-off-by: Abdiel Janulgue > --- > src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp > b/src/mesa/drivers/dri/i965/gen7_blorp.cpp > ind

Re: [Mesa-dev] [RFC PATCH 10/40] i965/blorp: Update hw-binding table entries for blorp.

On Sunday, January 04, 2015 04:04:24 PM Abdiel Janulgue wrote: > Update the hw-generated binding table for blorp SURFACE_STATE entries. > > Signed-off-by: Abdiel Janulgue > --- > src/mesa/drivers/dri/i965/gen6_blorp.cpp | 35 > > 1 file changed, 26 insertions(+)

Re: [Mesa-dev] [PATCH 092/133] nir: Add a pass to lower local variables to registers

On Tue, Dec 16, 2014 at 1:11 AM, Jason Ekstrand wrote: > --- > src/glsl/Makefile.sources | 1 + > src/glsl/nir/nir.h | 2 + > src/glsl/nir/nir_lower_locals_to_regs.c | 313 > > 3 files changed, 316 insertions(+) > create mo

Re: [Mesa-dev] [PATCH 092/133] nir: Add a pass to lower local variables to registers

Oh, and I forgot... can we rename this to lower_local_to_regs_scalar or at least add a note that this won't work for vec4 backends yet due to the different indexing? On Tue, Dec 16, 2014 at 1:11 AM, Jason Ekstrand wrote: > --- > src/glsl/Makefile.sources | 1 + > src/glsl/nir/n

Re: [Mesa-dev] [PATCH 093/133] nir: Add a pass for lowering input/output loads/stores

I'd also like to rename or at least note that this is a scalar-only thing for now... otherwise, Reviewed-by: Connor Abbott On Tue, Dec 16, 2014 at 1:11 AM, Jason Ekstrand wrote: > --- > src/glsl/Makefile.sources | 1 + > src/glsl/nir/nir.h | 2 + > src/glsl/nir/nir_lower_io.c |

Re: [Mesa-dev] [PATCH 095/133] nir/glsl: Generate SSA NIR

Except for the minor stale comment and assuming you checked that we don't call nir_create_local_reg() anymore, Reviewed-by: Connor Abbott On Tue, Dec 16, 2014 at 1:11 AM, Jason Ekstrand wrote: > With this commit, the GLSL IR -> NIR pass generates NIR in more-or-less SSA > form. It's SSA in th

Re: [Mesa-dev] [PATCH 097/133] nir/validate: Ensure that outputs are write-only and inputs are read-only

I'm not so sure how I feel about checking that outputs are write-only... eventually we'll want to do lower_input_reads in NIR itself, at which point we'll need to remove that part from the validator. At the same time, for now this is somewhat useful. I'm just not sure if it's worth it (making sure

Re: [Mesa-dev] [PATCH 096/133] i965/fs_nir: Use the new variable lowering code

Reviewed-by: Connor Abbott Nice job getting this variable lowering stuff all done! On Tue, Dec 16, 2014 at 1:11 AM, Jason Ekstrand wrote: > This commit switches us over to the new variable lowering code which is > capable of properly handling lowering indirects as we go. > --- > src/mesa/driv

Re: [Mesa-dev] [PATCH 099/133] nir: Vectorize intrinsics

Reviewed-by: Connor Abbott Nice to see that this idea worked out well! On Tue, Dec 16, 2014 at 1:11 AM, Jason Ekstrand wrote: > We used to have the number of components built into the intrinsic. This > meant that all of our load/store intrinsics had vec1, vec2, vec3, and vec4 > variants. Thi

Re: [Mesa-dev] [PATCH 098/133] nir: Remove the old variable lowering code

Reviewed-by: Connor Abbott On Tue, Dec 16, 2014 at 1:11 AM, Jason Ekstrand wrote: > --- > src/glsl/Makefile.sources |1 - > src/glsl/nir/nir_lower_variables_scalar.c | 1249 > - > 2 files changed, 1250 deletions(-) > delete mode 100644 src/glsl/

Re: [Mesa-dev] [PATCH 105/133] i965/fs_nir: Implement the ARB_gpu_shader5 interpolation intrinsics

This is a general question for the interpolation support: Why are we using the variable-based intrinsics directly, instead of lowering it to something index-based in the lower_io pass just like we do for normal inputs? On Tue, Dec 16, 2014 at 1:12 AM, Jason Ekstrand wrote: > --- > src/mesa/dri

Re: [Mesa-dev] [PATCH 101/133] nir: Add gpu_shader5 interpolation intrinsics

On Tue, Dec 16, 2014 at 1:12 AM, Jason Ekstrand wrote: > --- > src/glsl/nir/nir_intrinsics.h | 32 +++- > src/glsl/nir/nir_lower_io.c | 16 ++-- > 2 files changed, 21 insertions(+), 27 deletions(-) > > diff --git a/src/glsl/nir/nir_intrinsics.h b/src/gls

Re: [Mesa-dev] [RFC PATCH 19/40] mesa: Change internal state flag to a 64-bits

On Sunday, January 04, 2015 04:04:33 PM Abdiel Janulgue wrote: > Existing state flag cannot publish additional values. That's not quite true - there are actually two available bits. However, I don't think we should be adding _NEW_WHATEVER flags. These are basically for Mesa internals, and we've

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