On Thu, Jun 27, 2019 at 9:55 AM Dongwon Kim wrote:
>
> set bit15 (Disable Rebacking for Compression) of CACHE_MODE_0 register
Repacking
With minor nits fixed. This series is:
Reviewed-by: Anuj Phogat
I'll push the series after testing with these changes. Thanks for the patches :)
&
On Thu, Jun 27, 2019 at 9:55 AM Dongwon Kim wrote:
>
> set bit15 (Disable Rebacking for Compression) of CACHE_MODE_0 register
Repacking
> if the gen attribute, 'disable_ccs_repack' is set.
>
> Signed-off-by: Dongwon Kim
> ---
> src/gallium/drivers/iris/iris_state.c | 10 ++
> 1 file chan
On Thu, Jun 27, 2019 at 9:55 AM Dongwon Kim wrote:
>
> set bit15 (Disable Rebacking for Compression) of CACHE_MODE_0 register
Disable Repacking
> if the gen attribute, 'disable_ccs_repack' is set.
>
> Signed-off-by: Dongwon Kim
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 1 +
> src/me
On Thu, Jun 27, 2019 at 9:55 AM Dongwon Kim wrote:
>
> add a new attribute, 'disable_ccs_repack' to gen_device info, which
> indicates whether repacking of components in certain pixel formats
> before compression needs to be disabled to keep the compatibility
> with decompression capability of dis
+mesa-dev
On Thu, Jun 20, 2019 at 12:20 PM Anuj Phogat wrote:
>
> I sent out comments on your older patch. They applies to this patch too.
> Split i965 and anv changes in separate patches.
>
> On Thu, Jun 20, 2019 at 11:25 AM Dongwon Kim wrote:
> >
> > Repacking
On Tue, Jun 4, 2019 at 9:20 AM Dongwon Kim wrote:
>
> Repacking components in certain pixel formats before compression
> shouldn't be done for EHL to keep the compatibility with decompression
> capability in its display controller.
>
> Signed-off-by: Dongwon Kim
> ---
> src/gallium/drivers/iris/
Topi, Are you also planning to send out a similar patch for Iris ?
Thanks
Anuj
On Mon, Apr 8, 2019 at 4:20 PM Anuj Phogat wrote:
>
> On Wed, Mar 27, 2019 at 9:47 AM Topi Pohjolainen
> wrote:
> >
> > Similarly to 1cc17fb731466c68586915acbb916586457b19bc
> >
&g
On Wed, Mar 27, 2019 at 9:47 AM Topi Pohjolainen
wrote:
>
> Similarly to 1cc17fb731466c68586915acbb916586457b19bc
>
> Fixes gpu hangs with dEQP-VK.tessellation.shader_input_output.barrier
>
> CC: Anuj Phogat
> CC: Clayton Craft
> Signed-off-by: Topi Pohjolainen
>
>
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looks fine to me.
Reviewed-by: Anuj Phogat
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_set_default_flag_reg(p, 0, 0);
>brw_MOV(p, offset(retype(payload, BRW_REGISTER_TYPE_UD), 1),
>offset(retype(implied_header, BRW_REGISTER_TYPE_UD), 1));
>brw_pop_insn_state(p);
> --
> 2.20.1
>
> ___
> mesa-dev m
Fixes all subgroup test failures in vulkancts on Icelake.
Series is:
Tested-by: Anuj Phogat
On Fri, Jan 18, 2019 at 4:09 PM Francisco Jerez wrote:
>
> Currently the execution type calculation will return a bogus value in
> cases like:
>
> mov_indirect(8) vgrf0:w, vgrf1:w
yload, BRW_REGISTER_TYPE_UD));
> brw_inst_set_sfid(devinfo, send, sfid);
> --
Reviewed-by: Anuj Phogat
> 2.20.1
>
> ___
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+ if (devinfo->gen >= 9 && devinfo->gen < 11)
> subslices = 4 * brw->screen->devinfo.num_slices;
>
>unsigned scratch_ids_per_subslice;
> --
> 2.19.1
>
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On Mon, Nov 26, 2018 at 11:47 AM Francisco Jerez wrote:
>
> Anuj Phogat writes:
>
> > L3 allocation table in h/w specification recommends using 4 KB
> > granularity for programming allocation fields in L3CNTLREG.
> >
> > Signed-off-by: Anuj Phogat
> >
Use L3 configuration specified in h/w specification.
V2: Drop configs which do under allocation of l3 cache.
Bump up the comment above table.
Signed-off-by: Anuj Phogat
Cc: Kenneth Graunke
Cc: Francisco Jerez
---
src/intel/common/gen_l3_config.c | 12 ++--
1 file changed, 6
Dropping this patch.
On Tue, Nov 13, 2018 at 2:34 PM Anuj Phogat wrote:
>
> Config#6 recommended by h/w specification causes multiple piglit
> regressions. Use config#9 instead which works well. Setting a weight
> here so that we get the desired config.
>
> Signed-off-by:
On Fri, Nov 16, 2018 at 2:52 PM Francisco Jerez wrote:
>
> Anuj Phogat writes:
>
> > On Fri, Nov 16, 2018 at 6:21 AM Eero Tamminen
> > wrote:
> >>
> >> Hi,
> >>
> >> On 16.11.2018 10.33, Francisco Jerez wrote:
> >> > Kenne
On Fri, Nov 16, 2018 at 6:21 AM Eero Tamminen wrote:
>
> Hi,
>
> On 16.11.2018 10.33, Francisco Jerez wrote:
> > Kenneth Graunke writes:
> [...]
> >> Perhaps we'll get both configs working, and then will want to be able
> >> to select between them. I question whether the additional URB is truly
No problem Ken.
On Tue, Nov 13, 2018 at 9:48 PM Kenneth Graunke
wrote:
> On Tuesday, November 13, 2018 2:33:58 PM PST Anuj Phogat wrote:
> > Use L3 configuration table specified in h/w specification.
> >
> > Signed-off-by: Anuj Phogat
> > Cc: Kenneth Graunke
>
Use L3 configuration table specified in h/w specification.
Signed-off-by: Anuj Phogat
Cc: Kenneth Graunke
Cc: Francisco Jerez
Cc: Lionel Landwerlin
---
src/intel/common/gen_l3_config.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/src/intel/common
L3 allocation table in h/w specification recommends using 4 KB
granularity for programming allocation fields in L3CNTLREG.
Signed-off-by: Anuj Phogat
Cc: Kenneth Graunke
Cc: Francisco Jerez
Cc: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_defines.h | 1 +
src/mesa/drivers/dri/i965
Signed-off-by: Anuj Phogat
Cc: Kenneth Graunke
Cc: Francisco Jerez
Cc: Lionel Landwerlin
---
src/intel/common/gen_l3_config.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index 079608198bc
L3 allocation table in h/w specification recommends using 4 KB
granularity for programming allocation fields in L3CNTLREG.
Signed-off-by: Anuj Phogat
Cc: Kenneth Graunke
Cc: Francisco Jerez
Cc: Lionel Landwerlin
---
src/intel/genxml/gen11.xml | 1 +
src/intel/vulkan/genX_cmd_buffer.c
Config#6 recommended by h/w specification causes multiple piglit
regressions. Use config#9 instead which works well. Setting a weight
here so that we get the desired config.
Signed-off-by: Anuj Phogat
Cc: Kenneth Graunke
Cc: Francisco Jerez
Cc: Lionel Landwerlin
---
src/intel/common
Lionel,
I have this patch along with few other patches in my 'icl-urb-configs'
branch
at https://github.com/aphogat/mesa. But, I'm getting many piglit regressions
with these patches. That's the reason I haven't sent them out to the list.
I also
talked to Ken about my changes. Unfortunately we have
The default setting of this bit is not the desirable behavior.
WA_1406697149
Signed-off-by: Anuj Phogat
---
src/intel/genxml/gen11.xml | 1 +
src/intel/vulkan/genX_cmd_buffer.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml
The default setting of this bit is not the desirable behavior.
WA_1406697149
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_defines.h | 1 +
src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965
WA_1606682166:
Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
Disable the Sampler state prefetch functionality in the SARB by
programming 0xB000[30] to '1'. This is to be done at boot time and
the feature must remain disabled permanently.
Signed-off-by: An
Topi Pohjolainen
Signed-off-by: Anuj Phogat
Cc: Mark Janes
---
Latest kernel from drm-tip do have this workaround implemented
but we're seeing few deqp regressions with that kernel. I'm
adding this workaround to Mesa to make some progress in ICL
testing on CI. We can always revert
gt;
> Fixes:
> KHR-GL46.tessellation_shader.tessellation_shader_tc_barriers.barrier_guarded_read_write_calls
>
> CC: Anuj Phogat
> CC: Mark Janes
> Signed-off-by: Topi Pohjolainen
> ---
> src/intel/compiler/brw_fs.cpp | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff -
On Thu, Sep 20, 2018 at 11:01 PM Topi Pohjolainen
wrote:
>
> Fixes gpu hangs with Carchase and Manhattan.
>
> Cc: Anuj Phogat
> Signed-off-by: Topi Pohjolainen
> ---
> src/intel/compiler/brw_fs_visitor.cpp | 16 +---
> 1 file changed, 13 insertions(+), 3 del
Different ICL SKUs have different URB sizes.
Signed-off-by: Anuj Phogat
---
src/intel/dev/gen_device_info.c | 43 ++---
1 file changed, 29 insertions(+), 14 deletions(-)
diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index 3cece52a041
It fixes simulator error about h/w spec violation with piglit test:
glsl-1.50/execution/geometry/generate-zero-primitives.shader_test.
Simulator throws an error if dataLength < 1 for URB SIMD 8 write
message.
Signed-off-by: Anuj Phogat
Cc: Kenneth Graunke
Cc:
---
I doubt if sett
h/w specification requires this bit to be always set.
V2: Fix bit mask (Chris Wilson)
Suggested-by: Kenneth Graunke
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_defines.h | 4
src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++
2 files changed, 11 insertions
On Tue, Aug 28, 2018 at 10:57 AM Chris Wilson wrote:
>
> Quoting Anuj Phogat (2018-08-28 18:53:59)
> > h/w specification requires this bit to be always set.
> >
> > Suggested-by: Kenneth Graunke
> > Signed-off-by: Anuj Phogat
> > ---
> > src/me
h/w specification requires this bit to be always set.
Suggested-by: Kenneth Graunke
Signed-off-by: Anuj Phogat
---
src/intel/genxml/gen11.xml| 5 +
src/intel/vulkan/genX_state.c | 14 ++
2 files changed, 19 insertions(+)
diff --git a/src/intel/genxml/gen11.xml b/src/intel
h/w specification requires this bit to be always set.
Suggested-by: Kenneth Graunke
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_defines.h | 4
src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++
2 files changed, 11 insertions(+)
diff --git a/src/mesa/drivers
On Mon, Aug 20, 2018 at 2:13 PM Kenneth Graunke wrote:
>
> On Monday, August 20, 2018 10:26:29 AM PDT Anuj Phogat wrote:
> > On Mon, Aug 20, 2018 at 12:18 AM Kenneth Graunke wrote:
> [snip]
> > > I don't know if people are trying to enable pre-emption during GPGPU
&g
On Mon, Aug 20, 2018 at 12:18 AM Kenneth Graunke wrote:
>
> On Friday, August 17, 2018 5:13:25 PM PDT Anuj Phogat wrote:
> > It fixes simulator warnings in piglit tests complaining about missing
> > support for headerless sampler messages for pre-emptable contexts.
> &g
It fixes simulator warnings in vulkancts tests complaining about missing
support for headerless sampler messages for pre-emptable contexts.
Bit 5 in SAMPLER MODE register is newly introduced for ICLLP.
Signed-off-by: Anuj Phogat
---
src/intel/genxml/gen11.xml| 5 +
src/intel/vulkan
Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to
disable prefetching of binding tables for ICLLP A0 and B0
steppings. We have a similar patch for i965 driver in Mesa
commit a5889d70.
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/genX_pipeline.c | 21 +++--
1
It fixes simulator warnings in piglit tests complaining about missing
support for headerless sampler messages for pre-emptable contexts.
Bit 5 in SAMPLER MODE register is newly introduced for ICLLP.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_defines.h | 4
src/mesa
> *
> * 4X MSAA sample index / number layout
> @@ -107,7 +107,7 @@ gen6_get_sample_position(struct gl_context *ctx,
> void
> gen6_set_sample_maps(struct gl_context *ctx)
> {
> - uint8_t map_2x[2] = {0, 1};
> + uint8_t map_2x[2] = {1, 0};
> uint8_t
t;
> ___
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It's EXT_base_instance for gles.
With suggested changes to Subject:
Reviewed-by: Anuj Phogat
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checks in the code.
Signed-off-by: Anuj Phogat
---
src/intel/blorp/blorp_genX_exec.h | 7 +++
src/mesa/drivers/dri/i965/genX_state_upload.c | 14 +-
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/src/intel/blorp/blorp_genX_exec.h
b/src/intel/blorp
TCH0 :
> VARYING_SLOT_VAR0;
>} else if (vtn_var->mode != vtn_variable_mode_uniform) {
> vtn_warn("Location must be on input, output, uniform, sampler or "
> --
> 2.18.0
>
> ___
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> mesa-dev@li
Bump.
On Fri, Jun 1, 2018 at 2:40 PM Anuj Phogat wrote:
>
> CACHE_MODE_SS is not listed in gfxspecs table for user mode
> non-privileged registers. So, making any changes from Mesa
> will do nothing. Kernel is already setting this bit in
> CACHE_MODE_SS register which is saved/r
Bump
On Fri, Jun 1, 2018 at 2:40 PM Anuj Phogat wrote:
>
> CACHE_MODE_SS is not listed in gfxspecs table for user mode
> non-privileged registers. So, making any changes from Mesa
> will do nothing. Kernel is already setting this bit in
> CACHE_MODE_SS register which is saved/r
CACHE_MODE_SS is not listed in gfxspecs table for user mode
non-privileged registers. So, making any changes from Mesa
will do nothing. Kernel is already setting this bit in
CACHE_MODE_SS register which is saved/restored to/from
the HW context image.
Signed-off-by: Anuj Phogat
Cc: Lionel
CACHE_MODE_SS is not listed in gfxspecs table for user mode
non-privileged registers. So, making any changes from Mesa
will do nothing. Kernel is already setting this bit in
CACHE_MODE_SS register which is saved/restored to/from
the HW context image.
Signed-off-by: Anuj Phogat
Cc: Lionel
2x6 configuration with pci-id 0x3185 has same number of
banks (2) as 3x6 configuration (pci-id 0x3184).
Reported-by: Clayton Craft
Signed-off-by: Anuj Phogat
Cc:
Cc: Lionel Landwerlin
Cc: Francisco Jerez
---
src/intel/dev/gen_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Yes, I did. No regressions.
On Thu, May 10, 2018 at 12:09 PM, Jason Ekstrand wrote:
> Did you get a chance to test them?
>
>
> On May 10, 2018 11:58:54 Anuj Phogat wrote:
>
>> On Mon, May 7, 2018 at 2:56 PM, Jason Ekstrand
>> wrote:
>>>
>>> --
ORMAT_R8_UINT);
>
> default:
>assert(!"Unknown image format");
> --
> 2.5.0.400.gff86faf
>
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Both patches are:
Reviewed-by and Tested-by: Anuj Phogat
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vBuiltInFragCoord:
> nir_var->data.pixel_center_integer = b->pixel_center_integer;
> + /* fallthrough */
> + case SpvBuiltInSamplePosition:
> + nir_var->data.origin_upper_left = b->origin_upper_left;
> break;
>
> 2.17.0
>
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Reviewed-by: Anuj Phogat
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-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Reviewed-by: Anuj Phogat
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nLod = false,
>.variableMultisampleRate = true,
> --
> 2.5.0.400.gff86faf
>
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s/witho
This patch enables the Vulkan driver on Ice Lake h/w
with added warning about preliminary support.
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/anv_device.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 7522b7865c
On Thu, Apr 19, 2018 at 7:44 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:
> This didn't actually help the failing tests I'm looking at
> but hopefully has teeth elsewhere.
>
> CC: Jason Ekstrand
> CC: Jordan Justen
> CC: Anuj Phogat
> Signed-o
For the series:
Reviewed-by: Anuj Phogat
This might explain piglit GPU hangs or failures. I'll do a piglit run with
these patches.
Thanks
Anuj
On Tue, Apr 17, 2018 at 3:10 PM, Jason Ekstrand
wrote:
> ---
> src/mesa/drivers/dri/i965/genX_blorp_exec.c | 14 ++
> 1 fi
Signed-off-by: Anuj Phogat
---
include/pci_ids/i965_pci_ids.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 8716d758f0..c740a50bca 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids
On Wed, Feb 21, 2018 at 11:04 AM, Matt Turner wrote:
> On Wed, Feb 21, 2018 at 10:37 AM, Anuj Phogat wrote:
>> On Wed, Feb 21, 2018 at 9:22 AM, Rafael Antognolli
>> wrote:
>>> My understanding is that this commit is enough to make the driver try to
>>> initial
last patch in this series. Otherwise we'll
have a commit with ICL PCI IDs but missing compiler changes. Almost
nothing will work without the compiler patches.
>
> Rafael
>
> On Tue, Feb 20, 2018 at 09:15:08PM -0800, Matt Turner wrote:
>> From: Anuj Phogat
>>
>> S
On Wed, Feb 21, 2018 at 11:09 AM, Scott D Phillips
wrote:
> Anuj Phogat writes:
>
>> On Wed, Feb 21, 2018 at 10:00 AM, Scott D Phillips
>> wrote:
>>> Matt Turner writes:
>>>
>>>> From: Anuj Phogat
>>>>
>>>> Signed-off
On Wed, Feb 21, 2018 at 10:00 AM, Scott D Phillips
wrote:
> Matt Turner writes:
>
>> From: Anuj Phogat
>>
>> Signed-off-by: Anuj Phogat
>> ---
>> include/pci_ids/i965_pci_ids.h | 9 ++
>> src/intel/common/gen_device_info.c | 56
>> ++
On Thu, Feb 15, 2018 at 6:07 PM, Jason Ekstrand wrote:
> On Thu, Feb 15, 2018 at 5:44 PM, Anuj Phogat wrote:
>>
>> Signed-off-by: Anuj Phogat
>> ---
>> src/intel/vulkan/genX_pipeline.c | 7 +++
>> 1 file changed, 7 insertions(+)
>>
>> diff --gi
On Thu, Feb 15, 2018 at 6:14 PM, Jason Ekstrand wrote:
> I made a few fairly trivial comments but it all looks pretty good.
>
> Reviewed-by: Jason Ekstrand
Thanks for the quick review Jason.
>
> On Thu, Feb 15, 2018 at 5:44 PM, Anuj Phogat wrote:
>>
>> This series pr
On Thu, Feb 15, 2018 at 6:12 PM, Jason Ekstrand wrote:
>
>
> On Thu, Feb 15, 2018 at 5:44 PM, Anuj Phogat wrote:
>>
>> The PIPE_CONTROL command description says:
>>
>> "Whenever a Binding Table Index (BTI) used by a Render Taget Message
>> points
On Thu, Feb 15, 2018 at 6:13 PM, Jason Ekstrand wrote:
> On Thu, Feb 15, 2018 at 5:44 PM, Anuj Phogat wrote:
>>
>> Signed-off-by: Anuj Phogat
>> ---
>> src/intel/vulkan/genX_state.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> dif
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/genX_pipeline.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 784559380d..85391c93ca 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/genX_pipeline.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 85391c93ca..290d78e608 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/anv_entrypoints_gen.py | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_entrypoints_gen.py
b/src/intel/vulkan/anv_entrypoints_gen.py
index 1bab885180..c5a654f19b 100644
--- a/src/intel/vulkan
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/genX_state.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 54fb8634fd..f39508034f 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan
board Stall bit must
be set in this packet."
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/genX_cmd_buffer.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index ce47b8a1cc..e2b6c281e4 10
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/anv_private.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index d38dd9e422..009f5304f2 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan
Signed-off-by: Anuj Phogat
---
src/intel/Android.vulkan.mk | 21 +
src/intel/Makefile.sources | 4
src/intel/Makefile.vulkan.am | 7 ++-
src/intel/vulkan/meson.build | 2 +-
4 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/src/intel
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/anv_private.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 009f5304f2..9822afb81d 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/genX_pipeline.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 45ebe31de6..784559380d 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/anv_blorp.c | 3 +++
src/intel/vulkan/anv_device.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index d38b343671..d98bf8364d 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src
.
https://github.com/aphogat/mesa.git
Anuj Phogat (10):
anv/icl: Add gen11 mocs defines
anv/icl: Add #define genX
anv/icl: Don't set ResetGatewayTimer
anv/icl: Don't use SingleVertexDispatch
anv/icl: Don't use DISPATCH_MODE_SIMD4X2
anv/icl: Generate gen11 entry point func
+Ken
On Thu, Feb 15, 2018 at 11:11 AM, Anuj Phogat wrote:
> From PIPE_CONTROL command description in gfxspecs:
>
> "Whenever a Binding Table Index (BTI) used by a Render Taget Message
> points to a different RENDER_SURFACE_STATE, SW must issue a Render
> Target Cache Flush
I, PS Scoreboard Stall bit must
be set in this packet."
V2: Move the PIPE_CONTROL to update_renderbuffer_surfaces() in
brw_wm_surface_state.c (Ken).
Fixes a fulsim error and a GPU hang described in below JIRA.
JIRA: MD5-322
Signed-off-by: Anuj Phogat
---
src/mesa/driver
Sampling from hiz is enabled in i965 for GEN9+ but this feature has
been removed from gen11. So, this new flag will be useful to turn
the feature on/off for different gen h/w. It will be used later
in a patch adding device info for gen11.
Suggested-by: Kenneth Graunke
Signed-off-by: Anuj Phogat
On Thu, Feb 15, 2018 at 9:49 AM, Emil Velikov wrote:
> On 13 February 2018 at 19:15, Anuj Phogat wrote:
>> Signed-off-by: Anuj Phogat
>> ---
>> src/intel/Android.genxml.mk | 5 +
>> src/intel/Makefile.sources| 3 ++-
>> src/intel/genxml/genX_pa
On Tue, Feb 13, 2018 at 4:17 PM, Kenneth Graunke wrote:
> On Tuesday, February 13, 2018 11:15:16 AM PST Anuj Phogat wrote:
>> From PIPE_CONTROL command description in gfxspecs:
>>
>> "Whenever a Binding Table Index (BTI) used by a Render Taget Message
On Tue, Feb 13, 2018 at 4:25 PM, Kenneth Graunke wrote:
> On Tuesday, February 13, 2018 11:15:14 AM PST Anuj Phogat wrote:
>> On gen11+ AUX_HIZ is not a supported value for surfaces being
>> sampled by the 3D sampler.
>>
>> Signed-off-by: Anuj Phogat
>>
Sent this patch to ML by mistake :(. Reviewers can ignore this one for now.
Matt can send it out later with rest of his compiler changes.
On Tue, Feb 13, 2018 at 2:41 PM, Anuj Phogat wrote:
> From: Matt Turner
>
> ---
> src/intel/compiler/test_eu_validate.cpp | 1 +
> 1
From: Matt Turner
---
src/intel/compiler/test_eu_validate.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/compiler/test_eu_validate.cpp
b/src/intel/compiler/test_eu_validate.cpp
index f6c2b35625..d987311ef8 100644
--- a/src/intel/compiler/test_eu_validate.cpp
+++ b/src/intel/c
Signed-off-by: Anuj Phogat
---
This patch adds a big xml file. So I couldn't send the patch
to the list. Clamping down the patch so that reviewers can
actually see what i'm doing in [PATCH 01/16 ]. The whole
patch can be found in my 'review' branch on github.
src/intel/Makef
Signed-off-by: Anuj Phogat
---
This patch will be squashed with [PATCH 01/16]
src/intel/genxml/gen11.xml | 12
1 file changed, 12 insertions(+)
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 2490b0e25b..84020f7015 100644
--- a/src/intel/genxml/gen11.xml
ev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Series-is: Reviewed-by: Anuj Phogat
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
This series is also available at:
https://github.com/aphogat/mesa.git
Branch: review
On Tue, Feb 13, 2018 at 11:15 AM, Anuj Phogat wrote:
>
> This series prepares the driver to enable Ice Lake support
> in i965 driver. It adds gen11.xml, wires up the build
> infrastructure and make
On gen11+ AUX_HIZ is not a supported value for surfaces being
sampled by the 3D sampler.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src
StateCacheInvalidation is required on all gen7+ platforms. We
don't need to update this check for every new gen h/w unless
this requirement is changed. So, dropping the check for latest
gen h/w.
Signed-off-by: Anuj Phogat
---
src/intel/blorp/blorp_genX_exec.h | 2 +-
1 file changed, 1 inse
I, PS Scoreboard Stall bit must
be set in this packet."
Fixes a fulsim error and a GPU hang described in below JIRA.
JIRA: MD5-322
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/mesa/d
SIMD4x2 dispatch mode has been removed in GEN11. We're not using
it anyways in Mesa. Adding few asserts to make it explicit.
Signed-off-by: Anuj Phogat
---
src/intel/blorp/blorp_genX_exec.h | 4
src/mesa/drivers/dri/i965/genX_state_upload.c | 5 +
2 files chang
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 2c8c0f4b27..86c12e4d35 100644
--- a/src/mesa/drivers
Nothing is changed here from gen10 to gen11. So, just update
the assert.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_program.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_program.c
b/src/mesa/drivers/dri/i965/brw_program.c
Signed-off-by: Anuj Phogat
---
src/intel/blorp/blorp_genX_exec.h | 9 +
src/mesa/drivers/dri/i965/genX_state_upload.c | 9 +
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/src/intel/blorp/blorp_genX_exec.h
b/src/intel/blorp/blorp_genX_exec.h
index
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/Android.mk | 24 +++-
src/mesa/drivers/dri/i965/Makefile.am| 6 +-
src/mesa/drivers/dri/i965/Makefile.sources | 4
src/mesa/drivers/dri/i965/brw_blorp.c| 4
src/mesa/drivers
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