On Wed, Mar 27, 2019 at 4:05 PM Sagar Ghuge <sagar.gh...@intel.com> wrote:
>
> If predicate control is set to None, then in that case we can simply set
> flag reg/subreg number to zero. This allows round-tripping through the
> assembler/disassembler
>
> Signed-off-by: Sagar Ghuge <sagar.gh...@intel.com>
> ---
> src/intel/compiler/brw_eu_emit.c | 7 +++++++
> src/intel/compiler/brw_fs_generator.cpp | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/src/intel/compiler/brw_eu_emit.c
> b/src/intel/compiler/brw_eu_emit.c
> index 94e247e1a39..f59543db8df 100644
> --- a/src/intel/compiler/brw_eu_emit.c
> +++ b/src/intel/compiler/brw_eu_emit.c
> @@ -2267,6 +2267,13 @@ brw_fb_WRITE(struct brw_codegen *p,
> brw_inst_set_sfid(devinfo, insn, target_cache);
> brw_inst_set_compression(devinfo, insn, false);
>
> + if (brw_inst_pred_control(devinfo, insn) == BRW_PREDICATE_NONE) {
> + brw_inst_set_flag_subreg_nr(devinfo, insn, 0);
> + if (devinfo->gen >= 7) {
> + brw_inst_set_flag_reg_nr(devinfo, insn, 0);
> + }
> + }
> +
> if (devinfo->gen >= 6) {
> /* headerless version, just submit color payload */
> src0 = payload;
> diff --git a/src/intel/compiler/brw_fs_generator.cpp
> b/src/intel/compiler/brw_fs_generator.cpp
> index c24d4eb7cab..242450c605e 100644
> --- a/src/intel/compiler/brw_fs_generator.cpp
> +++ b/src/intel/compiler/brw_fs_generator.cpp
> @@ -307,6 +307,7 @@ fs_generator::fire_fb_write(fs_inst *inst,
> brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
> brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_flag_reg(p, 0, 0);
> brw_MOV(p, offset(retype(payload, BRW_REGISTER_TYPE_UD), 1),
> offset(retype(implied_header, BRW_REGISTER_TYPE_UD), 1));
> brw_pop_insn_state(p);
> --
> 2.20.1
>
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Change looks correct and harmless.
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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