Lionel,
I have this patch along with few other patches in my 'icl-urb-configs'
branch
at https://github.com/aphogat/mesa. But, I'm getting many piglit regressions
with these patches. That's the reason I haven't sent them out to the list.
I also
talked to Ken about my changes. Unfortunately we have no lead on what's
causing these regressions atm.
Thanks
Anuj
On Thu, Nov 8, 2018 at 4:26 AM Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:
> I forgot to Cc some people :)
>
> On 07/11/2018 13:31, Lionel Landwerlin wrote:
> > CNL configurations where given in increments of 2Kb, while ICL are
> > given in increments of 4Kb. We seem to have missed some updates in the
> > internal documentation.
> >
> > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
> > BSpec: 21166
> > ---
> > src/intel/common/gen_l3_config.c | 16 ++++++++++------
> > 1 file changed, 10 insertions(+), 6 deletions(-)
> >
> > diff --git a/src/intel/common/gen_l3_config.c
> b/src/intel/common/gen_l3_config.c
> > index b977c6ab136..079608198bc 100644
> > --- a/src/intel/common/gen_l3_config.c
> > +++ b/src/intel/common/gen_l3_config.c
> > @@ -137,12 +137,16 @@ static const struct gen_l3_config cnl_l3_configs[]
> = {
> > */
> > static const struct gen_l3_config icl_l3_configs[] = {
> > /* SLM URB ALL DC RO IS C T */
> > - {{ 0, 64, 64, 0, 0, 0, 0, 0 }},
> > - {{ 0, 64, 0, 16, 48, 0, 0, 0 }},
> > - {{ 0, 48, 0, 16, 64, 0, 0, 0 }},
> > - {{ 0, 32, 0, 0, 96, 0, 0, 0 }},
> > - {{ 0, 32, 96, 0, 0, 0, 0, 0 }},
> > - {{ 0, 32, 0, 16, 80, 0, 0, 0 }},
> > + {{ 0, 32, 32, 0, 0, 0, 0, 0 }},
> > + {{ 0, 32, 28, 0, 0, 0, 0, 0 }},
> > + {{ 0, 24, 0, 8, 28, 0, 0, 0 }},
> > + {{ 0, 16, 0, 0, 44, 0, 0, 0 }},
> > + {{ 0, 16, 12, 0, 0, 0, 0, 0 }},
> > + {{ 0, 16, 0, 0, 12, 0, 0, 0 }},
> > + {{ 0, 16, 80, 0, 0, 0, 0, 0 }},
> > + {{ 0, 16, 48, 0, 0, 0, 0, 0 }},
> > + {{ 0, 16, 44, 0, 0, 0, 0, 0 }},
> > + {{ 0, 32, 64, 0, 0, 0, 0, 0 }},
> > {{ 0 }}
> > };
> >
>
>
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