It fixes simulator error about h/w spec violation with piglit test:
glsl-1.50/execution/geometry/generate-zero-primitives.shader_test.
Simulator throws an error if dataLength < 1 for URB SIMD 8 write
message.
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
Cc: Kenneth Graunke <kenn...@whitecape.org>
Cc: <mesa-sta...@lists.freedesktop.org>
---
I doubt if setting final_gs_vertex_count to sources[1] is always
safe here. It is initialized to zero in case of above mentioned
piglit test. I'm not seeing any regressions in CI with this patch
and it fixes the simulation error.
---
src/intel/compiler/brw_fs.cpp | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 5b87991652d..4df332efe9b 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -1437,19 +1437,16 @@ fs_visitor::emit_gs_thread_end()
break;
}
}
- fs_reg hdr = abld.vgrf(BRW_REGISTER_TYPE_UD, 1);
- abld.MOV(hdr, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD)));
- inst = abld.emit(SHADER_OPCODE_URB_WRITE_SIMD8, reg_undef, hdr);
- inst->mlen = 1;
- } else {
- fs_reg payload = abld.vgrf(BRW_REGISTER_TYPE_UD, 2);
- fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 2);
- sources[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
- sources[1] = this->final_gs_vertex_count;
- abld.LOAD_PAYLOAD(payload, sources, 2, 2);
- inst = abld.emit(SHADER_OPCODE_URB_WRITE_SIMD8, reg_undef, payload);
- inst->mlen = 2;
}
+
+ fs_reg payload = abld.vgrf(BRW_REGISTER_TYPE_UD, 2);
+ fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 2);
+ sources[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
+ sources[1] = this->final_gs_vertex_count;
+ abld.LOAD_PAYLOAD(payload, sources, 2, 2);
+ inst = abld.emit(SHADER_OPCODE_URB_WRITE_SIMD8, reg_undef, payload);
+ inst->mlen = 2;
+
inst->eot = true;
inst->offset = 0;
}
--
2.17.1
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