Forgot it again
Fixes: b6347807a9 "radv: Generate icd files."
---
src/amd/vulkan/Makefile.am | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index 80937e38d3..99d9e578d8 100644
--- a/src/amd/vulkan
From: Mathias Fröhlich
Hi Brian,
The updated patch to be sure. The changes with removing the gl prefix lead to
an other small change in _tnl_import_array not to have attrib twice in the
argument list. Therefore the v2 again for review.
I did also rename the current values from curr_glattrib to c
Makes sense. Thanks
Reviewed-by: Jose Fonseca
On 09/03/18 00:00, Timothy Arceri wrote:
Calling __builtin_frame_address with a nonzero argument is unsafe
but is sometimes done for debugging purposes. Since this code is
part of some debug util code I'm assuming that is the case here
and using G
https://bugs.freedesktop.org/show_bug.cgi?id=105412
Bug ID: 105412
Summary: [OpenGL] [HD 7790] - VSYNC always ON in all videogames
Product: Mesa
Version: unspecified
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status:
From: Dave Airlie
It appears its quite legal to do image copies on multisample
images, however due to a bug in our txf handling and incomplete
tests we never actually noticed we didn't do it properly in radv.
This patch implements a compute shader to copy multiple samples
of an image to another
From: Dave Airlie
This is ported from the sb backend, there are some issues with
evergreen stacks on the boundary between entries and ALU_PUSH_BEFORE
instructions.
Whenever we are going to use a push before, we check the stack
usage and if we have to use the workaround, then we switch to
a separ
From: Roland Scheidegger
The logic would not work correctly for line lengths smaller than 1.0,
even a degenerated line with length 0 would still produce a fragment
with anyhwere between alpha 0.0 and 0.5.
---
src/gallium/auxiliary/draw/draw_pipe_aaline.c | 25 -
src/gall
Series is Tested-by: Ilia Mirkin
kmscube and weston both start. The terminal app in weston shows
correct colors. I got a (weston) crash when trying to run
egltri_wayland from mesa-demos, but that could be for a million
different reasons.
On Thu, Mar 8, 2018 at 12:36 PM, Daniel Stone wrote:
> Ad
On 9 March 2018 at 09:52, Bas Nieuwenhuizen wrote:
> Turns out they did not reset the patch number on release.
Oops and I think I suggested this, sorry!
for the series:
Reviewed-by: Dave Airlie
> ---
> src/amd/vulkan/radv_extensions.py | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(
patch set (1 through 9) Reviewed-by: Bruce Cherniak
> On Mar 7, 2018, at 7:32 PM, George Kyriazis wrote:
>
> ---
> src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp
> b/s
Reviewed-by: Ilia Mirkin
On Thu, Mar 8, 2018 at 8:05 AM, Thierry Reding wrote:
> From: Thierry Reding
>
> This adds support for framebuffer modifiers to Nouveau. This will be
> used by the Tegra driver to share metadata about the format of buffers
> (such as the tiling mode or compression).
>
>
Reviewed-by: Ilia Mirkin
On Thu, Mar 8, 2018 at 8:05 AM, Thierry Reding wrote:
> From: Thierry Reding
>
> Add a new macro that can be used to extract the tiling mode from a
> tile_mode value. This is will be used to determine the number of GOBs
> used in block linear mode.
>
> Acked-by: Emil Ve
Calling __builtin_frame_address with a nonzero argument is unsafe
but is sometimes done for debugging purposes. Since this code is
part of some debug util code I'm assuming that is the case here
and using GCC pragma to silence the warning.
Cc: José Fonseca
---
src/gallium/auxiliary/util/u_debug_
If the api version is too low, the loader clamps the application
requested version to the advertized version, which messes with
which extensions are enabled.
---
src/amd/vulkan/dev_icd.json.in| 7 --
src/amd/vulkan/meson.build| 34 +++-
src/amd/vulkan/radeo
Turns out they did not reset the patch number on release.
---
src/amd/vulkan/radv_extensions.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_extensions.py
b/src/amd/vulkan/radv_extensions.py
index 469b09a160..bfee1f76fa 100644
--- a/src/amd/vulkan/ra
On GFX9 whether the buffer size is interpreted as elements or bytes
depends on whether IDXEN is enabled in the instruction. If the index
is a constant zero, LLVM optimizes IDXEN to 0.
Now the size in elements is interpreted in bytes which of course
results in out of bounds accesses.
The correct f
On Thu, Mar 8, 2018 at 2:39 PM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:
> On 08/03/18 22:36, Jason Ekstrand wrote:
>
>
>> hash_table_foreach(brw->perfquery.oa_metrics_table, entry) {
>>struct brw_perf_query_info *query = entry->data;
>> - char config_path[256];
>
On 03/08/2018 06:50 AM, Samuel Pitoiset wrote:
> This pass moves load UBO operations just before their first use,
> loosely based on nir_opt_move_comparisons.
If I'm reading this correctly, it moves UBO loads closer to the first
use in the same block. My assumption is the benefit in the next patc
Reviewed-by: Bas Nieuwenhuizen
On Thu, Mar 8, 2018 at 5:30 PM, Samuel Pitoiset
wrote:
> Bit 0 enables VSRC0 (R in low bits, G high) and bit 2 enables
> VSRC1 (B in low bits, A high).
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/common/ac_nir_to_llvm.c | 5 +
> 1 file changed, 5 inser
On GFX9 whether the buffer size is interpreted as elements or bytes
depends on whether IDXEN is enabled in the instruction. If the index
is a constant zero, LLVM optimizes IDXEN to 0.
Now the size in elements is interpreted in bytes which of course
results in out of bounds accesses.
The correct f
I gave this a run on radeonsi and the results were mixed. On the one
hand we reduced some spills on the other hand we increase VGPR use and
max waves dropped. I wonder if we should look more closely into whats
going on here.
72280 shaders in 43328 tests
Totals:
SGPRS: 2930328 -> 2922464 (-0.27
On 08/03/18 22:36, Jason Ekstrand wrote:
hash_table_foreach(brw->perfquery.oa_metrics_table, entry) {
struct brw_perf_query_info *query = entry->data;
- char config_path[256];
+ char config_path[280];
What's with the bump?
Because the compiler is complain
On Thu, Mar 8, 2018 at 7:42 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:
> We want to reuse it later on.
>
> Signed-off-by: Lionel Landwerlin
> ---
> src/mesa/drivers/dri/i965/brw_context.h | 3 +
> src/mesa/drivers/dri/i965/brw_performance_query.c | 146
> ++
On 03/08/2018 02:23 PM, Ilia Mirkin wrote:
> On Thu, Mar 8, 2018 at 5:22 PM, Ilia Mirkin wrote:
>> On Thu, Mar 8, 2018 at 5:14 PM, Daniel Schürmann
>> wrote:
>>> From: Dave Airlie
>>>
>>> Signed-off-by: Dave Airlie
>>> ---
>>> src/compiler/shader_info.h| 1 +
>>> src/compiler/spirv/sp
This patch is
Reviewed-by: Ian Romanick
I think we should also add a flag for lowering this instruction as is
done in GLSL IR. You should then add some patterns to
nir_opt_algebraic.py that recognize open-code versions. It would also
be interesting to detect clamp() patterns and convert them t
On Thu, Mar 8, 2018 at 5:14 PM, Daniel Schürmann
wrote:
> From: Dave Airlie
>
> Signed-off-by: Dave Airlie
> ---
> src/compiler/shader_info.h| 1 +
> src/compiler/spirv/spirv_to_nir.c | 3 +++
> src/compiler/spirv/vtn_amd.c | 52
> +++
> src/c
On Thu, Mar 8, 2018 at 5:22 PM, Ilia Mirkin wrote:
> On Thu, Mar 8, 2018 at 5:14 PM, Daniel Schürmann
> wrote:
>> From: Dave Airlie
>>
>> Signed-off-by: Dave Airlie
>> ---
>> src/compiler/shader_info.h| 1 +
>> src/compiler/spirv/spirv_to_nir.c | 3 +++
>> src/compiler/spirv/vtn_amd.
On 08/03/18 21:17, Kenneth Graunke wrote:
On Thursday, March 8, 2018 7:42:49 AM PST Lionel Landwerlin wrote:
We already have the same function in brw_queryobj.c
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 13 ++---
1 file changed, 2 inser
---
src/amd/common/ac_nir_to_llvm.c | 53 +
1 file changed, 53 insertions(+)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 9b85069860..e78f4e8dcd 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir
From: Dave Airlie
These are needed for SPV_AMD_shader_trinary_minmax,
the AMD HW supports these.
Co-authored-by: Daniel Schürmann
Signed-off-by: Dave Airlie
---
src/compiler/nir/nir_opcodes.py | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/compiler/nir/nir_opcodes.py
From: Dave Airlie
Signed-off-by: Dave Airlie
---
src/compiler/shader_info.h| 1 +
src/compiler/spirv/spirv_to_nir.c | 3 +++
src/compiler/spirv/vtn_amd.c | 52 +++
src/compiler/spirv/vtn_private.h | 2 ++
4 files changed, 58 insertions(+)
di
---
src/amd/vulkan/radv_extensions.py | 1 +
src/amd/vulkan/radv_shader.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/amd/vulkan/radv_extensions.py
b/src/amd/vulkan/radv_extensions.py
index 469b09a160..12efaa04c6 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulk
Reviewed-by: Matt Turner
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mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
From: Ian Romanick
With some sets of optimization flags, GCC will generate warnings like
this:
src/mesa/main/texparam.c:2327:27: warning: ‘*((void *)&ip+12)’ may be used
uninitialized in this function [-Wmaybe-uninitialized]
params[3] = ip[3];
~~^~~
src/mes
https://bugs.freedesktop.org/show_bug.cgi?id=104229
--- Comment #2 from mercuriete ---
This bug is not longer valid due to this commit:
https://cgit.freedesktop.org/mesa/mesa/commit/?id=5b3979704df51f05a6f226ba3a10046df466d03d
Closing as resolved.
--
You are receiving this mail because:
You a
https://bugs.freedesktop.org/show_bug.cgi?id=104229
mercuriete changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
On Thursday, March 8, 2018 7:42:49 AM PST Lionel Landwerlin wrote:
> We already have the same function in brw_queryobj.c
>
> Signed-off-by: Lionel Landwerlin
> ---
> src/mesa/drivers/dri/i965/brw_performance_query.c | 13 ++---
> 1 file changed, 2 insertions(+), 11 deletions(-)
>
> diff
Yeah, I guess. Do we know for certain they don't work on any of the BSDs? If not
then I guess this is fine, and the other BSD maintainers can submit patches to
fix it.
Reviewed-by: Dylan Baker
Quoting Greg V (2018-03-08 11:23:02)
> On 3/8/2018 9:41 PM, Dylan Baker wrote:
> > Do vulkan drivers wo
From: Dave Airlie
This fixes a memory trashing crash (not the test) seen with
dEQP-GLES3.stress.draw.unaligned_data.random.203
on virgl.
Signed-off-by: Dave Airlie
---
src/gallium/auxiliary/util/u_vbuf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/
On Thu, Mar 8, 2018 at 11:58 AM, Eric Anholt wrote:
> Jason Ekstrand writes:
>
> > On Thu, Mar 8, 2018 at 8:45 AM, Dylan Baker wrote:
> >
> >> Quoting Jason Ekstrand (2018-03-07 20:22:51)
> >> > Yes, that is what happened. That said, wrote that patch in September
> and
> >> > you've had about
Jason Ekstrand writes:
> On Thu, Mar 8, 2018 at 8:45 AM, Dylan Baker wrote:
>
>> Quoting Jason Ekstrand (2018-03-07 20:22:51)
>> > Yes, that is what happened. That said, wrote that patch in September and
>> > you've had about 6 months to look at it. The only particularly active
>> Mesa
>> > co
On Wed, Mar 7, 2018 at 3:34 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> We can get it from si_screen.
Acked-by: Alex Deucher
> ---
> src/gallium/drivers/radeonsi/si_compute.c | 3 +--
> src/gallium/drivers/radeonsi/si_shader.h| 4 +---
> src/gallium/drivers/radeonsi/si_shader
Quoting Dylan Baker (2018-03-08 11:25:20)
> Quoting Greg V (2018-03-06 11:16:04)
> > e.g. libvdpau_radeonsi.so(.1(.0)) were pointing to the absolute
> > build-time path of libvdpau_radeonsi.so.1.0.0, which caused trouble
> > when packaging the libraries.
> > ---
> > bin/install_megadrivers.py | 2
On 3/8/2018 9:41 PM, Dylan Baker wrote:
Do vulkan drivers work on all of the BSDs?
I don't think anyone tried them on anything other than FreeBSD, but why
add extra conditionals?
Building them by default makes them more noticeable for e.g. package
maintainers :)
___
HI Daniel,
Am 08.03.2018 um 18:10 schrieb Daniel Schürmann:
---
src/amd/common/ac_nir_to_llvm.c | 66 +++--
1 file changed, 37 insertions(+), 29 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 9b85069860..
Hi Daniel,
Am 08.03.2018 um 18:10 schrieb Daniel Schürmann:
---
src/amd/common/ac_lower_subgroups.c | 50 ++---
1 file changed, 46 insertions(+), 4 deletions(-)
diff --git a/src/amd/common/ac_lower_subgroups.c
b/src/amd/common/ac_lower_subgroups.c
index d078
Quoting Greg V (2018-03-06 11:16:04)
> e.g. libvdpau_radeonsi.so(.1(.0)) were pointing to the absolute
> build-time path of libvdpau_radeonsi.so.1.0.0, which caused trouble
> when packaging the libraries.
> ---
> bin/install_megadrivers.py | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-By: George Kyriazis
mailto:george.kyria...@intel.com>>
On Mar 2, 2018, at 12:00 PM, Dylan Baker
mailto:dy...@pnwbakers.com>> wrote:
Otherwise SWR cannot be built with meson from an autotools generated
tarball, such as the 18.0.0-rc4 tarball.
CC: George Kyriazis
mailto:george.kyria...
On Wed, Mar 7, 2018 at 3:35 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> Tested by our OpenCL team.
>
> Fixes: 9c499e6759b26c5e "st/mesa: don't invoke st_finalize_texture &
> st_convert_sampler for TBOs"
Acked-by: Alex Deucher
> ---
> src/gallium/state_trackers/dri/dri2.c | 58
> +
On Wed, Mar 7, 2018 at 3:34 PM, Marek Olšák wrote:
> From: Marek Olšák
>
Reviewed-by: Alex Deucher
> ---
> src/amd/common/ac_gpu_info.c | 11 +++
> src/amd/common/ac_gpu_info.h | 2 ++
> 2 files changed, 13 insertions(+)
>
> diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/
Ping.
Quoting Dylan Baker (2018-03-02 10:00:15)
> Otherwise SWR cannot be built with meson from an autotools generated
> tarball, such as the 18.0.0-rc4 tarball.
>
> CC: George Kyriazis
> CC: Emil Velikov
> Fixes: 16bf81383080 ("meson/swr: re-shuffle generated files")
> Signed-off-by: Dylan Bak
On Wed, Mar 7, 2018 at 3:34 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> This is only required with the latest libdrm.
>
> This fixes 32-bit support with high addresses.
> (and possibly 64-bit support too because the high bits need to be masked out)
Acked-by: Alex Deucher
> ---
> src/galliu
Quoting Greg V (2018-03-06 11:16:04)
> e.g. libvdpau_radeonsi.so(.1(.0)) were pointing to the absolute
> build-time path of libvdpau_radeonsi.so.1.0.0, which caused trouble
> when packaging the libraries.
> ---
> bin/install_megadrivers.py | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
On Wed, Mar 7, 2018 at 3:34 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> Cc: 17.3 18.0
Reviewed-by: Alex Deucher
> ---
> src/amd/common/ac_gpu_info.c | 21 -
> src/amd/common/ac_gpu_info.h | 1 +
> src/gallium/drivers/radeonsi/
On Thu, Mar 8, 2018 at 11:51 AM, Marek Olšák wrote:
> From: Marek Olšák
>
> v2: pad with PKT2 NOPs on SI
Reviewed-by: Alex Deucher
> ---
> src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu
On Thu, Mar 8, 2018 at 8:45 AM, Dylan Baker wrote:
> Quoting Jason Ekstrand (2018-03-07 20:22:51)
> > Yes, that is what happened. That said, wrote that patch in September and
> > you've had about 6 months to look at it. The only particularly active
> Mesa
> > contributor who hasn't had access i
On 6 March 2018 at 19:16, Greg V wrote:
> e.g. libvdpau_radeonsi.so(.1(.0)) were pointing to the absolute
> build-time path of libvdpau_radeonsi.so.1.0.0, which caused trouble
> when packaging the libraries.
Patch looks correct, although CC-ing Dylan as our resident python expert.
Fixes: f7f1b30
Quoting Greg V (2018-03-06 11:16:03)
> ---
> meson.build | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/meson.build b/meson.build
> index d68460231c..e71f4ddd73 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -87,6 +87,8 @@ if (with_gles1 or with_gles2) an
Quoting Eric Anholt (2018-03-08 10:12:02)
> Greg V writes:
>
> > FreeBSD builds Mesa with --disable-glx-tls in autotools because:
> > https://github.com/dumbbell/test-tls-initial-exec
> >
> > Add the equivalent option to Meson.
> > ---
> > meson.build | 5 -
> > meson_options.txt | 6 +
On 2018-03-08 06:10 PM, Dylan Baker wrote:
>
> When I was given commit access I was told that I should wait 24 hours
> after sending patches unless they were trivial or fixed something
> critical, ie, without them you can't compile or nothing works.
FWIW, I think that's a good rule, and I follow
On 8 March 2018 at 18:12, Eric Anholt wrote:
> Greg V writes:
>
>> FreeBSD builds Mesa with --disable-glx-tls in autotools because:
>> https://github.com/dumbbell/test-tls-initial-exec
>>
>> Add the equivalent option to Meson.
>> ---
>> meson.build | 5 -
>> meson_options.txt | 6 +
On 26 February 2018 at 13:51, Eric Engestrom wrote:
> Cc: Keith Packard
> Signed-off-by: Eric Engestrom
> ---
> This will make Keith's addition much cleaner as well :)
Hey, every little helps. Fwiw
Reviewed-by: Emil Velikov
Another idea - make the wsi_*_{init,fini}_wsi kernel style stubs ;-)
Greg V writes:
> FreeBSD builds Mesa with --disable-glx-tls in autotools because:
> https://github.com/dumbbell/test-tls-initial-exec
>
> Add the equivalent option to Meson.
> ---
> meson.build | 5 -
> meson_options.txt | 6 ++
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
Eric Engestrom writes:
> I'm still slightly bothered by the build options inconsistency between
> autotools: reuse --with-platform=drm
> meson: new -D platform=display
>
> I'd be happy with either one being used everywhere, but from what you
> said last time I think you'd prefer to reus
Eric Engestrom writes:
> Cc: Keith Packard
> Signed-off-by: Eric Engestrom
Reviewed-by: Keith Packard
--
-keith
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Add support for XBGR2101010 and ABGR2101010.
Signed-off-by: Daniel Stone
Cc: Ilia Mirkin
---
src/egl/drivers/dri2/platform_wayland.c | 12
1 file changed, 12 insertions(+)
diff --git a/src/egl/drivers/dri2/platform_wayland.c
b/src/egl/drivers/dri2/platform_wayland.c
index 877f793
Add support for XBGR2101010 and ABGR2101010 formats.
Signed-off-by: Daniel Stone
---
src/gbm/backends/dri/gbm_dri.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c
index df20db40218..b3d6ceb15a3 100644
--- a/src/gbm/back
Hi,
On 8 March 2018 at 17:08, Ilia Mirkin wrote:
> On Thu, Mar 8, 2018 at 11:57 AM, Mario Kleiner
> wrote:
>> Under EGL there is matching of channel masks, so only X11+GLX is
>> problematic. Not sure if anything special would need to be done for
>> XWayland, haven't looked at that at all so far.
On 7 March 2018 at 14:34, Jason Ekstrand wrote:
> The original string map assumed that the mapping from strings to
> entrypoints was a bijection. This will not be true the moment we
> add entrypoint aliasing. This reworks things to be an arbitrary map
> from strings to non-negative signed intege
Reviewed-by: Marek Olšák
Marek
On Thu, Mar 8, 2018 at 11:50 AM, Michel Dänzer wrote:
> From: Michel Dänzer
>
> We were dropping the upper 32 bits, which caused assertion failures in
> some compute shader piglit tests with radeonsi since the commit below.
>
> Fixes: 752e96970303 ("compiler: Add
for the series,
Reviewed-by: Dylan Baker
Quoting Emil Velikov (2018-03-08 09:09:21)
> From: Emil Velikov
>
> The tool accepts the input and output files as arguments.
> There's no need for the redirection.
>
> Signed-off-by: Emil Velikov
> ---
> src/egl/Makefile.am | 4 ++--
> 1 file changed
On 08/03/18 17:00, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-03-08 15:42:53)
+static void
+read_gt_frequency(struct brw_context *brw,
+ struct brw_perf_query_object *obj)
+{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ uint32_t *start_reg = ob
From: Emil Velikov
The tool accepts the input and output files as arguments.
There's no need for the redirection.
Signed-off-by: Emil Velikov
---
src/egl/wayland/wayland-drm/Makefile.am | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/egl/wayland/wayland-drm/Makefi
From: Emil Velikov
The tool accepts the input and output files as arguments.
There's no need for the redirection.
Signed-off-by: Emil Velikov
---
src/egl/Makefile.am | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
index 9fcee9d2
From: Emil Velikov
The tool accepts the input and output files as arguments.
There's no need for the redirection.
Signed-off-by: Emil Velikov
---
src/vulkan/Makefile.am | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/vulkan/Makefile.am b/src/vulkan/Makefile.am
i
---
src/compiler/spirv/vtn_subgroup.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/vtn_subgroup.c
b/src/compiler/spirv/vtn_subgroup.c
index bd3143962b..73420b7e43 100644
--- a/src/compiler/spirv/vtn_subgroup.c
+++ b/src/compiler/spirv/vtn_subgroup
Co-authored-by: Connor Abbott
---
src/amd/common/ac_llvm_build.c | 475 +
src/amd/common/ac_llvm_build.h | 33 ++-
2 files changed, 507 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 5341eb3
This patch series implements the following SPIR-V capabilities for RADV:
GroupNonUniform
GroupNonUniformVote
GroupNonUniformArithmetic
GroupNonUniformBallot
GroupNonUniformShuffle
GroupNonUniformShuffleRelative
GroupNonUniformQuad
Not yet supported is the GroupNonUniformClustered capability due to
---
src/amd/common/ac_nir_to_llvm.c | 66 +++--
1 file changed, 37 insertions(+), 29 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 9b85069860..0f4cc32f15 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/
---
src/amd/vulkan/radv_device.c | 12 ++--
src/amd/vulkan/radv_shader.c | 6 +-
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 7a11e08f97..4200eb7d7d 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src
---
src/compiler/nir/nir_lower_subgroups.c | 5 ++---
src/compiler/nir/nir_opcodes.py| 12 ++--
2 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/src/compiler/nir/nir_lower_subgroups.c
b/src/compiler/nir/nir_lower_subgroups.c
index f18ad00c37..ea883c353e 100644
--- a
---
src/amd/common/ac_lower_subgroups.c | 50 ++---
1 file changed, 46 insertions(+), 4 deletions(-)
diff --git a/src/amd/common/ac_lower_subgroups.c
b/src/amd/common/ac_lower_subgroups.c
index d0782b481b..2be48e2ba1 100644
--- a/src/amd/common/ac_lower_subgroups.
---
src/amd/common/ac_llvm_build.c | 33 -
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 9851cafb7f..5341eb3f07 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac
Quoting Ilia Mirkin (2018-03-08 08:59:12)
> On Thu, Mar 8, 2018 at 11:45 AM, Dylan Baker wrote:
> > Quoting Jason Ekstrand (2018-03-07 20:22:51)
> >> Yes, that is what happened. That said, wrote that patch in September and
> >> you've had about 6 months to look at it. The only particularly activ
On Thu, Mar 8, 2018 at 11:57 AM, Mario Kleiner
wrote:
> Cc'ing mesa-dev, which was left out.
>
>
> On 03/05/2018 01:40 PM, Ilia Mirkin wrote:
>>
>> On Mon, Mar 5, 2018 at 2:25 AM, Mario Kleiner
>> wrote:
>>> Afaics EGL does the right thing wrt. channelmask matching of EGLConfigs
>>> to
>>> DRIcon
Quoting Lionel Landwerlin (2018-03-08 15:42:53)
> +static void
> +read_gt_frequency(struct brw_context *brw,
> + struct brw_perf_query_object *obj)
> +{
> + const struct gen_device_info *devinfo = &brw->screen->devinfo;
> + uint32_t *start_reg = obj->oa.map + MI_FREQ_START_OFFS
On Thu, Mar 8, 2018 at 11:45 AM, Dylan Baker wrote:
> Quoting Jason Ekstrand (2018-03-07 20:22:51)
>> Yes, that is what happened. That said, wrote that patch in September and
>> you've had about 6 months to look at it. The only particularly active Mesa
>> contributor who hasn't had access is Ili
Cc'ing mesa-dev, which was left out.
On 03/05/2018 01:40 PM, Ilia Mirkin wrote:
On Mon, Mar 5, 2018 at 2:25 AM, Mario Kleiner
wrote:
On 02/05/2018 12:50 AM, Ilia Mirkin wrote:
In case anyone's curious about 30bpp framebuffer support, here's the
current status:
Kernel:
Ben and I have switch
From: Marek Olšák
v2: pad with PKT2 NOPs on SI
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index d9a95c0..a3feeb9 100644
--- a/src/galli
On Gen10, whenever we do a fast clear, blorp will update the clear color
state buffer for us, as long as we set the clear color address
correctly.
However, on a hiz clear, if the surface is already on the fast clear
state we skip the actual fast clear operation and, before gen10, only
updated the
From: Michel Dänzer
We were dropping the upper 32 bits, which caused assertion failures in
some compute shader piglit tests with radeonsi since the commit below.
Fixes: 752e96970303 ("compiler: Add two new system values for subgroups")
Signed-off-by: Michel Dänzer
---
src/mesa/state_tracker/st
This flag was used while porting parts of the code to use the clear
color address, but other parts were not ported yet. So isl had to be
flexible enough to support both cases.
Now that the code is using exclusively clear color address for
everything Gen10+, we don't need it anymore.
Signed-off-by
In a follow up patch, we make use of clear_color_bo, which is in
mt->mcs_buf or mt->hiz_buf. To avoid duplicating more code that does the
same thing on both aux buffers, just use aux_buf already.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_blorp.c | 19 +++
Add an extra BO to store clear color when we receive the aux buffer from
the window system. Since we have no control over the aux buffer size in
this case, we need the new BO to store only the clear color.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 18 ++
Similarly to vulkan where we store the clear value in the aux surface,
we can do the same in GL.
v2: Remove unneeded extra function.
v3: Use clear_value_state_size instead of clear_value_size.
v4:
- rename to clear_color_state_size
- store clear_color_bo and clear_color_offset in the aux buf str
On Gen10+, instead of copying the clear color from the state buffer to
the surface state, just use the address of the state buffer in the
surface state directly. This way we can avoid the copy from state buffer
to surface state.
v4:
- Remove use_clear_address from anv code. (Jason)
- Use the hel
genxml does not support having two address fields with different names
but same position in the state struct. Both "Clear Color Address"
and "Clear Depth Address Low" mean the same thing, only for different
surface types.
To workaround this genxml limitation, rename "Clear Color Address"
to "Clear
We always want to update the fast clear color during a fast clear on
i965. On anv, we doing that before a resolve, but by adding support to
blorp, we can do a similar thing and update it during a fast clear
instead.
The goal is to remove some code from anv that does such update, and
centralize eve
Store the default clear address for HiZ fast clears on a global bo, and
point to it when needed.
Signed-off-by: Rafael Antognolli
---
src/intel/vulkan/anv_device.c | 19 +++
src/intel/vulkan/anv_image.c | 10 +++---
src/intel/vulkan/anv_private.h | 1 +
3 files changed, 2
The lower bits seem to have extra fields in every platform but gen8
(even though we don't use them in gen9). So just go ahead and avoid
using them for the address.
v4: Use Jason's suggestion for comment explaining the change.
Signed-off-by: Rafael Antognolli
Reviewed-by: Jason Ekstrand
Reviewed
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