On Thu, Mar 8, 2018 at 11:51 AM, Marek Olšák <mar...@gmail.com> wrote:
> From: Marek Olšák <marek.ol...@amd.com>
>
> v2: pad with PKT2 NOPs on SI
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> index d9a95c0..a3feeb9 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> @@ -1521,29 +1521,31 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs
> *rcs,
> /* pad DMA ring to 8 DWs */
> if (ws->info.chip_class <= SI) {
> while (rcs->current.cdw & 7)
> radeon_emit(rcs, 0xf0000000); /* NOP packet */
> } else {
> while (rcs->current.cdw & 7)
> radeon_emit(rcs, 0x00000000); /* NOP packet */
> }
> break;
> case RING_GFX:
> + case RING_COMPUTE:
> /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
> if (ws->info.gfx_ib_pad_with_type2) {
> while (rcs->current.cdw & 7)
> radeon_emit(rcs, 0x80000000); /* type2 nop packet */
> } else {
> while (rcs->current.cdw & 7)
> radeon_emit(rcs, 0xffff1000); /* type3 nop packet */
> }
> - ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4;
> + if (cs->ring_type == RING_GFX)
> + ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4;
> break;
> case RING_UVD:
> case RING_UVD_ENC:
> while (rcs->current.cdw & 15)
> radeon_emit(rcs, 0x80000000); /* type2 nop packet */
> break;
> case RING_VCN_DEC:
> while (rcs->current.cdw & 15)
> radeon_emit(rcs, 0x81ff); /* nop packet */
> break;
> --
> 2.7.4
>
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