On Wed, 2018-02-28 at 15:39 -0800, Kenneth Graunke wrote:
> On Monday, February 26, 2018 11:02:08 PM PST Iago Toral Quiroga
> wrote:
> > In 16631ca30ea6 we fixed gen9 active components to account for
> > padded
> > inputs in the URB, which we can have with SSO programs. To do that,
> > instead of g
Hi;
Some feedback below ..
On 02/28/2018 02:21 PM, Hugues Evrard wrote:
Hi Brian, all,
Thanks for the follow-up, and congrats to the team for the prompt bug
fix! We've just tweeted about it:
https://twitter.com/GraphicsFuzz/status/968815766681333760
We'll be pleased to report further Mesa i
Hi,
On Thursday, 1 March 2018 04:00:15 CET Roland Scheidegger wrote:
> Am 01.03.2018 um 03:28 schrieb Ilia Mirkin:
> > On Wed, Feb 28, 2018 at 8:42 PM, Roland Scheidegger
wrote:
[...]
> > Is this not the correct behavior? Or is it undefined what happens
> > outside of 0..1?
> I can't really see
https://bugs.freedesktop.org/show_bug.cgi?id=105296
--- Comment #2 from Jason Ekstrand ---
I can vouch for him.
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From: Mathias Fröhlich
Hi Brian,
that's what I mentioned yesterday.
You may want to test this change against your use cases of your recent
draw primitive optimization.
With one openscenegraph dlist based workload this change improves the
framerates on radeonsi by about 10% compared to without th
This gives the scheduler visibility into the headers which should
improve scheduling. More importantly, however, it lets the scheduler
know that the header gets written. As-is, the scheduler thinks that a
texture instruction only reads it's payload and is unaware that it may
write to the first re
Currently both users of this would overflow an array when the
input was a dual slot double as they expected the number of
components to be a max of 4.
Since we pass the type we can just let the functions handle
doubles in a way they choose.
---
src/amd/common/ac_nir_to_llvm.c | 4 ++--
1 file cha
Fixes piglit test:
tests/spec/arb_gpu_shader_fp64/execution/explicit-location-gs-fs-vs.shader_test
---
src/gallium/drivers/radeonsi/si_shader.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_sh
All the tess shader and tgsi equivalents are here and it allows
use to use llvm_type_is_64bit() in the following patch without
exposing it externally.
---
src/gallium/drivers/radeonsi/si_shader.c | 20
src/gallium/drivers/radeonsi/si_shader_internal.h | 9 -
From: Dave Airlie
This fixes some hangs seen where the recip_ieee opcodes would
end up split across the wrong slots.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
Am 01.03.2018 um 03:28 schrieb Ilia Mirkin:
> On Wed, Feb 28, 2018 at 8:42 PM, Roland Scheidegger
> wrote:
>> I suppose that's ok (and safer), albeit I'm not sure why it wouldn't
>> work with nv50.
>> Depth clip is enabled, yes, but I can't see why the produced values
>> wouldn't be inside the vi
We only need to check for previously processed location on user
defined varyings as they are the only ones that support component
packing. Therefore a single instance of processed_locs can be
shared by regular varyings and patches.
For simplicity we make processed_locs an array in order to handle
On Wed, Feb 28, 2018 at 8:42 PM, Roland Scheidegger wrote:
> I suppose that's ok (and safer), albeit I'm not sure why it wouldn't
> work with nv50.
> Depth clip is enabled, yes, but I can't see why the produced values
> wouldn't be inside the view volume (which is defined by the near/far
> values
On Wed, Feb 28, 2018 at 7:20 PM, Eric Anholt wrote:
> Rob Clark writes:
>
>> On Wed, Feb 28, 2018 at 4:09 PM, Eric Anholt wrote:
>>> Matt Turner writes:
>>>
I find this script *really* annoying. Getting Cc'd on a random sample of
a series is doing it wrong. Cc lists of 14 people is do
I suppose that's ok (and safer), albeit I'm not sure why it wouldn't
work with nv50.
Depth clip is enabled, yes, but I can't see why the produced values
wouldn't be inside the view volume (which is defined by the near/far
values for z).
Granted values outside [0,1] are not permitted by standard GL,
On Wednesday, February 28, 2018 2:21:24 PM PST Emil Velikov wrote:
> On 27 February 2018 at 00:05, Kenneth Graunke wrote:
>
> > --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > @@ -203,12 +203,23 @@ brw_emit_surface_state(struct
On Thursday, February 15, 2018 1:12:54 AM PST Tapani Pälli wrote:
> From: Simon Hausmann
>
> When looking up known glsl_type instances in the various hash tables, we
> end up leaking the key instances used for the lookup, as the glsl_type
> constructor allocates memory on the global mem_ctx. This
From: Dave Airlie
fs outputs don't start above VARYING_SLOT_VAR0, but I assume
that is there for a reason, so make an exception for fragment
outputs.
This fixes with NIR:
tests/spec/arb_enhanced_layouts/execution/component-layout/fs-output.shader_test
Signed-off-by: Dave Airlie
---
src/mesa/s
These were getting mapped off into outer space, which would cause nv50
and nvc0 to clip the primitives (as depth_clip was enabled).
Oddly enough, it worked with nv30 and llvmpipe though. Perhaps their
frustrum clipping rules are a bit different?
Signed-off-by: Ilia Mirkin
---
src/gallium/tests/
On Wed, Feb 28, 2018 at 1:09 PM, Eric Anholt wrote:
> Matt Turner writes:
>
>> I find this script *really* annoying. Getting Cc'd on a random sample of
>> a series is doing it wrong. Cc lists of 14 people is doing it wrong.
>>
>> Let's start the negotiation with "delete this script" and see if an
Rob Clark writes:
> On Wed, Feb 28, 2018 at 4:09 PM, Eric Anholt wrote:
>> Matt Turner writes:
>>
>>> I find this script *really* annoying. Getting Cc'd on a random sample of
>>> a series is doing it wrong. Cc lists of 14 people is doing it wrong.
>>>
>>> Let's start the negotiation with "delet
Reviewed-by: Timothy Arceri
On 01/03/18 11:02, Dave Airlie wrote:
From: Dave Airlie
This stops a crash when running (still fails):
tests/spec/arb_gpu_shader_fp64/execution/explicit-location-gs-fs-vs.shader_test
Signed-off-by: Dave Airlie
---
src/gallium/drivers/radeonsi/si_shader_nir.c |
On Wednesday, February 28, 2018 3:29:00 PM PST Jason Ekstrand wrote:
> We don't zalloc the physical device so we need to unconditionally set
> everything. Crucible helpfully initializes all allocations to 139 so it
> was getting true regardless of whether or not the kernel actually
> supports cont
Quoting Emil Velikov (2018-02-28 15:49:37)
> On 28 February 2018 at 21:15, Andres Gomez wrote:
> > 3 digits versions in LLVM only started from 3.4.1 on. Hence, if you
> > have installed 3.4 or below, meson will fail even when we may not make
> > use of LLVM.
> >
> > v2: Properly compare LLVM versi
From: Dave Airlie
This stops a crash when running (still fails):
tests/spec/arb_gpu_shader_fp64/execution/explicit-location-gs-fs-vs.shader_test
Signed-off-by: Dave Airlie
---
src/gallium/drivers/radeonsi/si_shader_nir.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/g
On 28 February 2018 at 21:18, Andres Gomez wrote:
> Travis CI has moved to LLVM 5.0, and meson is detecting automatically
> the available version in /usr/local/bin based on the PATH env variable
> order preference.
>
> As for 0.44.x, Meson cannot receive the path to the llvm-config binary
> as a c
On 28 February 2018 at 21:15, Andres Gomez wrote:
> 3 digits versions in LLVM only started from 3.4.1 on. Hence, if you
> have installed 3.4 or below, meson will fail even when we may not make
> use of LLVM.
>
> v2: Properly compare LLVM version and set patch version to 0
> if < 3.4.1 (Eric).
On 01/03/18 10:39, Dave Airlie wrote:
From: Dave Airlie
The nir->llvm conversion was using the wrong srcs.
Well that's embarrassing.
Reviewed-by: Timothy Arceri
Fixes:
tests/spec/arb_compute_shader/execution/shared-atomics.shader_test
Signed-off-by: Dave Airlie
---
src/amd/common/ac_
Reviewed-by: Bas Nieuwenhuizen
On Thu, Mar 1, 2018 at 12:39 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> The nir->llvm conversion was using the wrong srcs.
>
> Fixes:
> tests/spec/arb_compute_shader/execution/shared-atomics.shader_test
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/common/a
On Monday, February 26, 2018 11:02:08 PM PST Iago Toral Quiroga wrote:
> In 16631ca30ea6 we fixed gen9 active components to account for padded
> inputs in the URB, which we can have with SSO programs. To do that,
> instead of going through the bitfield of inputs (which doesn't include
> padding inf
From: Dave Airlie
The nir->llvm conversion was using the wrong srcs.
Fixes:
tests/spec/arb_compute_shader/execution/shared-atomics.shader_test
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/amd/
On Monday, February 26, 2018 11:02:08 PM PST Iago Toral Quiroga wrote:
> In 16631ca30ea6 we fixed gen9 active components to account for padded
> inputs in the URB, which we can have with SSO programs. To do that,
> instead of going through the bitfield of inputs (which doesn't include
> padding inf
Reviewed-by: Bas Nieuwenhuizen
On Thu, Mar 1, 2018 at 12:33 AM, Timothy Arceri wrote:
> Thanks!
>
> Reviewed-by: Timothy Arceri
>
> On 01/03/18 10:26, Dave Airlie wrote:
>>
>> From: Dave Airlie
>>
>> This matches the tgsi code.
>>
>> Fixes arb_texture_multisample texelFetch piglit tests.
>>
>>
Thanks!
Reviewed-by: Timothy Arceri
On 01/03/18 10:26, Dave Airlie wrote:
From: Dave Airlie
This matches the tgsi code.
Fixes arb_texture_multisample texelFetch piglit tests.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deleti
We don't zalloc the physical device so we need to unconditionally set
everything. Crucible helpfully initializes all allocations to 139 so it
was getting true regardless of whether or not the kernel actually
supports context priorities.
Fixes: 6d8ab53303331 "anv: implement VK_EXT_global_priority
From: Dave Airlie
This matches the tgsi code.
Fixes arb_texture_multisample texelFetch piglit tests.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_ll
Reviewed-by: Timothy Arceri
On 01/03/18 04:13, Alejandro Piñeiro wrote:
var->name could be true under ARB_gl_spirv for example. And in any
case, the code is already handing var name being NULL when reading a
variable, so it is consistent to do it writing a variable too.
---
src/compiler/nir/n
These days, we're just passing a pointer to a prog_data field, which
we already have access to. We can just use it directly.
(In the past, it was a pointer to a separate value.)
---
src/intel/compiler/brw_fs.cpp | 4 ++--
src/intel/compiler/brw_fs.h| 2 +-
src/intel/
https://bugs.freedesktop.org/show_bug.cgi?id=105291
mirh changed:
What|Removed |Added
CC||m...@protonmail.ch
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You are receiving this ma
Looks fine to me,
Reviewed-By: Gert Wollny
Am Mittwoch, den 28.02.2018, 23:18 +0200 schrieb Andres Gomez:
> Travis CI has moved to LLVM 5.0, and meson is detecting automatically
> the available version in /usr/local/bin based on the PATH env
> variable
> order preference.
>
> As for 0.44.x, Me
On 27 February 2018 at 00:05, Kenneth Graunke wrote:
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -203,12 +203,23 @@ brw_emit_surface_state(struct brw_context *brw,
> * FIXME: move to the point of assignment.
>
hmm, I haven't tried passing a struct (rather than a pointer to a
struct) as a parameter, but if there were 8/16 bit fields in the
struct it would calculate the size incorrectly.
(otoh the more important question is whether this agrees with how
clover lays out the input buffer, as far as where the
On 02/28/2018 10:39 PM, Emil Velikov wrote:
Hi Samuel,
On 20 February 2018 at 11:33, Samuel Pitoiset wrote:
Ported from RadeonSI.
Signed-off-by: Samuel Pitoiset
Cc:
---
src/amd/vulkan/radv_image.c | 35 ---
1 file changed, 32 insertions(+), 3 deletions(-
Quoting Andres Gomez (2018-02-28 13:15:07)
> 3 digits versions in LLVM only started from 3.4.1 on. Hence, if you
> have installed 3.4 or below, meson will fail even when we may not make
> use of LLVM.
>
> v2: Properly compare LLVM version and set patch version to 0
> if < 3.4.1 (Eric).
>
> Cc
On Wed, Feb 28, 2018 at 1:41 PM, Emil Velikov
wrote:
> Hi Jason,
>
> On 24 January 2018 at 23:46, Jason Ekstrand wrote:
> > This function is used to determine when we need to re-allocate a
> > miptree. Since we do nothing different in miptree allocation for
> > sRGB vs. linear, loosening this s
I thought OpenCL used a different set of alignment rules for structs,
unions, etc. In particular, I thought it was very close to standard C. If
that's true, then std430 is not what you want.
On Wed, Feb 28, 2018 at 1:44 PM, Karol Herbst wrote:
> it isn't yet. But you would use it in your drive
On 2018-02-28 12:53:01, Francisco Jerez wrote:
> Jordan Justen writes:
>
> > On 2018-02-28 01:58:24, Samuel Iglesias Gonsálvez wrote:
> >> What is the idea for src/intel/dev/ ?
> >>
> >> I'm not against this patch, just asking.
> >
> > Ken noticed a lot of duplicate lines in the xml for surface
I needed it in ir3, since nir->ir3 is .c code, and I need it to map
load_param offset to offset in constant registers. Sorry, I didn't
think the ir3 patches were interesting to others so I didn't include
them in the patchset.
Tbh if we used uniforms to pass params, I might not need these in ir3
(
it isn't yet. But you would use it in your driver when calculating
your memory offsets for kernel arguments. In OpenCL things are aligned
in memory by the size of the type and we would use those functions to
calculate those.
On Wed, Feb 28, 2018 at 10:39 PM, Jason Ekstrand wrote:
> Looking throug
On 22 February 2018 at 19:23, Emil Velikov wrote:
> Hi Anuj,
>
> On 7 February 2018 at 01:09, Anuj Phogat wrote:
>> Commit bit in the message descriptor (Bit 13) must be always set
>> to true in CNL+ for memory fence messages. It also fixes a piglit
>> GPU hang on cnl+ in simulation environment.
Hi Jason,
On 24 January 2018 at 23:46, Jason Ekstrand wrote:
> This function is used to determine when we need to re-allocate a
> miptree. Since we do nothing different in miptree allocation for
> sRGB vs. linear, loosening this should be safe and may lead to less
> copying and reallocating in s
Hi Samuel,
On 20 February 2018 at 11:33, Samuel Pitoiset wrote:
> Ported from RadeonSI.
>
> Signed-off-by: Samuel Pitoiset
> Cc:
> ---
> src/amd/vulkan/radv_image.c | 35 ---
> 1 file changed, 32 insertions(+), 3 deletions(-)
>
JFYI, seems like this patch hasn't
Looking through commit titles, I don't see any obvious place where this
would get used.
On Wed, Feb 28, 2018 at 11:51 AM, Rob Clark wrote:
> Signed-off-by: Rob Clark
> ---
> src/compiler/nir_types.cpp | 12
> src/compiler/nir_types.h | 4
> 2 files changed, 16 insertions(+
On Wed, Feb 28, 2018 at 1:35 PM, Rob Clark wrote:
> On Wed, Feb 28, 2018 at 4:18 PM, Karol Herbst wrote:
> > On Wed, Feb 28, 2018 at 9:46 PM, Jason Ekstrand
> wrote:
> >> I do not think this patch does what you think it does. The old opcode
> >> allowed you to shift any bit size integer by a 3
On 28 February 2018 at 19:16, George Kyriazis wrote:
> Populate pLastIndex, even for the non-indexed case. An zero pLastIndex
> can cause the index offsets inside the fetcher to have non-sensical values
> that can be either very large positive or very large negative numbers.
>
> Cherry-pick of 53
On Wed, Feb 28, 2018 at 1:18 PM, Karol Herbst wrote:
> On Wed, Feb 28, 2018 at 9:46 PM, Jason Ekstrand
> wrote:
> > I do not think this patch does what you think it does. The old opcode
> > allowed you to shift any bit size integer by a 32-bit integer. The new
> > version allows you to shift N
On Wed, Feb 28, 2018 at 4:18 PM, Karol Herbst wrote:
> On Wed, Feb 28, 2018 at 9:46 PM, Jason Ekstrand wrote:
>> I do not think this patch does what you think it does. The old opcode
>> allowed you to shift any bit size integer by a 32-bit integer. The new
>> version allows you to shift N bits
On Wed, Feb 28, 2018 at 11:51 AM, Rob Clark wrote:
> From: Karol Herbst
>
> OpenCL kernels also have int8/uint8.
>
> Signed-off-by: Rob Clark
> ---
> src/compiler/builtin_type_macros.h | 10
> src/compiler/glsl/ast_to_hir.cpp| 2 ++
> src/compiler/glsl/ir
On Wed, Feb 28, 2018 at 4:16 PM, Eric Anholt wrote:
> Rob Clark writes:
>
>> From: Karol Herbst
>>
>> OpenCL kernels have parameters (see pipe_grid_info::input), and so we
>> need a way to access them.
>>
>> Signed-off-by: Rob Clark
>>
>> ---
>> src/compiler/nir/nir_intrinsics.h | 2 ++
>> sr
Travis CI has moved to LLVM 5.0, and meson is detecting automatically
the available version in /usr/local/bin based on the PATH env variable
order preference.
As for 0.44.x, Meson cannot receive the path to the llvm-config binary
as a configuration parameter. See
https://github.com/mesonbuild/meso
---
src/compiler/nir/nir_search.c | 20
1 file changed, 20 insertions(+)
diff --git a/src/compiler/nir/nir_search.c b/src/compiler/nir/nir_search.c
index dec56fe..c7c52ae 100644
--- a/src/compiler/nir/nir_search.c
+++ b/src/compiler/nir/nir_search.c
@@ -27,6 +27,7 @@
#incl
On Wed, Feb 28, 2018 at 9:46 PM, Jason Ekstrand wrote:
> I do not think this patch does what you think it does. The old opcode
> allowed you to shift any bit size integer by a 32-bit integer. The new
> version allows you to shift N bits by N bits. In particular, you can't
> shift a 16-bit by a
On Wed, Feb 28, 2018 at 4:09 PM, Eric Anholt wrote:
> Matt Turner writes:
>
>> I find this script *really* annoying. Getting Cc'd on a random sample of
>> a series is doing it wrong. Cc lists of 14 people is doing it wrong.
>>
>> Let's start the negotiation with "delete this script" and see if an
Signed-off-by: Dylan Baker
---
meson.build | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 7cfd7f2183a..c565a81fe95 100644
--- a/meson.build
+++ b/meson.build
@@ -1188,7 +1188,8 @@ if with_platform_x11
endif
dep_glproto = dependency(
It should be possible to build EGL without GLX, but the meson build
currently doesn't allow that because it too tightly couples glx and dri.
This patch eases dri and glx apart, so that EGL without GLX can be
built.
CC: Daniel Stone
Signed-off-by: Dylan Baker
---
meson.build | 25 +++
Rob Clark writes:
> From: Karol Herbst
>
> OpenCL kernels have parameters (see pipe_grid_info::input), and so we
> need a way to access them.
>
> Signed-off-by: Rob Clark
>
> ---
> src/compiler/nir/nir_intrinsics.h | 2 ++
> src/compiler/nir/nir_lower_io.c | 13 ++---
> 2 files chan
3 digits versions in LLVM only started from 3.4.1 on. Hence, if you
have installed 3.4 or below, meson will fail even when we may not make
use of LLVM.
v2: Properly compare LLVM version and set patch version to 0
if < 3.4.1 (Eric).
Cc: Dylan Baker
Cc: Eric Engestrom
Signed-off-by: Andres Go
Quoting Dylan Baker (2018-02-28 13:02:02)
> Quoting Rob Clark (2018-02-28 12:54:28)
> > On Wed, Feb 28, 2018 at 3:25 PM, Matt Turner wrote:
> > > I find this script *really* annoying. Getting Cc'd on a random sample of
> > > a series is doing it wrong. Cc lists of 14 people is doing it wrong.
> >
Matt Turner writes:
> I find this script *really* annoying. Getting Cc'd on a random sample of
> a series is doing it wrong. Cc lists of 14 people is doing it wrong.
>
> Let's start the negotiation with "delete this script" and see if anyone
> can come up with a way of making this not so stupid.
Jordan Justen writes:
> On 2018-02-28 01:58:24, Samuel Iglesias Gonsálvez wrote:
>> What is the idea for src/intel/dev/ ?
>>
>> I'm not against this patch, just asking.
>
> Ken noticed a lot of duplicate lines in the xml for surface formats.
> (Patch 4). But, then we noticed that removing them m
Quoting Rob Clark (2018-02-28 12:54:28)
> On Wed, Feb 28, 2018 at 3:25 PM, Matt Turner wrote:
> > I find this script *really* annoying. Getting Cc'd on a random sample of
> > a series is doing it wrong. Cc lists of 14 people is doing it wrong.
> >
> > Let's start the negotiation with "delete this
Reviewed-by: Bruce Cherniak
> On Feb 28, 2018, at 1:16 PM, George Kyriazis
> wrote:
>
> Populate pLastIndex, even for the non-indexed case. An zero pLastIndex
> can cause the index offsets inside the fetcher to have non-sensical values
> that can be either very large positive or very large n
On Wed, Feb 28, 2018 at 3:25 PM, Matt Turner wrote:
> I find this script *really* annoying. Getting Cc'd on a random sample of
> a series is doing it wrong. Cc lists of 14 people is doing it wrong.
>
> Let's start the negotiation with "delete this script" and see if anyone
> can come up with a way
Rb
On Wed, Feb 28, 2018 at 12:18 PM, Ian Romanick wrote:
> From: Ian Romanick
>
> This transformation is inexact because section 4.7.1 (Range and
> Precision) says:
>
> Operations and built-in functions that operate on a NaN are not
> required to return a NaN as the result.
>
> The fmin
I do not think this patch does what you think it does. The old opcode
allowed you to shift any bit size integer by a 32-bit integer. The new
version allows you to shift N bits by N bits. In particular, you can't
shift a 16-bit by a 32-bit value.
I'm not sure what the best thing is to do here.
On Wed, Feb 28, 2018 at 9:41 PM, Samuel Pitoiset
wrote:
>
>
> On 02/28/2018 09:06 PM, Bas Nieuwenhuizen wrote:
>>
>> On Wed, Feb 28, 2018 at 8:31 PM, Samuel Pitoiset
>> wrote:
>>>
>>> This is an optimization which reduces the number of flushes for
>>> small pool buffers.
>>>
>>> Signed-off-by: Sa
If the query pool has been previously resetted using the compute
shader path.
v3: set pending_reset_query only for the compute shader path
v2: handle multiple commands buffers with same pool
Fixes: a41e2e9cf5 ("radv: allow to use a compute shader for resetting the query
pool")
Bugzilla: https://
On 02/28/2018 09:06 PM, Bas Nieuwenhuizen wrote:
On Wed, Feb 28, 2018 at 8:31 PM, Samuel Pitoiset
wrote:
This is an optimization which reduces the number of flushes for
small pool buffers.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_buffer.c | 6 --
src/amd/vulkan/ra
On Wed, 2018-02-28 at 18:53 +0100, Gert Wollny wrote:
> Am Mittwoch, den 28.02.2018, 17:52 +0200 schrieb Andres Gomez:
[...]
> >
+ test -f /usr/bin/llvm-config && ln -s /usr/bin/llvm-config
> > $HOME/prefix/bin
>
> I'm not sure how the toolchain packages on travis are created and maybe
> w
On Wed, 2018-02-28 at 17:12 +, Eric Engestrom wrote:
> On Wednesday, 2018-02-28 17:08:41 +, Eric Engestrom wrote:
> > On Wednesday, 2018-02-28 17:02:50 +, Eric Engestrom wrote:
> > > On Wednesday, 2018-02-28 17:52:05 +0200, Andres Gomez wrote:
> > > > 3 digits versions in LLVM only star
I find this script *really* annoying. Getting Cc'd on a random sample of
a series is doing it wrong. Cc lists of 14 people is doing it wrong.
Let's start the negotiation with "delete this script" and see if anyone
can come up with a way of making this not so stupid.
---
scripts/get_reviewer.pl |
From: Ian Romanick
v2: Fix several problems handling inverted predicates. Add a much
bigger comment around the BRW_CONDITIONAL_NZ case.
v3: Allow uniforms and shader inputs as sources for the original SEL and
CMP instructions. This enables a LOT more shaders to receive CSEL
merging (5816 vs 85
From: Ian Romanick
These transformations are inexact because section 4.7.1 (Range and
Precision) says:
Operations and built-in functions that operate on a NaN are not
required to return a NaN as the result.
The fmin or fmax might not return NaN in cases where the original
expression wou
From: Ian Romanick
This transformation is inexact because section 4.7.1 (Range and
Precision) says:
Operations and built-in functions that operate on a NaN are not
required to return a NaN as the result.
The fmin or fmax might not return NaN in cases where the original
expression would
On Wed, Feb 28, 2018 at 8:31 PM, Samuel Pitoiset
wrote:
> This is an optimization which reduces the number of flushes for
> small pool buffers.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_meta_buffer.c | 6 --
> src/amd/vulkan/radv_private.h | 6 ++
> src/amd/vul
An attempt to add physical pointer support to vtn. I'm not totally
happy about the handling of logical pointers vs physical pointers.
So this is really more of an RFS (request for suggestions)
---
src/compiler/spirv/spirv_to_nir.c | 47 +++--
src/compiler/spirv/vtn_private.h | 19 +++-
s
From: Karol Herbst
OpenCL kernels also have int8/uint8.
Signed-off-by: Rob Clark
---
src/compiler/builtin_type_macros.h | 10
src/compiler/glsl/ast_to_hir.cpp| 2 ++
src/compiler/glsl/ir_clone.cpp | 2 ++
src/compiler/glsl/link_uniform_i
From: Karol Herbst
Signed-off-by: Rob Clark
---
src/compiler/nir/nir_lower_system_values.c | 8
src/compiler/shader_enums.c| 1 +
src/compiler/shader_enums.h| 2 ++
src/compiler/spirv/vtn_variables.c | 4
4 files changed, 15 insertions(+)
d
These are just hints so we can ignore them.
Signed-off-by: Rob Clark
---
src/compiler/spirv/spirv_to_nir.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index e539d944302..3e7ac46c639 100644
--- a/src/compiler/spirv
Signed-off-by: Rob Clark
---
src/compiler/spirv/spirv_to_nir.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 3e7ac46c639..b9e5198e7bc 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/co
From: Karol Herbst
OpenCL kernels have raw pointers to global memory, so we need
instructions to load/store in order to dereference these pointers.
In some ways similar to other load/store intrinsics, but rather
than taking an offset as a src argument, they take a raw pointer
value (which can be
Signed-off-by: Rob Clark
---
src/compiler/spirv/vtn_alu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index d0c9e316935..9397240912b 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -592,6 +592,7 @@
I think a new intrinsic is the easiest way to do this. We can lower
this to a sequence of load/stores after vtn.
Signed-off-by: Rob Clark
---
src/compiler/nir/nir_intrinsics.h | 2 ++
src/compiler/spirv/vtn_variables.c | 17 -
2 files changed, 18 insertions(+), 1 deletion(-)
Unlike glsl/vk compute shaders, this isn't a builtin constant.
Signed-off-by: Rob Clark
---
src/compiler/spirv/spirv_to_nir.c | 3 +++
src/compiler/spirv/vtn_private.h | 2 ++
src/compiler/spirv/vtn_variables.c | 6 +++---
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/src/com
From: Karol Herbst
This is a thing for OpenCL kernels.
Signed-off-by: Rob Clark
---
src/compiler/nir/nir_opcodes.py | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py
index 278562b2bd1..c4d2c7805eb 100644
Signed-off-by: Rob Clark
---
src/compiler/nir_types.cpp | 12
src/compiler/nir_types.h | 4
2 files changed, 16 insertions(+)
diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp
index cbdd452dc81..0085a19248a 100644
--- a/src/compiler/nir_types.cpp
+++ b/src
From: Karol Herbst
OpenCL kernels have parameters (see pipe_grid_info::input), and so we
need a way to access them.
Signed-off-by: Rob Clark
---
src/compiler/nir/nir_intrinsics.h | 2 ++
src/compiler/nir/nir_lower_io.c | 13 ++---
2 files changed, 12 insertions(+), 3 deletions(-)
d
This assert is not valid for OpenCL kernels.
TODO can we somehow conditionally assert based on glsl vs cl??
Signed-off-by: Rob Clark
---
src/compiler/nir/nir.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 2acd9511f57..29181694a35 10064
This is by no means everything needed for clover/OpenCL.. but I took
a bit of time this morning to extract some parts of our growing stack
of patches which where plausibly mergable (or at least not complete
hacks), with the idea that review could start in parallel with further
clover/compute hackin
This is an optimization which reduces the number of flushes for
small pool buffers.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_buffer.c | 6 --
src/amd/vulkan/radv_private.h | 6 ++
src/amd/vulkan/radv_query.c | 12
3 files changed, 14 insertions
1 - 100 of 195 matches
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