Re: [Mesa-dev] [PATCH 2/6] r600g: Add r600_rat_buffer_create()

Hi Tom, First I'd like to say that even though I don't agree with the direction you're taking, I'd be okay with it for initial bring-up of the compute support. I am not in favor of using radeon_surface for plain untyped 1D buffers, where the only thing that really matters is the buffer alignment,

[Mesa-dev] [PATCH 09/22] gallium/u_blitter: add helper for blitting via resource_copy_region

v2: fix off-by-one error in is_box_inside_resource, add comments --- src/gallium/auxiliary/util/u_blitter.c | 140 src/gallium/auxiliary/util/u_blitter.h | 12 +++ 2 files changed, 152 insertions(+) diff --git a/src/gallium/auxiliary/util/u_blitter.c b/src/gal

Re: [Mesa-dev] [PATCH 1/2] i965/blorp: Increase Y alignment for multisampled stencil blits.

On 09/12/2012 08:51 PM, Paul Berry wrote: > This patch is a band-aid fix for a bug in commit 5fd67fa (i965/blorp: > Reduce alignment restrictions for stencil blits), which causes > multisampled stencil blits to work incorrectly on Sandy Bridge. > > When blitting to or from a normal stencil buffer,

[Mesa-dev] [PATCH 2/2] i965: Do texture swizzling in hardware on Haswell.

Haswell supports EXT_texture_swizzle and legacy DEPTH_TEXTURE_MODE swizzling by setting SURFACE_STATE entries. This means we don't have to bake the swizzle settings into the shader code by emitting MOV instructions, and thus don't have to recompile shaders whenever the swizzles change. Unfortunat

[Mesa-dev] [PATCH 1/2] i965: Refactor texture swizzle generation into a helper.

It's going to be reused in a second place soon. Cc: Paul Berry Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_state.h| 2 + src/mesa/drivers/dri/i965/brw_wm.c | 51 + src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 56 +

[Mesa-dev] [PATCH] intel/i965: Disable SampleAlphaToOne if dual source blending enabled

>From SandyBridge PRM, volume 2 Part 1, section 12.2.3, BLEND_STATE: DWord 1, Bit 30 (AlphaToOne Enable): "If Dual Source Blending is enabled, this bit must be disabled" Signed-off-by: Anuj Phogat --- src/mesa/drivers/dri/i965/gen6_cc.c | 13 +++-- 1 files changed, 11 insertions(+), 2

Re: [Mesa-dev] [PATCH 5/8] i965: Use visibility cflags on the driver code.

On Fri, Sep 21, 2012 at 3:11 AM, Eric Anholt wrote: > The only symbols that need to be public (those in intel_screen.c that the > loader looks for) are already marked public. Saves 100k of compiled driver > size. > --- > src/mesa/drivers/dri/i965/Makefile.am |1 + > 1 file changed, 1 inserti

[Mesa-dev] [PATCH 5/5] clover: Query device for CL_DEVICE_MAX_MEM_ALLOC_SIZE

From: Tom Stellard --- src/gallium/state_trackers/clover/api/device.cpp | 5 - src/gallium/state_trackers/clover/core/device.cpp | 6 ++ src/gallium/state_trackers/clover/core/device.hpp | 1 + 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/gallium/state_trackers/clo

[Mesa-dev] [PATCH 4/5] gallium: Add PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE

From: Tom Stellard --- src/gallium/drivers/r600/r600_pipe.c | 10 ++ src/gallium/include/pipe/p_defines.h | 3 ++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index 658e9a9..55db78c 100644 --

[Mesa-dev] [PATCH 2/5] r600g: Handle multiple kernels in the same program v2

From: Tom Stellard v2: - Use pc parameter of launch_grid --- src/gallium/drivers/r600/evergreen_compute.c | 42 ++ .../drivers/r600/evergreen_compute_internal.h | 18 ++ src/gallium/drivers/r600/llvm_wrapper.cpp | 38 src/gal

[Mesa-dev] [PATCH 3/5] clover: Handle NULL value for clEnqueueNDRangeKernel local_work_size

From: Tom Stellard --- src/gallium/state_trackers/clover/api/kernel.cpp | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/src/gallium/state_trackers/clover/api/kernel.cpp b/src/gallium/state_trackers/clover/api/kernel.cpp index ab4982d..6ef2b05 100644 --- a/src/g

[Mesa-dev] [PATCH 1/5] clover: Handle multiple kernels in the same program v2

From: Blaž Tomažič v2: Tom Stellard - Use pc parameter of launch_grid() --- src/gallium/include/pipe/p_context.h | 4 ++ .../state_trackers/clover/llvm/invocation.cpp | 66 +++--- 2 files changed, 37 insertions(+), 33 deletions(-) diff --git a/src/gallium/i

[Mesa-dev] [PATCH 6/6] r600g: Re-enable growing of the compute memory pool

From: Tom Stellard --- src/gallium/drivers/r600/compute_memory_pool.c | 15 +-- src/gallium/drivers/r600/r600_pipe.c | 7 +++ 2 files changed, 4 insertions(+), 18 deletions(-) diff --git a/src/gallium/drivers/r600/compute_memory_pool.c b/src/gallium/drivers/r600/comp

[Mesa-dev] [PATCH 5/6] r600g: Fix bug when adding new items to the compute memory pool

From: Tom Stellard The items are ordered in the item list by their offsets, with the lowest offset coming first in the list. The old code was assuming that new items being added to the list would always have a greater offset than the first item in the list, however this is not always the case. -

[Mesa-dev] [PATCH 4/6] r600g: Use a RAT buffer as the backing bo for the compute memory pool

From: Tom Stellard --- src/gallium/drivers/r600/compute_memory_pool.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/r600/compute_memory_pool.c b/src/gallium/drivers/r600/compute_memory_pool.c index 5e25a1d..9404f0a 100644 --- a/src/gallium/driver

[Mesa-dev] [PATCH 3/6] r600g: Make sure to init the compute memory pool with enough memory

From: Tom Stellard --- src/gallium/drivers/r600/compute_memory_pool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/r600/compute_memory_pool.c b/src/gallium/drivers/r600/compute_memory_pool.c index bd3c14d..5e25a1d 100644 --- a/src/gallium/drivers/r600/

[Mesa-dev] [PATCH 2/6] r600g: Add r600_rat_buffer_create()

From: Tom Stellard This function creates a buffer with an associated radeon_surface that can be used as a RAT. --- src/gallium/drivers/r600/r600_buffer.c | 69 src/gallium/drivers/r600/r600_pipe.h | 2 + src/gallium/drivers/r600/r600_resource.h | 5 +++ s

[Mesa-dev] [PATCH 1/6] r600g: Handle PIPE_BUFFER target in r600_init_surface()

From: Tom Stellard --- This change needs the drm patch I sent to the list in order to work: radeon: Allow N x 1 x 1 surfaces for evergreen+ src/gallium/drivers/r600/r600_texture.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/r600/r600_texture.c b/sr

[Mesa-dev] r600g compute buffer improvements

Hi, These series improves how the r600g compute code uses buffers for global memory. I'm interested in getting some feedback on these, especially patches 1 and 2. Thanks, Tom ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freede

Re: [Mesa-dev] automake-gallium testing

On Mon, Sep 17, 2012 at 8:22 AM, Andreas Boll wrote: > Yep, vdpau is also affected. > > $ LD_LIBRARY_PATH="/home/andreas/mesa-testing/lib/vdpau" > VDPAU_DRIVER=r600' vdpauinfo > display: :0 screen: 0 > Failed to open VDPAU backend > /home/andreas/mesa-testing/lib/vdpau/libvdpau_r600.so: undefine

Re: [Mesa-dev] [PATCH 00/23] Gallium blit rework

On 09/14/2012 11:09 AM, Marek Olšák wrote: This series reworks blitting and MSAA resolving in Gallium as discussed here: http://www.mail-archive.com/mesa-dev@lists.freedesktop.org/msg26592.html I'd like to clarify some more rules for the blit function: - Z/S blitting must always be supported reg

Re: [Mesa-dev] [PATCH 03/23] gallium: add PIPE_CAP_TEXTURE_MULTISAMPLE

On 09/14/2012 11:09 AM, Marek Olšák wrote: --- src/gallium/drivers/i915/i915_screen.c |1 + src/gallium/drivers/llvmpipe/lp_screen.c |1 + src/gallium/drivers/nv30/nv30_screen.c |1 + src/gallium/drivers/nv50/nv50_screen.c |1 + src/gallium/drivers/nvc0/nvc0_screen.c

Re: [Mesa-dev] [PATCH 09/23] gallium/u_blitter: add helper for blitting via resource_copy_region

On 09/14/2012 11:09 AM, Marek Olšák wrote: --- src/gallium/auxiliary/util/u_blitter.c | 136 src/gallium/auxiliary/util/u_blitter.h |4 + 2 files changed, 140 insertions(+) diff --git a/src/gallium/auxiliary/util/u_blitter.c b/src/gallium/auxiliary/util

Re: [Mesa-dev] [PATCH] meta: Add on demand compilation of per target shader programs

On 09/20/2012 04:19 PM, Anuj Phogat wrote: A call to glGenerateMipmap() follows the generation of a relevant shader program in setup_glsl_generate_mipmap(). To support all texture targets and to avoid compiling shaders everytime, per target shader programs are compiled on demand and saved for th

Re: [Mesa-dev] [PATCH] egl-util: Adds probe_front_pixel_rgb function

On 09/20/2012 09:59 AM, Robert Bragg wrote: This adds an egl_probe_front_pixel_rgb function that is analogous to piglit_probe_pixel_rgba except it probes the front buffer instead of probing the back buffer. --- tests/egl/egl-util.c | 31 +++ tests/egl/egl-util.h |

Re: [Mesa-dev] [PATCH] radeon/llvm: support for interpolation intrinsics

On Tue, Sep 18, 2012 at 10:57:22PM +0200, Vincent Lejeune wrote: Reviewed-by: Tom Stellard This patch is OK to commit if there are no regressions with the LLVM compiler. > --- > src/gallium/drivers/radeon/AMDGPUISelLowering.cpp | 2 + > src/gallium/drivers/radeon/AMDGPUISelLowering.h|

[Mesa-dev] [PATCH] st/mesa: check for zero-size image in st_TestProxyTexImage()

Fixes divide by zero issue in llvmpipe driver. --- src/mesa/state_tracker/st_cb_texture.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/mesa/state_tracker/st_cb_texture.c b/src/mesa/state_tracker/st_cb_texture.c index 4f4fe77..5634a3e 100644 --- a/src/mesa/state

Re: [Mesa-dev] [PATCH 1/3] clover: Default to required minimum for CL_DEVICE_MAX_MEM_ALLOC_SIZE

Tom Stellard writes: > From: Tom Stellard > > --- > src/gallium/state_trackers/clover/api/device.cpp | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/src/gallium/state_trackers/clover/api/device.cpp > b/src/gallium/state_trackers/clover/api/device.cpp > index 1a9127b.

Re: [Mesa-dev] [PATCH 2/3] clover: Initialize height and depth to 1 for transfers

Tom Stellard writes: > From: Tom Stellard > Thanks, Reviewed-by: Francisco Jerez > --- > src/gallium/state_trackers/clover/api/transfer.cpp | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/gallium/state_trackers/clover/api/transfer.cpp > b/src/gallium/state_tracke

Re: [Mesa-dev] [PATCH 3/3] pipe-loader: Remove a few debug_printfs

Tom Stellard writes: > From: Tom Stellard > > On debug builds these were always being printed. > --- > > Are these printfs useful to anyone? Should they be controlled with an > ENV variable instead? > Not much I guess... Reviewed-by: Francisco Jerez > src/gallium/auxiliary/pipe-loader/pipe_l

Re: [Mesa-dev] [PATCH 1/8] i965/vp: Remove support for GLSL flow control from the old VS backend.

On 09/21/2012 03:11 AM, Eric Anholt wrote: > --- > src/mesa/drivers/dri/i965/brw_vs_emit.c | 83 > --- > 1 file changed, 83 deletions(-) And good riddance! For the series: Reviewed-by: Kenneth Graunke ___ mesa-dev maili

Re: [Mesa-dev] [PATCH] intel: Fix size of temporary etc1 buffer

Hello; On 09/20/2012 11:01 PM, Chad Versace wrote: > Adding Tapani to the CC list. Removing Oliver. > > On 09/20/2012 09:55 PM, Chad Versace wrote: >> Fixes valgrind errors in piglit test >> oes_compressed_etc1_rgb8_texture-miptree: an invalid write in >> _mesa_store_compressed_store_texsubimage(

[Mesa-dev] [PATCH 8/8] intel: Remove dead intel_format_to_rb_datatype.

This was for some of the old spans-related code that is now gone. --- src/mesa/drivers/dri/intel/intel_tex.h|2 - src/mesa/drivers/dri/intel/intel_tex_format.c | 50 - 2 files changed, 52 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_tex.h b/src

[Mesa-dev] [PATCH 7/8] intel: Mark some file-local code as static.

--- src/mesa/drivers/dri/i965/brw_shader.cpp |2 +- src/mesa/drivers/dri/i965/brw_state.h |5 - src/mesa/drivers/dri/i965/brw_state_upload.c |2 +- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |2 +- src/mesa/drivers/dri/intel/intel_batchbuffer.c

[Mesa-dev] [PATCH 6/8] i965: Mark brw_disasm.c tables as static const.

--- src/mesa/drivers/dri/i965/brw_disasm.c | 99 ++-- 1 file changed, 43 insertions(+), 56 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index aebfa73..c726ebd 100644 --- a/src/mesa/drivers/dri/i965/brw_dis

[Mesa-dev] [PATCH 5/8] i965: Use visibility cflags on the driver code.

The only symbols that need to be public (those in intel_screen.c that the loader looks for) are already marked public. Saves 100k of compiled driver size. --- src/mesa/drivers/dri/i965/Makefile.am |1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/Makefile.am b/src/

[Mesa-dev] [PATCH 4/8] i965/vp: Remove support for non-ARB_vp, non-NV_vp opcodes.

--- src/mesa/drivers/dri/i965/brw_vs_emit.c | 86 --- 1 file changed, 86 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index a4c4943..558a1df 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src

[Mesa-dev] [PATCH 2/8] i965/vp: Remove support for reading destination registers.

It's prohibited by ARB_vp and NV_vp, and not used by fixed function t&l. --- src/mesa/drivers/dri/i965/brw_vs.h |1 - src/mesa/drivers/dri/i965/brw_vs_emit.c | 67 ++- 2 files changed, 4 insertions(+), 64 deletions(-) diff --git a/src/mesa/drivers/dri/i965/b

[Mesa-dev] [PATCH 1/8] i965/vp: Remove support for GLSL flow control from the old VS backend.

--- src/mesa/drivers/dri/i965/brw_vs_emit.c | 83 --- 1 file changed, 83 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 46954bc..b2b59bc 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src

[Mesa-dev] [PATCH 3/8] i965/vp: Remove support for relative addressing of destination registers.

This was added for GLSL support back in the day. It's prohibited by both ARB_vp and NV_vp. --- src/mesa/drivers/dri/i965/brw_vs_emit.c | 90 +++ 1 file changed, 7 insertions(+), 83 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers

Re: [Mesa-dev] [PATCH 1/3] i965: Remove broken non-interleaved-to-interleaved upload code.

On 09/21/2012 10:29 AM, Kenneth Graunke wrote: On 09/21/2012 12:59 AM, Eric Anholt wrote: This failed when all the uploads to occur were uniform-type vertex data (like glColor4f being active across a DrawArrays), because it would upload 1 element instead of 1 element per vertex. There was no ci

Re: [Mesa-dev] [PATCH] intel: Fix size of temporary etc1 buffer

Chad Versace writes: > Fixes valgrind errors in piglit test > oes_compressed_etc1_rgb8_texture-miptree: an invalid write in > _mesa_store_compressed_store_texsubimage() at line 4406 and invalid reads > in texcompress_etc_tmp.h:etc1_parse_block(). > > The calculation of the size of the temporary e

Re: [Mesa-dev] FOSDEM2013: DevRoom or not?

On Sun, Aug 12, 2012 at 03:50:16PM +0200, Luc Verhaegen wrote: > Hi, > > The FOSDEM organizers have sent out a call for devrooms. FOSDEM this > year is on the weekend of the 2nd and 3rd of February 2013. > > After the success of this formula last year, where, for the first time > ever, we had a

Re: [Mesa-dev] [PATCH] intel: Improve teximage perf for Google Chrome paint rects (v3)

Chad Versace writes: > This patch reduces the time spent in glTexImage and glTexSubImage by > over 5x on Sandybridge for the workload described below. > > It adds a new fast path for glTexImage2D and glTexSubImage2D, > intel_texsubimage_tiled_memcpy, which is optimized for Google Chrome's > paint

Re: [Mesa-dev] [PATCH 1/3] i965: Remove broken non-interleaved-to-interleaved upload code.

On 09/21/2012 12:59 AM, Eric Anholt wrote: > This failed when all the uploads to occur were uniform-type vertex data (like > glColor4f being active across a DrawArrays), because it would upload 1 element > instead of 1 element per vertex. There was no citation for how this code > helped any partic

[Mesa-dev] [PATCH 2/3] i965: Add a comment explaining one of the brw_draw_upload.c loops.

--- src/mesa/drivers/dri/i965/brw_draw_upload.c |4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 31e092e..f5f65ca 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drive

[Mesa-dev] [PATCH 3/3] i965: Remove stale comment about rebuilding tnl_program.

It gets built in Mesa core before we're called these days. --- src/mesa/drivers/dri/i965/brw_draw.c |7 --- 1 file changed, 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index a09f555..21abfbe 100644 --- a/src/mesa/drivers/dri/i96

[Mesa-dev] [PATCH 1/3] i965: Remove broken non-interleaved-to-interleaved upload code.

This failed when all the uploads to occur were uniform-type vertex data (like glColor4f being active across a DrawArrays), because it would upload 1 element instead of 1 element per vertex. There was no citation for how this code helped any particular application, and it breaks ETQW, so just remov

Re: [Mesa-dev] [PATCH] i965: Remove brw_set_predicate_inverse(p, true) from scratch offset code

Kenneth Graunke writes: > Given that it exists between a push/pop of instruction state, this call > can only affect the MOV or ADD instruction generated just below it. > Neither of those instructions are predicated, so it makes no sense to > ask for the inverse predicate. > > This fixes grumbling