While the program won't successfully link in the end, this avoids
possible assertion failure in the driver during linking if
this->result isn't initialized with something already.
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --
The 965 driver was ignoring the VERTEX_PROGRAM_TWO_SIDE flag and only
looking at fixed-function state.
---
src/mesa/main/mtypes.h |2 ++
src/mesa/main/state.c | 18 +-
2 files changed, 19 insertions(+), 1 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtyp
Fixes piglit vertex-program-two-side back.
---
src/mesa/drivers/dri/i965/gen6_sf_state.c |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index bb8bc83..4482e9c 100644
--- a/src/m
Fixes piglit:
vertex-program-two-side
vertex-program-two-side primary
vertex-program-two-side secondary
---
src/mesa/drivers/dri/i965/brw_vs_constval.c |6 +++---
src/mesa/drivers/dri/i965/gen6_sf_state.c |5 +++--
src/mesa/drivers/dri/i965/gen7_sf_state.c |6 ++
3 files change
Removes 1.8% of the instructions from 97% of the vertex shaders in
shader-db.
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 177 +++
src/mesa/drivers/dri/i965/brw_vec4.h|1 +
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp |1 +
3 files changed, 179 inserti
We'll only do compute-to-MRF on accesses to this file.
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 10 ++
1 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 83f543f
This will be used for compute-to-mrf, which needs to know when MRFs
get overwritten.
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 37
src/mesa/drivers/dri/i965/brw_vec4.h |2 +
2 files changed, 39 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers
These were copy and pasted from the FS, and are never used.
---
src/mesa/drivers/dri/i965/brw_vec4.h |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 3f116ee..0f85cdb 100644
--- a/src/mesa/d
We've been referencing MRFs through the HW_REG file so far, but that
makes it harder to handle compute-to-MRF and similar optimizations.
---
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_
We generate silly code for array access, and it's easier to generally
support the cleanup than to specifically avoid the bad code in each
place we might generate it.
Removes 4.6% of instructions from 41.6% of shaders in shader-db,
particularly savage2/hon and unigine.
---
src/mesa/drivers/dri/i96
For those that don't care for i965, there's patch 7/10 to look at, to
go along with the proposed vertex-program-two-side piglit test.
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http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Fixes piglit nv_conditional_render-dlist.
---
src/mesa/main/dlist.c | 45 +
1 files changed, 45 insertions(+), 0 deletions(-)
diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
index 6e075b4..a80cfdc 100644
--- a/src/mesa/main/dlist.c
+++ b/sr
>From the NV_conditional_render spec:
BeginQuery sets the active query object name for the query type given by
to . If BeginQuery is called with an of zero, if the
active query object name for is non-zero, if is the active
query object name for any query type, or if is the ac
>From the NV_conditional_render spec:
BeginQuery sets the active query object name for the query type given by
to . If BeginQuery is called with an of zero, if the
active query object name for is non-zero, if is the active
query object name for any query type, or if is the ac
On Thu, Sep 08, 2011 at 09:25:30PM -0700, Kenneth Graunke wrote:
> On 09/08/2011 06:59 PM, Yuanhan Liu wrote:
> > On Thu, Sep 08, 2011 at 08:39:46AM -0700, Eric Anholt wrote:
> >> On Thu, 8 Sep 2011 11:00:52 +0800, Yuanhan Liu
> >> wrote:
> >>> BTW, this patch fix the oglc pntrast fail on SNB(ha
On Thu, Sep 08, 2011 at 09:12:44PM -0700, Kenneth Graunke wrote:
> On 09/08/2011 07:56 PM, Yuanhan Liu wrote:
> > There is already comments show how to detect a null texture. Fix the
> > code to match the comments.
> >
> > This would fix the oglc divzero(basic.texQOrWEqualsZero) and
> > divzero(ba
https://bugs.freedesktop.org/show_bug.cgi?id=40729
--- Comment #6 from Alexandre Demers 2011-09-08
22:13:10 PDT ---
Review of attachment 50992:
--> (https://bugs.freedesktop.org/review?bug=40729&attachment=50992)
Need to replace "struct pipe_present_control ctrl;" by "struct
native_present_con
https://bugs.freedesktop.org/show_bug.cgi?id=40729
--- Comment #5 from Alexandre Demers 2011-09-08
22:10:52 PDT ---
OK, I think I got it working. You must have meant to replace "pipe" by "native"
at line 1109. Doing this fixed your patch and allowed me to build without
error.
--
Configure bugm
On Fri, Sep 09, 2011 at 10:56:36AM +0800, Yuanhan Liu wrote:
> There is already comments show how to detect a null texture. Fix the
> code to match the comments.
>
> This would fix the oglc divzero(basic.texQOrWEqualsZero) and
> divzero(basic.texTrivialPrim) test case fail.
>
> Signed-off-by: Yua
https://bugs.freedesktop.org/show_bug.cgi?id=40729
--- Comment #4 from Alexandre Demers 2011-09-08
22:03:17 PDT ---
(In reply to comment #3)
> (In reply to comment #2)
> > src/dxgi_native.cpp: In member function ‘virtual HRESULT
> > GalliumDXGISwapChain::Present(UINT, UINT)’:
> > src/dxgi_native
https://bugs.freedesktop.org/show_bug.cgi?id=40729
--- Comment #3 from Chia-I Wu 2011-09-08 21:56:10 PDT ---
(In reply to comment #2)
> src/dxgi_native.cpp: In member function ‘virtual HRESULT
> GalliumDXGISwapChain::Present(UINT, UINT)’:
> src/dxgi_native.cpp:1109:31: error: aggregate
> ‘Gallium
https://bugs.freedesktop.org/show_bug.cgi?id=40729
--- Comment #2 from Alexandre Demers 2011-09-08
21:41:56 PDT ---
Not quite yet:
g++ -c -I. -I../../../../../src/gallium/include
-I../../../../../src/gallium/auxiliary -I../../../../../src/gallium/drivers
-I../../../../../include -Iinclude -I../
On 09/08/2011 06:59 PM, Yuanhan Liu wrote:
> On Thu, Sep 08, 2011 at 08:39:46AM -0700, Eric Anholt wrote:
>> On Thu, 8 Sep 2011 11:00:52 +0800, Yuanhan Liu
>> wrote:
>>> BTW, this patch fix the oglc pntrast fail on SNB(haven't tested it on
>>> IVB yet).
>>
>> Could you include a piglit test for
i915_miptree_layout, i945_miptree_layout, and brw_miptree_layout always
just return GL_TRUE, so there's really no point to it. Change them to
void functions and remove the (dead) error checking code.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i915/i915_tex_layout.c|8 ++
On 09/08/2011 07:56 PM, Yuanhan Liu wrote:
> There is already comments show how to detect a null texture. Fix the
> code to match the comments.
>
> This would fix the oglc divzero(basic.texQOrWEqualsZero) and
> divzero(basic.texTrivialPrim) test case fail.
>
> Signed-off-by: Yuanhan Liu
> ---
>
https://bugs.freedesktop.org/show_bug.cgi?id=40729
--- Comment #1 from Chia-I Wu 2011-09-08 21:01:08 PDT ---
Created an attachment (id=50992)
View: https://bugs.freedesktop.org/attachment.cgi?id=50992
Review: https://bugs.freedesktop.org/review?bug=40729&attachment=50992
fix the build error
Y
There is already comments show how to detect a null texture. Fix the
code to match the comments.
This would fix the oglc divzero(basic.texQOrWEqualsZero) and
divzero(basic.texTrivialPrim) test case fail.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c |2 +-
1
On Thu, Sep 08, 2011 at 01:16:23PM -0700, Ian Romanick wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> On 09/08/2011 03:16 AM, Yuanhan Liu wrote:
> > If user call glTexImage1D with width = 0 and height = 0(the last
> > level) like this: glTexImage1D(GL_TEXTURE_1D, level, interfomart,
On 8 September 2011 18:06, Eric Anholt wrote:
> On Thu, 08 Sep 2011 12:57:31 -0700, Ian Romanick
> wrote:
> > -BEGIN PGP SIGNED MESSAGE-
> > Hash: SHA1
> >
> > On 09/07/2011 12:51 PM, Eric Anholt wrote:
> > > Previously, it would produce:
> > >
> > > Failed to compile FS: 0:6(7): error:
On Thu, Sep 08, 2011 at 08:39:46AM -0700, Eric Anholt wrote:
> On Thu, 8 Sep 2011 11:00:52 +0800, Yuanhan Liu
> wrote:
> > This patch is just for RFC, as I am not sure it's the right way to setup
> > the edge flag enable bit in Vertex Element struture. Setting up this
> > bit, according to Bspec
On Thu, 08 Sep 2011 12:57:31 -0700, Ian Romanick wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> On 09/07/2011 12:51 PM, Eric Anholt wrote:
> > Previously, it would produce:
> >
> > Failed to compile FS: 0:6(7): error: non-lvalue in assignment
> >
> > and now it produces:
> >
> >
Am 08.09.2011 21:43, schrieb Ian Romanick:
> On 09/08/2011 12:18 PM, Roland Scheidegger wrote:
>> Am 08.09.2011 21:03, schrieb Roland Scheidegger:
>>> Am 08.09.2011 19:53, schrieb Ian Romanick:
On 09/06/2011 03:21 PM, Roland Scheidegger wrote:
> Am 06.09.2011 22:13, schrieb Ian Romanick:
>
Am 08.09.2011 23:13, schrieb Marek Olšák:
> On Thu, Sep 8, 2011 at 9:03 PM, Roland Scheidegger wrote:
>> Am 08.09.2011 19:53, schrieb Ian Romanick:
>>> On 09/06/2011 03:21 PM, Roland Scheidegger wrote:
Am 06.09.2011 22:13, schrieb Ian Romanick:
> From: Ian Romanick
>
> Core Mesa
https://bugs.freedesktop.org/show_bug.cgi?id=40729
Summary: d3d1x build error: any interface changes lately?
Product: Mesa
Version: git
Platform: All
OS/Version: All
Status: NEW
Severity: major
Priority: medium
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_emit.cpp|5 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 15 +++
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
b/src/mesa/drivers/dri/i965
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 23 ---
1 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index d413bc4..31a2297 10064
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_defines.h |2 ++
src/mesa/drivers/dri/i965/brw_fs.cpp |1 +
src/mesa/drivers/dri/i965/brw_fs.h |1 +
src/mesa/drivers/dri/i965/brw_fs_emit.cpp|4
src/mesa/drivers/dri/i965/brw_fs_visit
These patches implement texelFetch/TXF via the "ld" sampler message on all
i965 platforms. I've tested it on Broadwater, Cantiga, Sandybridge, and
Ivybridge. Pretty sure I tested on Ironlake too, but a while ago.
Piglit tests fs-texelFetch-2D and fs-texelFetchOffset-2D pass now.
Huge thanks to D
On 09/07/2011 01:03 PM, Eric Anholt wrote:
> With the core GLSL fixups I just sent out plus this patch series, I
> think it's ready to turn on by default. piglit is non-regressing, and
> the oglconform I've tested is overall better (but not perfect), and I
> think it will fix one actual bug report
On Thu, Sep 8, 2011 at 9:03 PM, Roland Scheidegger wrote:
> Am 08.09.2011 19:53, schrieb Ian Romanick:
>> On 09/06/2011 03:21 PM, Roland Scheidegger wrote:
>>> Am 06.09.2011 22:13, schrieb Ian Romanick:
From: Ian Romanick
Core Mesa already does the dispatch offset remapping for eve
On Thu, 08 Sep 2011 20:13:45 +0200, Roland Scheidegger
wrote:
> Am 08.09.2011 19:59, schrieb Eric Anholt:
> > On Thu, 08 Sep 2011 10:53:45 -0700, Ian Romanick
> > wrote:
> >> -BEGIN PGP SIGNED MESSAGE-
> >> Hash: SHA1
> >>
> >> On 09/06/2011 03:21 PM, Roland Scheidegger wrote:
> >>> EXT
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 09/07/2011 01:03 PM, Eric Anholt wrote:
> With the core GLSL fixups I just sent out plus this patch series,
> I think it's ready to turn on by default. piglit is
> non-regressing, and the oglconform I've tested is overall better
> (but not perfect)
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 09/08/2011 03:16 AM, Yuanhan Liu wrote:
> If user call glTexImage1D with width = 0 and height = 0(the last
> level) like this: glTexImage1D(GL_TEXTURE_1D, level, interfomart,
> 0, 0, format, type, pixel)
>
> It would generate a SIGSEGV fault. As i9
On Mon, 29 Aug 2011 14:59:02 -0700, "Ian Romanick" wrote:
> From: Ian Romanick
>
> The test was of an enum, attIndex, which should be unsigned. The
> explicit check for < 0 was replaced with a cast to unsigned in an
> assertion that attIndex is less than the size of the array it will be
> used
On Mon, 29 Aug 2011 14:59:00 -0700, "Ian Romanick" wrote:
> From: Ian Romanick
>
> The internalFormat, format, and type parameters were not used by
> either try_pbo_upload or try_pbo_zcopy, so remove them. The width
> parameter was also not used by try_pbo_zcopy (because it doesn't
> actually c
On Mon, 29 Aug 2011 14:58:59 -0700, "Ian Romanick" wrote:
> From: Ian Romanick
>
> The depth0 parameter was not used in intel_miptree_create_for_region,
> so remove it. All of the places that call this function, pass 1 for
> that parameter, and the place where it looks like it should have been
On Mon, 29 Aug 2011 14:58:58 -0700, "Ian Romanick" wrote:
> From: Ian Romanick
>
> The GLenum target parameter was not used in intel_copy_texsubimage, so
> remove it.
We should also stop having all 3 callers look up the internalFormat from
the texImage->InternalFormat and pass it in.
pgp5c7qs
On Mon, 29 Aug 2011 14:58:56 -0700, "Ian Romanick" wrote:
> From: Ian Romanick
>
> The gl_framebuffer was not used in intel_draw_buffer, so remove it.
Reviewed-by: Eric Anholt
pgpon7SjIctA3.pgp
Description: PGP signature
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m
On Mon, 29 Aug 2011 14:58:54 -0700, "Ian Romanick" wrote:
> From: Ian Romanick
>
> ---
> src/mesa/drivers/dri/intel/intel_buffer_objects.c | 47
> ++---
> 1 files changed, 31 insertions(+), 16 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c
>
On Mon, 29 Aug 2011 14:58:53 -0700, "Ian Romanick" wrote:
> From: Ian Romanick
>
> ---
> src/mesa/drivers/dri/intel/intel_batchbuffer.h |4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h
> b/src/mesa/drivers/dri/inte
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 09/07/2011 12:51 PM, Eric Anholt wrote:
> Previously, it would produce:
>
> Failed to compile FS: 0:6(7): error: non-lvalue in assignment
>
> and now it produces:
>
> Failed to compile FS: 0:5(7): error: whole array assignment is not
> allowed i
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 09/08/2011 12:18 PM, Roland Scheidegger wrote:
> Am 08.09.2011 21:03, schrieb Roland Scheidegger:
>> Am 08.09.2011 19:53, schrieb Ian Romanick:
>>> On 09/06/2011 03:21 PM, Roland Scheidegger wrote:
Am 06.09.2011 22:13, schrieb Ian Romanick:
>>>
Am 08.09.2011 21:03, schrieb Roland Scheidegger:
> Am 08.09.2011 19:53, schrieb Ian Romanick:
>> On 09/06/2011 03:21 PM, Roland Scheidegger wrote:
>>> Am 06.09.2011 22:13, schrieb Ian Romanick:
From: Ian Romanick
Core Mesa already does the dispatch offset remapping for every
fu
Am 08.09.2011 19:53, schrieb Ian Romanick:
> On 09/06/2011 03:21 PM, Roland Scheidegger wrote:
>> Am 06.09.2011 22:13, schrieb Ian Romanick:
>>> From: Ian Romanick
>>>
>>> Core Mesa already does the dispatch offset remapping for every
>>> function that could possibly ever be supported. There's no
Am 08.09.2011 19:59, schrieb Eric Anholt:
> On Thu, 08 Sep 2011 10:53:45 -0700, Ian Romanick wrote:
>> -BEGIN PGP SIGNED MESSAGE-
>> Hash: SHA1
>>
>> On 09/06/2011 03:21 PM, Roland Scheidegger wrote:
>>> EXT_blend_equation_separate allows some unholy combinations which the
>>> r200 (possib
On Thu, 08 Sep 2011 10:53:45 -0700, Ian Romanick wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> On 09/06/2011 03:21 PM, Roland Scheidegger wrote:
> > EXT_blend_equation_separate allows some unholy combinations which the
> > r200 (possibly other hw too) can't handle correctly. Namely
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 09/06/2011 03:21 PM, Roland Scheidegger wrote:
> Am 06.09.2011 22:13, schrieb Ian Romanick:
>> From: Ian Romanick
>>
>> Core Mesa already does the dispatch offset remapping for every
>> function that could possibly ever be supported. There's no ne
Am 08.09.2011 09:08, schrieb Marek Olšák:
> 2011/9/7 Roland Scheidegger :
>> That said I'm not really sure why pipe_sampler_view and pipe_surface
>> actually have a context pointer in them, since they are only supposed to
>> be used with the context in which they were created I think those
>> shoul
On Thu, 8 Sep 2011 11:00:52 +0800, Yuanhan Liu
wrote:
> This patch is just for RFC, as I am not sure it's the right way to setup
> the edge flag enable bit in Vertex Element struture. Setting up this
> bit, according to Bspec, need do:
> 1. Edge flags are supported for the following primitives
If user call glTexImage1D with width = 0 and height = 0(the
last level) like this:
glTexImage1D(GL_TEXTURE_1D, level, interfomart, 0, 0, format, type, pixel)
It would generate a SIGSEGV fault. As i945_miptree_layout_2d
didn't handle this special case. More info are commented in line
in this patch.
On Thu, Sep 8, 2011 at 3:53 PM, Benjamin Franzke
wrote:
> 2011/9/8 Chia-I Wu :
>> On Thu, Sep 8, 2011 at 3:11 PM, Benjamin Franzke
>> wrote:
>>> First thanks for taking this on.
>>>
>>> There are some things I'd like to have addtionally/differently:
>>>
>>> Supported shm formats are exposed via a
2011/9/8 Chia-I Wu :
> On Thu, Sep 8, 2011 at 3:13 PM, Benjamin Franzke
> wrote:
>> 2011/9/8 Chia-I Wu :
>>> From: Chia-I Wu
>>>
>>> Return true for NATIVE_PARAM_PREMULTIPLIED_ALPHA when all formats with
>>> alpha support premultiplied alpha. Currently, it means when argb32 and
>>> argb32_pre ar
2011/9/8 Chia-I Wu :
> On Thu, Sep 8, 2011 at 3:11 PM, Benjamin Franzke
> wrote:
>> First thanks for taking this on.
>>
>> There are some things I'd like to have addtionally/differently:
>>
>> Supported shm formats are exposed via a "format" event as well
>> (like the supported drm formats), so th
On Thu, Sep 8, 2011 at 3:41 PM, Chia-I Wu wrote:
> On Thu, Sep 8, 2011 at 3:11 PM, Benjamin Franzke
> wrote:
>> First thanks for taking this on.
>>
>> There are some things I'd like to have addtionally/differently:
>>
>> Supported shm formats are exposed via a "format" event as well
>> (like the
On Thu, Sep 8, 2011 at 3:13 PM, Benjamin Franzke
wrote:
> 2011/9/8 Chia-I Wu :
>> From: Chia-I Wu
>>
>> Return true for NATIVE_PARAM_PREMULTIPLIED_ALPHA when all formats with
>> alpha support premultiplied alpha. Currently, it means when argb32 and
>> argb32_pre are both supported.
>> ---
>> ..
On Thu, Sep 8, 2011 at 3:11 PM, Benjamin Franzke
wrote:
> First thanks for taking this on.
>
> There are some things I'd like to have addtionally/differently:
>
> Supported shm formats are exposed via a "format" event as well
> (like the supported drm formats), so the config creation logic is the
2011/9/8 Chia-I Wu :
> From: Chia-I Wu
>
> Return true for NATIVE_PARAM_PREMULTIPLIED_ALPHA when all formats with
> alpha support premultiplied alpha. Currently, it means when argb32 and
> argb32_pre are both supported.
> ---
> .../state_trackers/egl/wayland/native_drm.c | 8 ++--
>
First thanks for taking this on.
There are some things I'd like to have addtionally/differently:
Supported shm formats are exposed via a "format" event as well
(like the supported drm formats), so the config creation logic is the
same for drm and shm, and I think it can remain in native_wayland.c
2011/9/7 Roland Scheidegger :
> That said I'm not really sure why pipe_sampler_view and pipe_surface
> actually have a context pointer in them, since they are only supposed to
> be used with the context in which they were created I think those
> shouldn't actually exist - surface_destroy and sample
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