On Thu, 8 Sep 2011 11:00:52 +0800, Yuanhan Liu <yuanhan....@linux.intel.com> wrote: > This patch is just for RFC, as I am not sure it's the right way to setup > the edge flag enable bit in Vertex Element struture. Setting up this > bit, according to Bspec, need do: > 1. Edge flags are supported for the following primitives > 3DPRIM_TRILIST* > 3DPRIM_TRISTRIP* > 3DPRIM_TRIFAN* > 3DPRIM_POLYGON > 2. This bit must only be ENABLED on the last valid VERTEX_ELEMENT > structure. > > 3. When set, Component 0 Control must be set to VFCOMP_STORE_SRC, and > Component 1-3 Control must be set to VFCOMP_NOSTORE. > > 4. The Source Element Format must be set to the UINT format. > > This patch did 1, 2, but didn't do 3, 4. As it simply seems wrong to me > just change the last vetex element's component setting and source > element format. > > Thoughts? > > BTW, this patch fix the oglc pntrast fail on SNB(haven't tested it on > IVB yet).
Could you include a piglit test for the failure? > + /* > + * According to Bspec, the edge flag enable bit should be set > + * at the last valid vertex element structure > + */ Instead of saying "According to the Bspec", could you actually cite the text from the public PRM? For example, in one of my previous patches: ... + * And this last workaround is tricky because of the requirements on + * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM + * volume 2 part 1: + * + * "1 of the following must also be set: + * - Render Target Cache Flush Enable ([12] of DW1) + * - Depth Cache Flush Enable ([0] of DW1) + * - Stall at Pixel Scoreboard ([1] of DW1) + * - Depth Stall ([13] of DW1) + * - Post-Sync Operation ([13] of DW1) + * - Notify Enable ([8] of DW1)" It means that someone else stumbling on this code later gets a pointer to where to start reading up on what's going on in the code.
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