From: Ian Munsie
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
drivers/misc/cxl/Kconfig | 18 ++
drivers/misc/cxl/Makefile | 3 +++
2 files changed, 21 insertions(+)
diff --git a/drivers/misc/cxl/Kconfig b/drivers/misc/cxl/Kconfig
index 48533e1..d413e90
From: Ian Munsie
This documentation gives an overview of the hardware architecture, userspace
APIs via /dev/cxl/afu0.0 and the syfs files. It also adds a MAINTAINERS file
entry for cxl.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
Documentation/ABI/testing/sysfs-class-cxl
> > @@ -58,12 +56,12 @@ int spu_handle_mm_fault(struct mm_struct *mm, unsigned
> > long ea,
> > goto out_unlock;
> > }
> >
> > - is_write = dsisr & MFC_DSISR_ACCESS_PUT;
> > + is_write = dsisr & DSISR_ISSTORE;
> > if (is_write) {
> > if (!(vma->vm_flag
> > +
> > +int copro_data_segment(struct mm_struct *mm, u64 ea, u64 *esid, u64 *vsid)
> > +{
> > + int psize, ssize;
> > +
> > + *esid = (ea & ESID_MASK) | SLB_ESID_V;
> > +
> > + switch (REGION_ID(ea)) {
> > + case USER_REGION_ID:
> > + pr_devel("copro_data_segment: 0x%llx -- USE
> >+static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
> >+{
> >+struct irq_data *idata;
> >+struct irq_chip *ichip;
> >+
> >+/*
> >+ * Change the IRQ chip for the MSI interrupts on PHB3.
> >+ * The corresponding IRQ chip should be populated for
> >+ * the
> >+struct device_node *pnv_pci_to_phb_node(struct pci_dev *dev)
> >+{
> >+struct device_node *np;
> >+struct property *prop = NULL;
> >+
> >+np = of_node_get(pci_device_to_OF_node(dev));
> >+
> >+/* Scan up the tree looking for the PHB node */
> >+while (np) {
> >+
> > diff --git a/arch/powerpc/sysdev/msi_bitmap.c
> > b/arch/powerpc/sysdev/msi_bitmap.c
> > index 2ff6302..e001559 100644
> > --- a/arch/powerpc/sysdev/msi_bitmap.c
> > +++ b/arch/powerpc/sysdev/msi_bitmap.c
> > @@ -24,28 +24,36 @@ int msi_bitmap_alloc_hwirqs(struct msi_bitmap *bmp, int
> > num)
for other co-processors. This moves
> > the code of the cell platform so it can be used by other powerpc code.
>
> Could we also mention:
>
> and adds 1TB segment support.
Good point. I'll add.
> > Signed-off-by: Ian Munsie
> > Signed-off
gt;
> > This also adds a hooks for when SLBs are invalidated to ensure any
> > corresponding SLBs in cxl are also invalidated at the same time.
> >
> > Signed-off-by: Ian Munsie
> > Signed-off-by: Michael Neuling
>
> > + use_local = local &
On Mon, 2014-09-29 at 14:00 +0530, Aneesh Kumar K.V wrote:
> Michael Neuling writes:
>
> > From: Ian Munsie
> >
> > __spu_trap_data_seg() currently contains code to determine the VSID and ESID
> > required for a particular EA and mm struct.
> >
> > Th
> > You also added code to handle KERNEL_REGION_ID in
> > [PATCH 02/15] powerpc/cell: Move data segment faulting code out of cell
> > platform. do we need to handle that here ?
> >
(Sorry missed this on my other reply...)
I've refactored that code now so it should be handled in the vsid
calculat
v2:
- Updates based on comments from, Anton, Gavin, Aneesh, jk and offline reviews
- Simplified copro_data_segment() and merged code with hash_page_mm()
(New patch 10/17)
- PCIe code simplifications based on Gavin's review
- Removed redundant comment in msi_bitmap_alloc_hwirqs()
- Fix for
-by: Michael Neuling
---
arch/powerpc/Kconfig | 4
arch/powerpc/include/asm/copro.h | 18 ++
arch/powerpc/include/asm/spu.h | 5 ++---
arch/powerpc/mm/Makefile | 1
segment handling which Cell didn't have.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/mmu-hash64.h | 7 -
arch/powerpc/mm/copro_fault.c | 48 ++
arch/powerpc/mm/slb.c | 3 ---
arch/po
From: Ian Munsie
This moves spu_flush_all_slbs() into a generic call copro_flush_all_slbs().
This will be useful when we add cxl which also needs a similar SLB flush call.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/copro.h | 6 ++
arch/powerpc
igned-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/sysdev/msi_bitmap.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/sysdev/msi_bitmap.c b/arch/powerpc/sysdev/msi_bitmap.c
index 2ff6302..961a358 100644
--- a/arch/po
From: Ian Munsie
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/mm/hash_utils_64.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 5c0738d..bbdb054 100644
--- a/arch/powerpc/mm
From: Ian Munsie
Some of the MSI IRQ code in pnv_pci_ioda_msi_setup() is generically useful so
split it out.
This will be used by some of the cxl PCIe code later.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/platforms/powernv/pci-ioda.c | 43
From: Ian Munsie
This new header add defines for callbacks and structs needed by the rest of the
kernel to hook into the cxl infrastructure.
Empty functions are provided when CONFIG CXL_BASE is not enabled.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
include/misc/cxl.h | 34
From: Ian Munsie
This adds a number of functions for allocating IRQs under powernv PCIe for cxl.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/pnv-pci.h| 27 +
arch/powerpc/platforms/powernv/pci-ioda.c | 161
be careful here as the current hash_page() assumes current in a few
places.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/mmu-hash64.h | 1 +
arch/powerpc/mm/hash_utils_64.c | 22 ++
2 files changed, 15 insertions(+), 8 deletions
From: Ian Munsie
This adds the OPAL call to change a PHB into cxl mode.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/opal.h| 2 ++
arch/powerpc/platforms/powernv/opal-wrappers.S | 1 +
2 files changed, 3 insertions(+)
diff --git a
From: Ian Munsie
The vsid calculation between hash_page() and copro_data_segment() are very
similar. This merges these two different versions.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/mmu-hash64.h | 2 ++
arch/powerpc/mm/copro_fault.c
igned-off-by: Michael Neuling
---
arch/powerpc/mm/copro_fault.c| 2 ++
arch/powerpc/mm/hash_native_64.c | 6 +-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/copro_fault.c b/arch/powerpc/mm/copro_fault.c
index ba8bf8e..219dadb 100644
--- a/arch/power
cxl contexts are currently in use. This is used by the tlbie() to
determine if it can do local TLB invalidations or not. This also adds get/put
calls for the cxl driver module to refcount the active cxl contexts.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
drivers/misc/Kconfig
From: Ian Munsie
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
drivers/misc/cxl/Kconfig | 18 ++
drivers/misc/cxl/Makefile | 3 +++
2 files changed, 21 insertions(+)
diff --git a/drivers/misc/cxl/Kconfig b/drivers/misc/cxl/Kconfig
index 5cdd319..967b5c8
From: Ian Munsie
This defines structs and magic numbers required for userspace to interact with
the kernel cxl driver via /dev/cxl/afu0.0.
It adds this header file Kbuild so it's exported when doing make
headers_installs.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
in
From: Ian Munsie
This documentation gives an overview of the hardware architecture, userspace
APIs via /dev/cxl/afu0.0 and the syfs files. It also adds a MAINTAINERS file
entry for cxl.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
Documentation/ABI/testing/sysfs-class-cxl
On Wed, 2014-10-01 at 17:13 +1000, Michael Ellerman wrote:
> On Tue, 2014-30-09 at 10:34:52 UTC, Michael Neuling wrote:
> > diff --git a/arch/powerpc/include/asm/copro.h
> > b/arch/powerpc/include/asm/copro.h
> > index 2858108..f3d338f 100644
> > --- a/arch/powerpc/in
On Wed, 2014-10-01 at 15:15 +0530, Aneesh Kumar K.V wrote:
> Michael Neuling writes:
>
> > From: Ian Munsie
> >
> > __spu_trap_data_seg() currently contains code to determine the VSID and ESID
> > required for a particular EA and mm struct.
> >
> > Th
On Wed, 2014-10-01 at 16:47 +1000, Michael Ellerman wrote:
> On Tue, 2014-30-09 at 10:34:51 UTC, Michael Neuling wrote:
> > From: Ian Munsie
> >
> > __spu_trap_data_seg() currently contains code to determine the VSID and ESID
> > required for a particular EA and mm st
On Wed, 2014-10-01 at 15:23 +0530, Aneesh Kumar K.V wrote:
> Michael Neuling writes:
>
> > From: Ian Munsie
> >
> > __spu_trap_data_seg() currently contains code to determine the VSID and ESID
> > required for a particular EA and mm struct.
> >
> > Th
On Wed, 2014-10-01 at 17:13 +1000, Michael Ellerman wrote:
> On Tue, 2014-30-09 at 10:34:53 UTC, Michael Neuling wrote:
> > From: Ian Munsie
> >
> > Currently msi_bitmap_alloc_hwirqs() will round up any IRQ all
On Wed, 2014-10-01 at 17:13 +1000, Michael Ellerman wrote:
> On Tue, 2014-30-09 at 10:34:54 UTC, Michael Neuling wrote:
> > From: Ian Munsie
>
> Mind explaining why ? :)
Sure.
Mikey
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.o
On Wed, 2014-10-01 at 22:00 +1000, Michael Ellerman wrote:
> On Tue, 2014-30-09 at 10:34:56 UTC, Michael Neuling wrote:
> > From: Ian Munsie
> >
> > This new header add defines for callbacks and structs needed by the rest of
> > the
> adds
&
On Wed, 2014-10-01 at 22:00 +1000, Michael Ellerman wrote:
> On Tue, 2014-30-09 at 10:35:02 UTC, Michael Neuling wrote:
> > This also adds the cxl_ctx_in_use() function for use in the mm code to see
> > if
> > any cxl contexts are currently in use. This is used by the tlbie(
On Thu, 2014-10-02 at 11:57 +1000, Michael Ellerman wrote:
> On Tue, 2014-30-09 at 10:34:55 UTC, Michael Neuling wrote:
> > From: Ian Munsie
> >
> > Some of the MSI IRQ code in pnv_pci_ioda_msi_setup() is generically useful
> > so
> > split it out.
> >
&
On Thu, 2014-10-02 at 13:16 +1000, Michael Ellerman wrote:
> On Tue, 2014-30-09 at 10:34:57 UTC, Michael Neuling wrote:
> > From: Ian Munsie
> >
> > This adds a number of functions for allocating IRQs under powernv PCIe for
> > cxl.
> >
> > diff --g
On Wed, 2014-10-01 at 15:25 +0530, Aneesh Kumar K.V wrote:
> Michael Neuling writes:
>
> > From: Ian Munsie
> >
> > The vsid calculation between hash_page() and copro_data_segment() are very
> > similar. This merges these two different versions.
> >
>
On Wed, 2014-10-01 at 15:13 +0530, Aneesh Kumar K.V wrote:
> Michael Neuling writes:
>
> > From: Ian Munsie
> >
> > This adds a new function hash_page_mm() based on the existing hash_page().
> > This version allows any struct mm to be passed in, rather than assumin
On Thu, 2014-10-02 at 13:48 +1000, Michael Ellerman wrote:
> On Tue, 2014-30-09 at 10:34:58 UTC, Michael Neuling wrote:
> > From: Ian Munsie
> >
> > This adds a new function hash_page_mm() based on the existing hash_page().
> > This version allows any struct mm t
This is the latest version of the cxl driver. Change log below:
v3:
- Updates based on comments from mpe, benh, aneesh and offline reviews.
- Fixed bug freeing AFU IRQs that also freed the multiplexed PSL IRQ
- Change copro_flush_all_slbs to a static inline as suggested by mpe
- Implement san
-by: Michael Neuling
---
arch/powerpc/Kconfig | 4
arch/powerpc/include/asm/copro.h | 18 ++
arch/powerpc/include/asm/spu.h | 5 ++---
arch/powerpc/mm/Makefile | 1
segment handling which Cell didn't have.
This also moves the internal struct spu_slb to a generic struct copro_slb which
is now used in the spu and copro code. We use this new struct instead of the
us passing around esid and vsid parameters.
Signed-off-by: Ian Munsie
Signed-off-by: Mi
From: Ian Munsie
This moves spu_flush_all_slbs() into a generic call copro_flush_all_slbs().
This will be useful when we add cxl which also needs a similar SLB flush call.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/copro.h | 6 ++
arch/powerpc
ement though.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/sysdev/msi_bitmap.c | 33 ++---
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/sysdev/msi_bitmap.c b/arch/powerpc/sysdev/msi_bitmap.c
index 2ff6302..56
From: Ian Munsie
Export mmu_kernel_ssize and mmu_linear_psize. These are needed by the cxl
driver which has it's own MMU. To setup the MMU cxl need access to these.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/mm/hash_utils_64.c | 2 ++
1 file chang
From: Ian Munsie
Some of the MSI IRQ code in pnv_pci_ioda_msi_setup() is generically useful so
split it out.
This will be used by some of the cxl PCIe code later.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/platforms/powernv/pci-ioda.c | 42
when CONFIG_CXL_BASE is not enabled.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
include/misc/cxl.h | 48
1 file changed, 48 insertions(+)
create mode 100644 include/misc/cxl.h
diff --git a/include/misc/cxl.h b/include/misc/cxl.h
new file
From: Ian Munsie
This adds a number of functions for allocating IRQs under powernv PCIe for cxl.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/pnv-pci.h| 27 ++
arch/powerpc/platforms/powernv/pci-ioda.c | 153
be careful here as the current hash_page() assumes current in a few
places.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/mmu-hash64.h | 1 +
arch/powerpc/mm/hash_utils_64.c | 24 +---
2 files changed, 18 insertions(+), 7
From: Ian Munsie
This adds the OPAL call to change a PHB into cxl mode.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/opal.h| 2 ++
arch/powerpc/platforms/powernv/opal-wrappers.S | 1 +
2 files changed, 3 insertions(+)
diff --git a
d-off-by: Michael Neuling
---
arch/powerpc/mm/copro_fault.c| 2 ++
arch/powerpc/mm/hash_native_64.c | 6 +-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/copro_fault.c b/arch/powerpc/mm/copro_fault.c
index 222ef9b..55791fc 100644
--- a/arch/powerpc/mm/copro_fa
contexts are currently in use. This is used by the tlbie() to
determine if it can do local TLB invalidations or not. This also adds get/put
calls for the cxl driver module to refcount the active cxl contexts.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
drivers/misc/Kconfig
From: Ian Munsie
This defines structs and magic numbers required for userspace to interact with
the kernel cxl driver via /dev/cxl/afu0.0.
It adds this header file Kbuild so it's exported when doing make
headers_installs.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
in
From: Ian Munsie
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
drivers/misc/cxl/Kconfig | 10 ++
drivers/misc/cxl/Makefile | 2 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/misc/cxl/Kconfig b/drivers/misc/cxl/Kconfig
index 5cdd319..585d6e3 100644
--- a
From: Ian Munsie
This documentation gives an overview of the hardware architecture, userspace
APIs via /dev/cxl/afu0.0 and the syfs files. It also adds a MAINTAINERS file
entry for cxl.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
Documentation/ABI/testing/sysfs-class-cxl
> > +int copro_data_segment(struct mm_struct *mm, u64 ea, u64 *esid, u64 *vsid);
>
> This function is otherwise not included in this patch, so it should
> probably be removed (as the next patch removes it anyway).
Yeah, looks like I screwed it up slightly in the packing of these
patches.
Thanks
On Wed, 2014-10-08 at 10:04 +1100, Michael Ellerman wrote:
> On Tue, 2014-07-10 at 10:48:18 UTC, Michael Neuling wrote:
> > From: Ian Munsie
> >
> > This adds the base cxl support that needs to be build into the kernel to use
> > cxl as a module. This is needed so t
On Wed, 2014-10-08 at 09:59 +1100, Michael Ellerman wrote:
> On Tue, 2014-07-10 at 10:48:14 UTC, Michael Neuling wrote:
> > From: Ian Munsie
> >
> > This adds a number of functions for allocating IRQs under powernv PCIe for
> > cxl.
> >
> > diff --g
This is the latest version of the cxl driver. Change log below:
v4:
- Updates based on comments from mpe (offline and online).
- Refactor the sstp lock to be an entry lock.
- Fixed error paths on new status_mutex in start_work
- added some missing include files
- moved associating pid/mm fro
-by: Michael Neuling
---
arch/powerpc/Kconfig | 4
arch/powerpc/include/asm/copro.h | 16
arch/powerpc/include/asm/spu.h | 5 ++---
arch/powerpc/mm/Makefile
igned-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/copro.h | 7 +
arch/powerpc/include/asm/mmu-hash64.h | 7 +
arch/powerpc/mm/copro_fault.c | 46
arch/powerpc/mm/slb.c | 3 --
arch/po
From: Ian Munsie
This moves spu_flush_all_slbs() into a generic call copro_flush_all_slbs().
This will be useful when we add cxl which also needs a similar SLB flush call.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/copro.h | 6 ++
arch/powerpc
ement though.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/sysdev/msi_bitmap.c | 36 +---
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/sysdev/msi_bitmap.c b/arch/powerpc/sysdev/msi_bitmap.c
index 2f
From: Ian Munsie
Export mmu_kernel_ssize and mmu_linear_psize. These are needed by the cxl
driver which has it's own MMU. To setup the MMU cxl needs access to these.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/mm/hash_utils_64.c | 2 ++
1 file chang
From: Ian Munsie
Some of the MSI IRQ code in pnv_pci_ioda_msi_setup() is generically useful so
split it out.
This will be used by some of the cxl PCIe code later.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/platforms/powernv/pci-ioda.c | 42
SE is not enabled.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
include/misc/cxl.h | 48
1 file changed, 48 insertions(+)
create mode 100644 include/misc/cxl.h
diff --git a/include/misc/cxl.h b/include/misc/cxl.h
new file mode 1
From: Ian Munsie
This adds a number of functions for allocating IRQs under powernv PCIe for cxl.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/pnv-pci.h| 31 ++
arch/powerpc/platforms/powernv/pci-ioda.c | 154
be careful here as the current hash_page() assumes current in a few
places.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/mmu-hash64.h | 1 +
arch/powerpc/mm/hash_utils_64.c | 24 +---
2 files changed, 18 insertions(+), 7
From: Ian Munsie
This adds the OPAL call to change a PHB into cxl mode.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/opal.h| 2 ++
arch/powerpc/platforms/powernv/opal-wrappers.S | 1 +
2 files changed, 3 insertions(+)
diff --git a
when SLBs are invalidated. This ensures any
corresponding SLBs in cxl are also invalidated at the same time. This is
required for segment demotion.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/mm/copro_fault.c| 2 ++
arch/powerpc/mm/hash_native_64.c | 6 +-
2
CONFIG_SPU_BASE.
This adds a cxl_slbia() call (similar to spu_flush_all_slbs()) which checks if
the cxl module is loaded and in use, returning immediately if it is not. If it
is in use it calls into the cxl SLB invalidation code.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
drivers/misc
in
Documentation/powerpc/cxl.txt.
It also adds this new userspace header file to Kbuild so it's exported when
doing "make headers_installs".
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
include/uapi/Kbuild | 1 +
include/uapi/misc/Kbuild | 2 ++
include/
From: Ian Munsie
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
drivers/misc/cxl/Kconfig | 17 +
drivers/misc/cxl/Makefile | 2 ++
2 files changed, 19 insertions(+)
diff --git a/drivers/misc/cxl/Kconfig b/drivers/misc/cxl/Kconfig
index 5cdd319..a990b39 100644
From: Ian Munsie
This documentation gives an overview of the hardware architecture, userspace
APIs via /dev/cxl/afuM.N and the syfs files. It also adds a MAINTAINERS file
entry for cxl.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
Documentation/ABI/testing/sysfs-class-cxl
> The hypervisor returns H_P2 if relocation on exceptions are
> not supported. If we get this, just print a lower priority
> informational message.
Can you add something about why this is needed? Something about
h_set_mode being available so we can enable LE but not supporting any of
the other ca
: Michael Neuling
--
mpe: This might help us find some bugs in v3.18, but it's probably
better suited for your next tree.
diff --git a/arch/powerpc/configs/pseries_defconfig
b/arch/powerpc/configs/pseries_defconfig
index dd2a9ca..de51828 100644
--- a/arch/powerpc/configs/pseries_defconfig
On Sun, 2014-11-02 at 20:02 +0530, Aneesh Kumar K.V wrote:
> Runtime disable transactional memory feature looking at pa-features
> device tree entry. We need to do this so that we can run a kernel
> built with TM config in PR mode.
I'm happy to turn this off but why do we need to do this in PR mo
> Remove the function mmio_size_show() that is not used anywhere.
Did you compile check this patch?
drivers/misc/cxl/sysfs.c:291:74: error: ‘mmio_size_show’ undeclared here (not
in a function)
It's used here:
static struct device_attribute afu_attrs[] = {
__ATTR_RO(mmi
ninitialized variable: hwirq
>
> Commit 80fa93fce37d ("cxl: Name interrupts in /proc/interrupt")
> introduced this error.
>
> This is a simple fix that removes the redundant increment.
>
> Signed-off-by: Colin Ian King
Thanks. Looks good.
Acked-By: Michael Neulin
Event Based Branching (EBB) is a new POWER8 feature to take asynchronous
userspace interrupt based on events. Currently on POWER8 these events can be
PMU overflows.
This patch series context switches the three new EBB SPRs which are:
- Event Based Branch Handler Register (EBBHR)
- Event Based Bra
.
Note we don't touch CPU_FTR_TM, because it is conditionally enabled if
the kernel is built with TM support.
Signed-off-by: Michael Ellerman
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/cputable.h |8
arch/powerpc/kernel/entry_64.S |4 ++--
2 files ch
This turns Event Based Branching (EBB) on in the Hypervisor Facility Status and
Control Register (HFSCR) and Facility Status and Control Register (FSCR).
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/reg.h|2 ++
arch/powerpc/kernel/cpu_setup_power.S |4 ++--
2
Signed-off-by: Matt Evans
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/processor.h |3 +++
arch/powerpc/include/asm/reg.h |3 +++
arch/powerpc/kernel/asm-offsets.c|3 +++
arch/powerpc/kernel/entry_64.S | 16
4 files changed, 25
Make sure that current->thread.reg exists before we deference it in
flush_hash_page.
Signed-off-by: Michael Neuling
Reported-by: John J Miller
Cc:
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 3e4c4ed..88ac0ee 100644
--- a/arch/powerpc/mm/hash_utils_6
Nishanth Aravamudan wrote:
> Now that we have AT_HWCAP2 support, start exposing some of the new
> POWER8 features via it.
>
> Signed-off-by: Nishanth Aravamudan
A few points:
We need a TAR bit as well, although this could be covered in 207?
For TM we need to turn it off if CONFIG_PPC_TRANSAC
Anshuman Khandual wrote:
> Fixing some conditions during BHRB entry processing.
I think we can simplify this a lot more... something like the below.
Also, this marks the "to" address as all 1s, which is better poison
value since it's possible to branch to/from 0x0.
diff --git a/arch/powerpc/pe
Check truncate_if_32bit() on final write to nip.
Signed-off-by: Michael Neuling
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index e15c521..99c7fc1 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -580,7 +580,7 @@ int __kprobes emulate_step(struct
Anshuman Khandual wrote:
> On 05/06/2013 04:41 PM, Michael Neuling wrote:
> > Anshuman Khandual wrote:
> >
> >> Fixing some conditions during BHRB entry processing.
> >
> > I think we can simplify this a lot more... something like the below.
> >
&g
Peter & Stephane,
We are plumbing the POWER8 Branch History Rolling Buffer (BHRB) into
struct perf_branch_entry.
Sometimes on POWER8 we may not be able to fill out the "to" address. We
initially thought of just making this 0, but it's feasible that this
could be a valid address to branch to.
T
Peter Zijlstra wrote:
> On Tue, May 07, 2013 at 11:35:28AM +1000, Michael Neuling wrote:
> > Peter & Stephane,
> >
> > We are plumbing the POWER8 Branch History Rolling Buffer (BHRB) into
> > struct perf_branch_entry.
> >
> > Sometimes on POWER8 we m
Stephane Eranian wrote:
> On Wed, May 8, 2013 at 5:59 PM, Peter Zijlstra wrote:
> > On Tue, May 07, 2013 at 11:35:28AM +1000, Michael Neuling wrote:
> >> Peter & Stephane,
> >>
> >> We are plumbing the POWER8 Branch History Rolling Buffer (
This is a rewrite of the code to take this into account.
Signed-off-by: Michael Neuling
---
arch/powerpc/perf/core-book3s.c | 86 ---
1 file changed, 45 insertions(+), 41 deletions(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-boo
the offset of
a branch and calculate the target address.
This adds a function power_pmu_bhrb_to() to calculate the target/to address of
the corresponding I and B form branches. It handles branches in both user and
kernel spaces. It also plumbs this into the perf brhb reading code.
Signed-off-b
the offset of
a branch and calculate the target address.
This adds a function power_pmu_bhrb_to() to calculate the target/to address of
the corresponding I and B form branches. It handles branches in both user and
kernel spaces. It also plumbs this into the perf brhb reading code.
Signed-off-b
On Fri, May 10, 2013 at 8:43 PM, Peter Zijlstra wrote:
> On Thu, May 09, 2013 at 08:39:15AM +1000, Michael Neuling wrote:
>> > Just because I'm curious.. however does that happen? Surely the CPU
>> > knows where next to fetch instructions?
>>
>> For computed
David Woodhouse wrote:
> From: David Woodhouse
>
> Some versions of GCC apparently expect this to be provided by libgcc.
>
> Signed-off-by: David Woodhouse
> ---
> Untested.
>
> diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
> index 19e096b..f077dc2 100644
> --- a
From: David Woodhouse
Some versions of GCC apparently expect this to be provided by libgcc.
Updates from Mikey to fix 32 bit version and adding "r" to registers.
Signed-off-by: David Woodhouse
Signed-off-by: Michael Neuling
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powe
From: David Woodhouse
Some versions of GCC apparently expect this to be provided by libgcc.
Updates from Mikey to fix 32 bit version and adding "r" to registers.
Signed-off-by: David Woodhouse
Signed-off-by: Michael Neuling
---
Fixes from Gabriel.
arch/powerpc/kernel/misc_32.
101 - 200 of 1646 matches
Mail list logo
