Re: powerpc32: fix warning from include/linux/mm.h

Le 21/03/2015 00:52, Scott Wood a écrit : On Fri, Dec 05, 2014 at 12:20:20PM +0100, LEROY Christophe wrote: include/linux/mm.h: In function 'is_vmalloc_addr': include/linux/mm.h:367:14: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] r

Re: [PATCH v2 11/11] powerpc/8xx: Add support for TASK_SIZE greater than 0x80000000

Le 21/03/2015 01:47, Scott Wood a écrit : On Tue, 2015-01-20 at 10:57 +0100, Christophe Leroy wrote: By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely sufficient for most cases. However, kernel configuration allows to set TASK_SIZE to another value, so the 8xx shall h

Re: [PATCH 0/8] powerpc/8xx: Getting rid of CONFIG_8xx

Le 25/03/2015 01:45, Scott Wood a écrit : On Fri, 2015-03-13 at 10:34 +1100, Michael Ellerman wrote: On Thu, 2015-03-12 at 16:24 +0100, Christophe Leroy wrote: Two config options exist to define powerpc MPC8xx: * CONFIG_PPC_8xx * CONFIG_8xx In addition, CONFIG_PPC_8xx also defines CONFIG_CPM1

Re: [v3, 01/11] powerpc/8xx: remove remaining unnecessary code in FixupDAR

Le 26/03/2015 22:32, Scott Wood a écrit : On Tue, Feb 03, 2015 at 12:38:16PM +0100, LEROY Christophe wrote: Since commit 33fb845a6f01 ("powerpc/8xx: Don't use MD_TWC for walk"), MD_EPN and MD_TWC are not writen anymore in FixupDAR so saving r3 has become useless. Signed-off

Re: [v3, 01/11] powerpc/8xx: remove remaining unnecessary code in FixupDAR

Le 13/04/2015 22:26, Scott Wood a écrit : On Sun, 2015-04-12 at 18:16 +0200, leroy christophe wrote: Le 26/03/2015 22:32, Scott Wood a écrit : On Tue, Feb 03, 2015 at 12:38:16PM +0100, LEROY Christophe wrote: Since commit 33fb845a6f01 ("powerpc/8xx: Don't use MD_TWC for walk&quo

Re: [PATCH v3 00/17] crypto: talitos - Add support for SEC1

Oops, this is the first time I use directly the output of git format-patch into sendmail, and it looks like the mails are dated with the commit date, not today's date. I will resend now with today's date. Sorry for the noise. Christophe Le 17/04/2015 15:47, Christophe Leroy a écrit : The purp

Re: [PATCH v3 03/17] crypto: talitos - talitos_ptr renamed ptr for more lisibility

Le 17/04/2015 17:14, David Laight a écrit : From: Christophe Leroy Linux CodyingStyle recommends to use short variables for local variables. ptr is just good enough for those 3 lines functions. It helps keep single lines shorter than 80 characters. ... -static void to_talitos_ptr(struct talito

Re: [PATCH 00/11] powerpc8xx: Further optimisation of TLB handling

Le 20/04/2015 07:26, Christophe Leroy a écrit : This patchset provides a further optimisation of TLB handling in the 8xx. Main changes are based on: - Using processor handling of PGD/PTE Validity bits instead of testing ourselves the entries validity - Aligning PGD address to allow direct bit man

Re: [PATCH 07/11] powerpc/8xx: macro for handling CPU15 errata

Le 20/04/2015 13:40, David Laight a écrit : From: Christophe Leroy Sent: 20 April 2015 06:27 Having a macro will help keep clear code. ... * We have to use the MD_xxx registers for the tablewalk because the * equivalent MI_xxx registers only perform the attribute functions. */ + +#i

Re: [v2,2/2] powerpc32: add support for csum_add()

Le 05/05/2015 00:10, Segher Boessenkool a écrit : On Fri, May 01, 2015 at 08:00:14PM -0500, Scott Wood wrote: On Tue, 2015-04-28 at 21:01 +0200, christophe leroy wrote: The generated code is most likely different on ppc64. I have no ppc64 compiler For reference: yes you do. Just add -m64.

Re: Linux 3.16: all my drivers on SPI bus report WARNING: at drivers/base/dd.c:286

Le 19/08/2014 11:21, leroy christophe a écrit : Since Linux 3.16, for all drivers tied to SPI bus, I get the following warning on a PowerPC 8xx. It doesn't happen with Linux 3.15 What can be the reason / what should I look at ? [3.086957] device: 'spi32766.1': device_add [

Re: [PATCH] spi: fsl: Don't use devm_kzalloc in master->setup callback

0c6d0] ret_from_kernel_thread+0x5c/0x64 [3.285970] Instruction dump: [3.288900] 80de 419e01d0 3b7b0038 3c60c046 7f65db78 38635264 48211b99 813f00a0 [3.296559] 381f00a0 7d290278 3169 7c0b4910 <0f00> 93df0044 7fe3fb78 4bfffd4d Reported-by: leroy christophe Signed-off-by: Axel Lin -

Re: [PATCH v3 03/21] powerpc/8xx: exception InstructionAccess does not exist on MPC8xx

Le 18/09/2014 17:15, Joakim Tjernlund a écrit : Christophe Leroy wrote on 2014/09/17 18:36:57: Exception InstructionAccess does not exist on MPC8xx. No need to branch there from somewhere else. Handling can be done directly in InstructionTLBError Exception. Signed-off-by: Christophe Leroy

Re: [PATCH v3 03/21] powerpc/8xx: exception InstructionAccess does not exist on MPC8xx

Le 18/09/2014 22:02, Joakim Tjernlund a écrit : christophe leroy wrote on 2014/09/18 21:11:01: Le 18/09/2014 20:12, Joakim Tjernlund a écrit : leroy christophe wrote on 2014/09/18 18:42:14: Le 18/09/2014 17:15, Joakim Tjernlund a écrit : Christophe Leroy wrote on 2014/09/17 18:36:57

Looking for mpc8xx QMC driver

I'm looking for someone having some QMC driver and/or some experience with the QMC (QUICC Multichannel Controlleur) on mpc8xx. This is because we are trying to implement audio interface to codecs via the TDM bus using the QUICC. At the time being we are facing a major issue which is that after s

Re: [PATCH v2 1/2] spi: fsl-spi: Fix parameter ram offset setup for CPM1

Le 07/10/2014 02:15, Scott Wood a écrit : On Sat, 2014-10-04 at 14:02 +0200, christophe leroy wrote: Le 03/10/2014 22:29, Scott Wood a écrit : On Fri, 2014-10-03 at 18:49 +0200, Christophe Leroy wrote: On CPM1, the SPI parameter RAM has a default location. In fsl_spi_cpm_get_pram() there was

Re: [PATCH 2/2] spi: fsl-spi: Allow dynamic allocation of CPM1 parameter RAM

Le 07/10/2014 02:19, Scott Wood a écrit : On Sat, 2014-10-04 at 12:15 +0200, christophe leroy wrote: Le 03/10/2014 22:24, Scott Wood a écrit : On Fri, 2014-10-03 at 22:15 +0200, christophe leroy wrote: Le 03/10/2014 16:44, Mark Brown a écrit : On Fri, Oct 03, 2014 at 02:56:09PM +0200, Christ

Re: [PATCH 0/2] net: fs_enet: Remove non NAPI RX and add NAPI for TX

Le 08/10/2014 22:03, David Miller a écrit : From: Christophe Leroy Date: Tue, 7 Oct 2014 15:04:53 +0200 (CEST) When using a MPC8xx as a router, 'perf' shows a significant time spent in fs_enet_interrupt() and fs_enet_start_xmit(). 'perf annotate' shows that the time spent in fs_enet_start_xm

Re: powerpc32: add support for csum_add()

Le 12/10/2014 18:22, Jochen Rollwagen a écrit : This patch https://lists.ozlabs.org/pipermail/linuxppc-dev/2014-September/121144.html only compiles after putting an #ifndef ARCH_HAS_CSUM_ADD around the definition in include/net/checksum.h This is missing from the patch This is already in

Re: [PATCH v3 00/21] powerpc/8xx: Optimise MMU TLB handling and add support of 16k pages

Le 17/09/2014 22:34, Scott Wood a écrit : On Wed, 2014-09-17 at 22:33 +0200, christophe leroy wrote: Le 17/09/2014 18:40, Scott Wood a écrit : On Wed, 2014-09-17 at 18:36 +0200, Christophe Leroy wrote: This patchset: 1) provides several MMU TLB handling optimisation on MPC8xx. 2) adds support

kernel 3.17 - perf build failure

LINK perf libperf.a(skip-callchain-idx.o): In function `arch_skip_callchain_idx': /root/gen/trunk/knl/tools/perf/arch/powerpc/util/skip-callchain-idx.c:250: undefined reference to `pr_debug' libperf.a(skip-callchain-idx.o): In function `check_return_addr': /root/gen/trunk/knl/tools/perf/ar

What is the reel purpose of in_beXX() and out_beXX() fonctions ?

Many drivers use in_be16(), in_be32(), out_be16(), out_be32(), etc to access to registrers in IO mapped memory. What is the real purpose of those functions, and are they really needed ? ioremap() maps the related areas as GUARDED, which means that accesses can't be speculative. So what is

Re: [v4,17/21] powerpc/8xx: set PTE bit 22 off TLBmiss

Le 07/11/2014 04:37, Scott Wood a écrit : On Fri, Sep 19, 2014 at 10:36:09AM +0200, LEROY Christophe wrote: No need to re-set this bit at each TLB miss. Let's set it in the PTE. Signed-off-by: Christophe Leroy --- Changes in v2: - None Changes in v3: - Removed PPC405 related macro

Re: [v2 PATCH 2/2] powerpc/8xx: use _PAGE_RO instead of _PAGE_RW

Le 18/12/2014 03:22, Scott Wood a écrit : On Wed, 2014-12-17 at 10:14 +0100, Christophe Leroy wrote: On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW Signed-off-by: Christophe Leroy --- v2 is

Re: [v2 PATCH 1/2] powerpc32: adds handling of _PAGE_RO

Le 18/12/2014 03:14, Scott Wood a écrit : On Wed, 2014-12-17 at 10:14 +0100, Christophe Leroy wrote: Some powerpc like the 8xx don't have a RW bit in PTE bits but a RO (Read Only) bit. This patch implements the handling of a _PAGE_RO flag to be used in place of _PAGE_RW Signed-off-by: Christ

Re: [v2 PATCH 1/2] powerpc32: adds handling of _PAGE_RO

Le 18/12/2014 03:14, Scott Wood a écrit : On Wed, 2014-12-17 at 10:14 +0100, Christophe Leroy wrote: Some powerpc like the 8xx don't have a RW bit in PTE bits but a RO (Read Only) bit. This patch implements the handling of a _PAGE_RO flag to be used in place of _PAGE_RW Signed-off-by: Christ

Re: [PATCH v3 2/2] powerpc/8xx: use _PAGE_RO instead of _PAGE_RW

Le 05/01/2015 19:12, Joakim Tjernlund a écrit : On Mon, 2014-12-22 at 11:14 +0100, Christophe Leroy wrote: On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW Signed-off-by: Christophe Leroy Hi

Re: [PATCH 09/11] powerpc/8xx: dont save CR in SCRATCH registers

Le 05/01/2015 19:30, Joakim Tjernlund a écrit : On Tue, 2014-12-16 at 16:03 +0100, Christophe Leroy wrote: CR only needs to be preserved when checking if we are handling a kernel address. So we can preserve CR in a register: - In ITLBMiss, check is done only when CONFIG_MODULES is defined. Othe

Re: [PATCH 05/11] powerpc/8xx: Optimise access to swapper_pg_dir

Le 06/01/2015 13:08, David Laight a écrit : On Tue, 2014-12-16 at 16:03 +0100, Christophe Leroy wrote: All accessed to PGD entries are done via 0(r11). By using lower part of swapper_pg_dir as load index to r11, we can remove the ori instruction. Signed-off-by: Christophe Leroy Nice :) Acked

Re: [BUG] mpc8323_rdb platform doesn't boot since kernel 3.16

Le 06/06/2015 17:32, Rob Herring a écrit : On Sat, Jun 6, 2015 at 6:20 AM, christophe leroy wrote: I've got a MPC8323 RDB evaluation platform from freescale kernel 4.0 doesn't boot kernel 3.16 doesn't boot kernel 3.15 boots ok I disected the issue down to your commit "of/fdt: Convert FDT funct

Re: [BUG] mpc8323_rdb platform doesn't boot since kernel 3.16

Le 10/06/2015 20:17, Rob Herring a écrit : On Wed, Jun 10, 2015 at 10:12 AM, leroy christophe wrote: Le 06/06/2015 17:32, Rob Herring a écrit : On Sat, Jun 6, 2015 at 6:20 AM, christophe leroy wrote: I've got a MPC8323 RDB evaluation platform from freescale kernel 4.0 doesn't b

Oops in 3.18.14 in destroy_inode()

[46796.501487] Unable to handle kernel paging request for data at address 0x02dd [46796.514365] Faulting instruction address: 0xc00c5978 [46796.524217] Oops: Kernel access of bad area, sig: 11 [#1] [46796.529351] PREEMPT CMPC885 [46796.532144] CPU: 0 PID: 1107 Comm: snmpd Not tainted 3.18.14

Re: [HELP/RFC] Moving ppc8xx microcode patch from micropatch.c to firmware

Le 30/06/2015 22:38, christophe leroy a écrit : I'm trying to move the 3 microcode patches included in arch/powerpc/sysdev/micropatch.c into the firmware directory in order to use request_firmware() and then be able to add additional micropatch that I need to relocate SMC2 on my MPC885. I've n

Re: Missing Linux patches

Le 02/08/2015 21:05, Markus Stockhausen a écrit : Hi Christophe, I saw that this patch from you is still missing in Linux mainline: https://lists.ozlabs.org/pipermail/linuxppc-dev/2014-September/121144.html Is there any reason for not using it? Markus Hi, I sent v3 of that Patch on 19 May

Re: [PATCH v2 2/2] powerpc32: optimise csum_partial() loop

Le 07/08/2015 01:25, Segher Boessenkool a écrit : On Thu, Aug 06, 2015 at 05:45:45PM -0500, Scott Wood wrote: If this makes performance non-negligibly worse on other 32-bit chips, and is an important improvement on 8xx, then we can use an ifdef since 8xx already requires its own kernel build.

Re: [PATCH v2 2/2] powerpc32: optimise csum_partial() loop

Le 17/08/2015 12:56, leroy christophe a écrit : Le 07/08/2015 01:25, Segher Boessenkool a écrit : On Thu, Aug 06, 2015 at 05:45:45PM -0500, Scott Wood wrote: If this makes performance non-negligibly worse on other 32-bit chips, and is an important improvement on 8xx, then we can use an

Re: [PATCH v2 2/2] powerpc32: optimise csum_partial() loop

Le 17/08/2015 13:00, leroy christophe a écrit : Le 17/08/2015 12:56, leroy christophe a écrit : Le 07/08/2015 01:25, Segher Boessenkool a écrit : On Thu, Aug 06, 2015 at 05:45:45PM -0500, Scott Wood wrote: If this makes performance non-negligibly worse on other 32-bit chips, and is an

Re: [v2] Enhanced support for MPC8xx/8xxx watchdog

Le 26/06/2013 01:04, Scott Wood a écrit : On Thu, Feb 28, 2013 at 09:52:22AM +0100, LEROY Christophe wrote: This patch modifies the behaviour of the MPC8xx/8xxx watchdog. On the MPC8xx, at 133Mhz, the maximum timeout of the watchdog timer is 1s, which means it must be pinged twice a second

Feedback wished on possible improvment of CPU15 errata handling on mpc8xx

The mpc8xx powerpc has an errata identified CPU15 which is that whenever the last instruction of a page is a conditional branch to the last instruction of the next page, the CPU might do crazy things. To work around this errata, one of the workarounds proposed by freescale is: "In the ITLB miss

Re: Feedback wished on possible improvment of CPU15 errata handling on mpc8xx

Le 29/08/2013 19:57, Joakim Tjernlund a écrit : "Linuxppc-dev" wrote on 2013/08/29 19:11:48: The mpc8xx powerpc has an errata identified CPU15 which is that whenever the last instruction of a page is a conditional branch to the last instruction of the next page, the CPU might do crazy things.

Re: [PATCH] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB

Le 12/09/2013 02:15, Benjamin Herrenschmidt a écrit : On Wed, 2013-09-11 at 17:36 -0500, Scott Wood wrote: I wonder why we don't start from entry 31 so we can actually make use of that autodecrement. What will happen when we load the first normal TLB entry later on? I don't see any setting of

Re: [PATCH v2] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB

Le 12/09/2013 20:44, Scott Wood a écrit : On Thu, 2013-09-12 at 20:25 +0200, Christophe Leroy wrote: This is a reorganisation of the setup of the TLB at kernel startup, in order to handle the CONFIG_PIN_TLB case in accordance with chapter 8.10.3 of MPC866 and MPC885 reference manuals. Signed-of

Re: [PATCH v2] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB

Le 16/09/2013 23:02, Scott Wood a écrit : On Fri, 2013-09-13 at 07:04 +0200, leroy christophe wrote: Le 12/09/2013 20:44, Scott Wood a écrit : On Thu, 2013-09-12 at 20:25 +0200, Christophe Leroy wrote: This is a reorganisation of the setup of the TLB at kernel startup, in order to handle the

Re: [PATCH v2] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB

Le 20/09/2013 23:22, Scott Wood a écrit : The hardware wants to decrement; why fight it? >I see your point. >However it is not clear in the documentation if the decrement is done >really after the update, or at xTLB interrupt. So I propose to still set >the CTR ourself as described in the refer

Re: [PATCH] powerpc 8xx: Fixing memory init issue with CONFIG_PIN_TLB

Le 11/10/2013 17:13, Joakim Tjernlund a écrit : "Linuxppc-dev" wrote on 2013/10/11 14:56:40: Activating CONFIG_PIN_TLB allows access to the 24 first Mbytes of memory at bootup instead of 8. It is needed for "big" kernels for instance when activating CONFIG_LOCKDEP_SUPPORT. This needs to be

Re: [PATCH] powerpc 8xx: Fixing memory init issue with CONFIG_PIN_TLB

Le 15/10/2013 22:33, Scott Wood a écrit : On Tue, 2013-10-15 at 18:27 +0200, leroy christophe wrote: Le 11/10/2013 17:13, Joakim Tjernlund a écrit : "Linuxppc-dev" wrote on 2013/10/11 14:56:40: Activating CONFIG_PIN_TLB allows access to the 24 first Mbytes of memory at bootup in

Re: [PATCH] Enhanced support for MPC8xx/8xxx watchdog

Hi Wim, Le 27/02/2013 20:52, Wim Van Sebroeck a écrit : The rest of the code is OK and when above comments are corrected, I will add the patch to improve the userspace experience. Kind regards, Wim. Ok, I'll fix and re-submit my patch according to your comments. Best regards Christophe _

Linux 3.16: all my drivers on SPI bus report WARNING: at drivers/base/dd.c:286

Since Linux 3.16, for all drivers tied to SPI bus, I get the following warning on a PowerPC 8xx. It doesn't happen with Linux 3.15 What can be the reason / what should I look at ? [3.086957] device: 'spi32766.1': device_add [3.087179] bus: 'spi': add device spi32766.1 [3.087653] bus

BUG: Patch "Convert some mftb/mftbu into mfspr" breaks MPC885

Scott, The patch "Convert some mftb/mftbu into mfspr" (beb2dc0a7a84be003ce54e98b95d65cc66e6e536) breaks startup on MPC885. The CPU traps (SoftwareEmulation trap) at sched_clock() when trying to read TBU with mfspr. Reverting the patch solves the issue. What's the prefered way to fix this ?

BUG: Patch "Convert some mftb/mftbu into mfspr" breaks MPC885

Scott, The patch "Convert some mftb/mftbu into mfspr" (beb2dc0a7a84be003ce54e98b95d65cc66e6e536 ) breaks startup on MPC885. The CPU traps (Softwa

Re: [PATCH] watchdog: mpc8xxx_wdt convert to watchdog core

Le 01/12/2013 20:38, Guenter Roeck a écrit : On 11/30/2013 07:33 AM, Christophe Leroy wrote: Convert mpc8xxx_wdt.c to the new watchdog API. Signed-off-by: Christophe Leroy diff -ur a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c --- a/drivers/watchdog/mpc8xxx_wdt.c2013

Re: [PATCH v2] powerpc 8xx: Loading kernels over 8Mbytes without CONFIG_PIN_TLB

Le 10/12/2013 23:24, Scott Wood a écrit : On Tue, 2013-12-10 at 12:29 +0100, Christophe Leroy wrote: Today, the only way to load kernels whose size is greater than 8Mbytes is to activate CONFIG_PIN_TLB. Otherwise, the physical memory initially mapped is limited to 8Mbytes. This patch adds the c

Re: [PATCH v2] powerpc 8xx: Loading kernels over 8Mbytes without CONFIG_PIN_TLB

Le 11/12/2013 00:18, Scott Wood a écrit : On Wed, 2013-12-11 at 00:05 +0100, leroy christophe wrote: Le 10/12/2013 23:24, Scott Wood a écrit : On Tue, 2013-12-10 at 12:29 +0100, Christophe Leroy wrote: Today, the only way to load kernels whose size is greater than 8Mbytes is to activate

Re: [PATCH v2] powerpc 8xx: Loading kernels over 8Mbytes without CONFIG_PIN_TLB

Le 16/12/2013 23:57, Scott Wood a écrit : On Wed, 2013-12-11 at 00:36 +0100, leroy christophe wrote: Le 11/12/2013 00:18, Scott Wood a écrit : There wasn't previously an ifdef specifically around the setting of SPRN_MD_CTR. That's new. There was an ifdef around the entire block,

Re: [PATCH v2 07/11] powerpc/8xx: macro for handling CPU15 errata

Le 20/01/2015 12:09, David Laight a écrit : From Christophe Leroy Having a macro will help keep clear code. It might remove an #if but it doesn't really help. All it means is that anyone reading the code has to hunt for the definition before proceeding. Some comment about what (and why) the

cacheable_memcpy() versus memcpy() ==> 8% improvment on FTP throughput

In powerpc32 architecture we have a function called cacheable_memcpy() which does same thing as memcpy() but using dcbz/dcbt instructions for an optimised copy (just like __copy_tofrom_user()) What seems strange is that it is almost nowhere used (only used in drivers/net/ethernet/ibm/emac/core.c

[QUESTION,RFC] cacheable_memcpy() versus memcpy() ==> 8% improvment on FTP throughput

In powerpc32 architecture there is a function called cacheable_memcpy() which does same thing as memcpy() but using dcbz/dcbt instructions for an optimised copy (just like __copy_tofrom_user()) What seems strange is that it is almost nowhere used (only used in drivers/net/ethernet/ibm/emac/core.

Re: [PATCH] spi: fsl-spi: use of_iomap() to map parameter ram on CPM1

Le 03/03/2015 19:44, Mark Brown a écrit : On Thu, Feb 26, 2015 at 05:11:42PM +0100, Christophe Leroy wrote: On CPM2, the SPI parameter RAM is dynamically allocated in the dualport RAM whereas in CPM1, it is statically allocated to a default address with capability to relocate it somewhere else v

Re: [PATCH 0/17] crypto: talitos - Add support for SEC1

Le 06/03/2015 01:21, Kim Phillips a écrit : On Thu, 5 Mar 2015 17:46:05 +0100 Christophe Leroy wrote: [15/17] crypto: talitos - Implementation of SEC1 ... [16/17] crypto: talitos - SEC1 bugs on 0 data hash [17/17] crypto: talitos - Update DT bindings with SEC1 This patchseries doesn't ap

Re: [PATCH 0/17] crypto: talitos - Add support for SEC1

Le 06/03/2015 01:28, Herbert Xu a écrit : On Thu, Mar 05, 2015 at 06:21:01PM -0600, Kim Phillips wrote: On Thu, 5 Mar 2015 17:46:05 +0100 Christophe Leroy wrote: [15/17] crypto: talitos - Implementation of SEC1 ... [16/17] crypto: talitos - SEC1 bugs on 0 data hash [17/17] crypto: talitos

Re: [PATCH] spi: fsl-spi: use of_iomap() to map parameter ram on CPM1

Le 06/03/2015 12:44, Mark Brown a écrit : On Wed, Mar 04, 2015 at 09:00:39AM +0100, leroy christophe wrote: Le 03/03/2015 19:44, Mark Brown a écrit : Why are we using of_iomap() rather than a generic I/O mapping function here? because all drivers for powerpc seems to be using of_iomap(), as

Strange reports of perf events on powerpc 83xx

Hi, Has anybody already used 'perf' tool on powerpc MPC83xx ? I have been succesfully using perf on MPC8xx, but on MPC83xx I get something strange. perf record/report reports addresses on user stack, as if it was mixing up D accesses and I accesses. Any idea of what the problem can be ? #

Re: powerpc32 boot crash in 5.1-rc1

Meelis Roos a écrit : While 5.0.0 worked fine on my PowerMac G4, 5.0 + git (unknown rev as of Mar 13), 5.0.0-11520-gf261c4e and todays git all fail to boot. The problem seems to be in page fault handler in load_elf_binary() of init process. The patch at https://patchwork.ozlabs.org/patch

Re: powerpc32 boot crash in 5.1-rc1

Meelis Roos a écrit : While 5.0.0 worked fine on my PowerMac G4, 5.0 + git (unknown rev as of Mar 13), 5.0.0-11520-gf261c4e and todays git all fail to boot. The problem seems to be in page fault handler in load_elf_binary() of init process. The patch at https://patchwork.ozlabs.org/patch

Re: [PATCH] compiler: allow all arches to enable CONFIG_OPTIMIZE_INLINING

Arnd Bergmann a écrit : On Wed, Mar 20, 2019 at 10:41 AM Arnd Bergmann wrote: I've added your patch to my randconfig test setup and will let you know if I see anything noticeable. I'm currently testing clang-arm32, clang-arm64 and gcc-x86. This is the only additional bug that has come up s

Re: [PATCH] compiler: allow all arches to enable CONFIG_OPTIMIZE_INLINING

Masahiro Yamada a écrit : Commit 60a3cdd06394 ("x86: add optimized inlining") introduced CONFIG_OPTIMIZE_INLINING, but it has been available only for x86. The idea is obviously arch-agnostic although we need some code fixups. This commit moves the config entry from arch/x86/Kconfig.debug to li

Re: [PATCH v2] powerpc/tm: Print 64-bits MSR

Breno Leitao a écrit : Hi, On 08/07/2018 02:15 PM, Christophe LEROY wrote: Le 07/08/2018 à 15:35, Breno Leitao a écrit : On a kernel TM Bad thing program exception, the Machine State Register (MSR) is not being properly displayed. The exception code dumps a 32-bits value but MSR is a 64 bits

Re: [PATCH net] powerpc: use big endian to hash len and proto in csum_ipv6_magic

Xin Long a écrit : The function csum_ipv6_magic doesn't convert len and proto to big endian before doing ipv6 csum hash, which is not consistent with RFC and other arches. Jianlin found it when ICMPv6 packets from other hosts were dropped in the powerpc64 system. This patch is to fix it by us

Re: [PATCH v3 06/24] powerpc/mm: properly set PAGE_KERNEL flags in ioremap()

Michael Ellerman a écrit : Christophe Leroy writes: Set PAGE_KERNEL directly in the caller and do not rely on a hack adding PAGE_KERNEL flags when _PAGE_PRESENT is not set. As already done for PPC64, use pgprot_cache() helpers instead of _PAGE_XXX flags in PPC32 ioremap() derived functions.

Re: [PATCH v3 06/24] powerpc/mm: properly set PAGE_KERNEL flags in ioremap()

Michael Ellerman a écrit : Michael Ellerman writes: Christophe Leroy writes: Set PAGE_KERNEL directly in the caller and do not rely on a hack adding PAGE_KERNEL flags when _PAGE_PRESENT is not set. As already done for PPC64, use pgprot_cache() helpers instead of _PAGE_XXX flags in PPC32

Re: [PATCH v3 06/24] powerpc/mm: properly set PAGE_KERNEL flags in ioremap()

LEROY Christophe a écrit : Michael Ellerman a écrit : Christophe Leroy writes: Set PAGE_KERNEL directly in the caller and do not rely on a hack adding PAGE_KERNEL flags when _PAGE_PRESENT is not set. As already done for PPC64, use pgprot_cache() helpers instead of _PAGE_XXX flags in

Re: [PATCH 3/9] powerpc/mm: Remove extern from function definition

Breno Leitao a écrit : Function huge_ptep_set_access_flags() has the 'extern' keyword in the function definition and also in the function declaration. This causes a warning in 'sparse' since the 'extern' storage class should be used only on symbol declarations. arch/powerpc/mm/pgtable.c:232:1

Re: [PATCH 3/9] powerpc/mm: Remove extern from function definition

Breno Leitao a écrit : hi Christophe, On 10/23/2018 12:38 PM, LEROY Christophe wrote: Breno Leitao a écrit : This patch removes the keyword from the definition part, while keeps it in the declaration part. I think checkpatch also says that extern should be avoided in declarations

Re: [PATCH 0/5] Guarded Userspace Access Prevention on Radix

Russell Currey a écrit : Guarded Userspace Access Prevention is a security mechanism that prevents the kernel from being able to read and write userspace addresses outside of the allowed paths, most commonly copy_{to/from}_user(). At present, the only CPU that supports this is POWER9, and only

Re: [PATCH 2/5] powerpc/futex: GUAP support for futex ops

Russell Currey a écrit : Wrap the futex operations in GUAP locks and unlocks. Does it means futex doesn't work anymore once only patch 1 is applied ? If so, then you should split patch 1 in two parts and reorder patches so that guap can only be activated once all necessary changes are d

Re: [PATCH 3/5] powerpc/lib: checksum GUAP support

Same comment as for futex Christophe Russell Currey a écrit : Wrap the checksumming code in GUAP locks and unlocks. Signed-off-by: Russell Currey --- arch/powerpc/lib/checksum_wrappers.c | 4 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/lib/checksum_wrappers.c b/arch/p

Re: [PATCH 5/5] powerpc/64s: Document that PPC supports nosmap

Why not call our new functionnality SMAP instead of calling it GUAP ? Christophe Russell Currey a écrit : Signed-off-by: Russell Currey --- Documentation/admin-guide/kernel-parameters.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-pa

Re: [PATCH 1/5] powerpc/64s: Guarded Userspace Access Prevention

Russell Currey a écrit : Guarded Userspace Access Prevention (GUAP) utilises a feature of the Radix MMU which disallows read and write access to userspace addresses. By utilising this, the kernel is prevented from accessing user data from outside of trusted paths that perform proper safety ch

Re: NXP P50XX/e5500: SMP doesn't work anymore with the latest Git kernel

Christian Zigotzky a écrit : Hello, I figured out that the problem is in the OF source code of the commit: Merge tag devicetree-for-4.20. [1] That's a merge commit. Can you bisect the branch and identify the faulting commit ? Christophe I reverted the following OF files and SMP work

Re: [PATCH 1/5] powerpc/64s: Guarded Userspace Access Prevention

Russell Currey a écrit : On Sun, 2018-10-28 at 18:57 +0100, LEROY Christophe wrote: Russell Currey a écrit : > Guarded Userspace Access Prevention (GUAP) utilises a feature of > the Radix MMU which disallows read and write access to userspace > addresses. By utilising this, the

Re: [PATCH 0/5] Guarded Userspace Access Prevention on Radix

Russell Currey a écrit : On Fri, 2018-10-26 at 18:29 +0200, LEROY Christophe wrote: Russell Currey a écrit : > Guarded Userspace Access Prevention is a security mechanism that > prevents > the kernel from being able to read and write userspace addresses > outside of > th

Re: [PATCH 5/5] powerpc/64s: Document that PPC supports nosmap

Russell Currey a écrit : On Fri, 2018-10-26 at 18:35 +0200, LEROY Christophe wrote: Why not call our new functionnality SMAP instead of calling it GUAP ? mpe wasn't a fan of using the same terminology as other architectures. I don't like too much the word 'guarded&#x

Re: [PATCH v8 01/25] scsi/atari_scsi: Don't select CONFIG_NVRAM

Finn Thain a écrit : On powerpc, setting CONFIG_NVRAM=n builds a kernel with no NVRAM support. Setting CONFIG_NVRAM=m enables the /dev/nvram misc device module without enabling NVRAM support in drivers. Setting CONFIG_NVRAM=y enables the misc device (built-in) and also enables NVRAM support in

Re: [PATCH v8 02/25] m68k/atari: Move Atari-specific code out of drivers/char/nvram.c

Finn Thain a écrit : Move the m68k-specific code out of the driver to make the driver generic. I've used 'SPDX-License-Identifier: GPL-2.0+' for the new file because the old file is covered by MODULE_LICENSE("GPL"). Signed-off-by: Finn Thain Tested-by: Christian T. Steigies Acked-by: Geert

Re: [PATCH v8 01/25] scsi/atari_scsi: Don't select CONFIG_NVRAM

Michael Schmitz a écrit : Hi Finn, Am 29.12.2018 um 14:06 schrieb Finn Thain: On Fri, 28 Dec 2018, LEROY Christophe wrote: diff --git a/drivers/scsi/atari_scsi.c b/drivers/scsi/atari_scsi.c index 89f5154c40b6..99e5729d910d 100644 --- a/drivers/scsi/atari_scsi.c +++ b/drivers/scsi

Re: [PATCH v8 20/25] powerpc, fbdev: Use arch_nvram_ops methods instead of nvram_read_byte() and nvram_write_byte()

Finn Thain a écrit : Make use of arch_nvram_ops in device drivers so that the nvram_* function exports can be removed. Since they are no longer global symbols, rename the PPC32 nvram_* functions appropriately. Signed-off-by: Finn Thain --- arch/powerpc/kernel/setup_32.c | 8

Re: [PATCH v8 01/25] scsi/atari_scsi: Don't select CONFIG_NVRAM

Arnd Bergmann a écrit : On Sat, Dec 29, 2018 at 3:51 AM Michael Schmitz wrote: Hi Finn, Am 29.12.2018 um 15:34 schrieb Finn Thain: > On Sat, 29 Dec 2018, Michael Schmitz wrote: > >> >> IS_BUILTIN(CONFIG_NVRAM) is probably what Christophe really meant to suggest. >> >> Or (really going ou

Re: [PATCH v8 13/25] m68k: Dispatch nvram_ops calls to Atari or Mac functions

Finn Thain a écrit : On Sat, 29 Dec 2018, Arnd Bergmann wrote: On Wed, Dec 26, 2018 at 1:43 AM Finn Thain wrote: > + > +static ssize_t m68k_nvram_get_size(void) > +{ > + if (MACH_IS_ATARI) > + return atari_nvram_get_size(); > + else if (MACH_IS_MAC) > +

Re: [PATCH 1/2] powerpc/4xx/ocm: Fix phys_addr_t printf warnings

Michael Ellerman a écrit : Currently the code produces several warnings, eg: arch/powerpc/platforms/4xx/ocm.c:240:38: error: format '%llx' expects argument of type 'long long unsigned int', but argument 3 has type 'phys_addr_t {aka unsigned int}' seq_printf(m, "PhysAddr : 0x%llx

Re: [PATCH v5] soc/fsl/qe: fix err handling of ucc_of_parse_tdm

Peng Hao a écrit : From: Wen Yang Currently there are some issues with the ucc_of_parse_tdm function: 1, a possible null pointer dereference in ucc_of_parse_tdm, detected by the semantic patch deref_null.cocci, with the following warning: drivers/soc/fsl/qe/qe_tdm.c:177:21-24: ERROR: pdev is

Re: [PATCH v3 1/2] selftests/powerpc: Add MSR bits

Breno Leitao a écrit : This patch simply adds definitions for the MSR bits and some macros to test for MSR TM bits. This was copied from arch/powerpc/include/asm/reg.h generic MSR part. Can't we find a way to avoid duplicating such defines ? Christophe Signed-off-by: Breno Leitao --- t

Re: [PATCH] Remove 'type' argument from access_ok() function

Mathieu Malaterre a écrit : In commit 05a4ab823983 ("powerpc/uaccess: fix warning/error with access_ok()") an attempt was made to remove a warning by referencing the variable `type`, however in commit 96d4f267e40f ("Remove 'type' argument from access_ok() function") the variable `type` has been

Re: [PATCH v13 00/10] powerpc: Switch to CONFIG_THREAD_INFO_IN_TASK

Michael Ellerman a écrit : Christophe Leroy writes: The purpose of this serie is to activate CONFIG_THREAD_INFO_IN_TASK which moves the thread_info into task_struct. Moving thread_info into task_struct has the following advantages: - It protects thread_info from corruption in the case of st

Re: [PATCH v4 0/6] powerpc/fsl: Speculation barrier for NXP PowerPC Book3E

Diana Craciun a écrit : Implement barrier_nospec for NXP PowerPC Book3E processors. Diana Craciun (6): Disable the speculation barrier from the command line Document nospectre_v1 kernel parameter. Make stf barrier PPC_BOOK3S_64 specific. Enable cpu vulnerabilities reporting for NXP PPC

Re: [PATCH v4 4/6] powerpc/fsl: Enable cpu vulnerabilities reporting for NXP PPC BOOK3E

Diana Craciun a écrit : The NXP PPC Book3E platforms are not vulnerable to meltdown and Spectre v4, so make them PPC_BOOK3S_64 specific. Signed-off-by: Diana Craciun --- History: v2-->v3 - used the existing functions for spectre v1/v2 arch/powerpc/Kconfig | 7 ++- arch/powerp

Re: [PATCH v4 4/6] powerpc/fsl: Enable cpu vulnerabilities reporting for NXP PPC BOOK3E

Diana Madalina Craciun a écrit : On 7/17/2018 7:47 PM, LEROY Christophe wrote: Diana Craciun a écrit : The NXP PPC Book3E platforms are not vulnerable to meltdown and Spectre v4, so make them PPC_BOOK3S_64 specific. Signed-off-by: Diana Craciun --- History: v2-->v3 - used the exist

Re: [PATCH 2/7] powerpc/traps: Return early in show_signal_msg()

Murilo Opsfelder Araujo a écrit : Modify logic of show_signal_msg() to return early, if possible. Replace printk_ratelimited() by printk() and a default rate limit burst to limit displaying unhandled signals messages. Can you explain more the benefits of this change ? Christophe Signed-o

Re: [PATCH 6/7] powerpc/traps: Print signal name for unhandled signals

Murilo Opsfelder Araujo a écrit : This adds a human-readable name in the unhandled signal message. Before this patch, a page fault looked like: Jul 11 16:04:11 localhost kernel: pandafault[6303]: unhandled signal 11 at 17d0 nip 161c lr 7fff93c55100 code 2 i

Re: [PATCH 7/7] powerpc/traps: Show instructions on exceptions

Murilo Opsfelder Araujo a écrit : Move show_instructions() declaration to arch/powerpc/include/asm/stacktrace.h and include asm/stracktrace.h in arch/powerpc/kernel/process.c, which contains the implementation. Modify show_instructions() not to call __kernel_text_address(), allowing userspa

Re: [PATCH v4 00/11] hugetlb: Factorize hugetlb architecture primitives

Alex Ghiti a écrit : Hi everyone, This is the result of the build for all arches tackled in this series rebased on 4.18-rc6: arm:     versatile_defconfig: without huge page OK     keystone_defconfig: with huge page OK arm64:     defconfig: with huge page OK ia64:     generi

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