Le 20/09/2013 23:22, Scott Wood a écrit :
The hardware wants to decrement; why fight it?
>I see your point.
>However it is not clear in the documentation if the decrement is done
>really after the update, or at xTLB interrupt. So I propose to still set
>the CTR ourself as described in the reference Manual and not assume that
>the HW decrements it.
It says "every update" -- do you have any reason to believe that's
wrong? It could be tested...
Ok. I just test it, and I observe the following: As we have set the
RSV4x bit, the CPU sets Mx_CTR to a value below 0x1c after each update:
* After writing entry 0x1c, Mx_CTR has value 0x1b
* After writing entry 0x1d, Mx_CTR has value 0x18
* After writing entry 0x1e, Mx_CTR has value 0x19
* After writing entry 0x1f, Mx_CTR has value 0x1a
Indeed the first version of my patch was complete, only the description
was not fully correct.
So, in order to minimise code churn, I will re-submit my initial patch
with a modified description.
Christophe
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